[linux-2.6-block.git] / drivers / watchdog / pic32-dmt.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * PIC32 deadman timer driver
 *
 * Purna Chandra Mandal <purna.mandal@microchip.com>
 * Copyright (c) 2016, Microchip Technology Inc.
 */
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/watchdog.h>

#include <asm/mach-pic32/pic32.h>

/* Deadman Timer Regs */
#define DMTCON_REG	0x00
#define DMTPRECLR_REG	0x10
#define DMTCLR_REG	0x20
#define DMTSTAT_REG	0x30
#define DMTCNT_REG	0x40
#define DMTPSCNT_REG	0x60
#define DMTPSINTV_REG	0x70

/* Deadman Timer Regs fields */
#define DMT_ON			BIT(15)
#define DMT_STEP1_KEY		BIT(6)
#define DMT_STEP2_KEY		BIT(3)
#define DMTSTAT_WINOPN		BIT(0)
#define DMTSTAT_EVENT		BIT(5)
#define DMTSTAT_BAD2		BIT(6)
#define DMTSTAT_BAD1		BIT(7)

/* Reset Control Register fields for watchdog */
#define RESETCON_DMT_TIMEOUT	BIT(5)

struct pic32_dmt {
	void __iomem	*regs;
	struct clk	*clk;
};

static inline void dmt_enable(struct pic32_dmt *dmt)
{
	writel(DMT_ON, PIC32_SET(dmt->regs + DMTCON_REG));
}

static inline void dmt_disable(struct pic32_dmt *dmt)
{
	writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG));
	/*
	 * Cannot touch registers in the CPU cycle following clearing the
	 * ON bit.
	 */
	nop();
}

static inline int dmt_bad_status(struct pic32_dmt *dmt)
{
	u32 val;

	val = readl(dmt->regs + DMTSTAT_REG);
	val &= (DMTSTAT_BAD1 | DMTSTAT_BAD2 | DMTSTAT_EVENT);
	if (val)
		return -EAGAIN;

	return 0;
}

static inline int dmt_keepalive(struct pic32_dmt *dmt)
{
	u32 v;
	u32 timeout = 500;

	/* set pre-clear key */
	writel(DMT_STEP1_KEY << 8, dmt->regs + DMTPRECLR_REG);

	/* wait for DMT window to open */
	while (--timeout) {
		v = readl(dmt->regs + DMTSTAT_REG) & DMTSTAT_WINOPN;
		if (v == DMTSTAT_WINOPN)
			break;
	}

	/* apply key2 */
	writel(DMT_STEP2_KEY, dmt->regs + DMTCLR_REG);

	/* check whether keys are latched correctly */
	return dmt_bad_status(dmt);
}

static inline u32 pic32_dmt_get_timeout_secs(struct pic32_dmt *dmt)
{
	unsigned long rate;

	rate = clk_get_rate(dmt->clk);
	if (rate)
		return readl(dmt->regs + DMTPSCNT_REG) / rate;

	return 0;
}

static inline u32 pic32_dmt_bootstatus(struct pic32_dmt *dmt)
{
	u32 v;
	void __iomem *rst_base;

	rst_base = ioremap(PIC32_BASE_RESET, 0x10);
	if (!rst_base)
		return 0;

	v = readl(rst_base);

	writel(RESETCON_DMT_TIMEOUT, PIC32_CLR(rst_base));

	iounmap(rst_base);
	return v & RESETCON_DMT_TIMEOUT;
}

static int pic32_dmt_start(struct watchdog_device *wdd)
{
	struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);

	dmt_enable(dmt);
	return dmt_keepalive(dmt);
}

static int pic32_dmt_stop(struct watchdog_device *wdd)
{
	struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);

	dmt_disable(dmt);

	return 0;
}

static int pic32_dmt_ping(struct watchdog_device *wdd)
{
	struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);

	return dmt_keepalive(dmt);
}

static const struct watchdog_ops pic32_dmt_fops = {
	.owner		= THIS_MODULE,
	.start		= pic32_dmt_start,
	.stop		= pic32_dmt_stop,
	.ping		= pic32_dmt_ping,
};

static const struct watchdog_info pic32_dmt_ident = {
	.options	= WDIOF_KEEPALIVEPING |
			  WDIOF_MAGICCLOSE,
	.identity	= "PIC32 Deadman Timer",
};

static struct watchdog_device pic32_dmt_wdd = {
	.info		= &pic32_dmt_ident,
	.ops		= &pic32_dmt_fops,
};

static void pic32_clk_disable_unprepare(void *data)
{
	clk_disable_unprepare(data);
}

static int pic32_dmt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;
	struct pic32_dmt *dmt;
	struct watchdog_device *wdd = &pic32_dmt_wdd;

	dmt = devm_kzalloc(dev, sizeof(*dmt), GFP_KERNEL);
	if (!dmt)
		return -ENOMEM;

	dmt->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(dmt->regs))
		return PTR_ERR(dmt->regs);

	dmt->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(dmt->clk)) {
		dev_err(dev, "clk not found\n");
		return PTR_ERR(dmt->clk);
	}

	ret = clk_prepare_enable(dmt->clk);
	if (ret)
		return ret;
	ret = devm_add_action_or_reset(dev, pic32_clk_disable_unprepare,
				       dmt->clk);
	if (ret)
		return ret;

	wdd->timeout = pic32_dmt_get_timeout_secs(dmt);
	if (!wdd->timeout) {
		dev_err(dev, "failed to read watchdog register timeout\n");
		return -EINVAL;
	}

	dev_info(dev, "timeout %d\n", wdd->timeout);

	wdd->bootstatus = pic32_dmt_bootstatus(dmt) ? WDIOF_CARDRESET : 0;

	watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
	watchdog_set_drvdata(wdd, dmt);

	ret = devm_watchdog_register_device(dev, wdd);
	if (ret) {
		dev_err(dev, "watchdog register failed, err %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, wdd);
	return 0;
}

static const struct of_device_id pic32_dmt_of_ids[] = {
	{ .compatible = "microchip,pic32mzda-dmt",},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pic32_dmt_of_ids);

static struct platform_driver pic32_dmt_driver = {
	.probe		= pic32_dmt_probe,
	.driver		= {
		.name		= "pic32-dmt",
		.of_match_table = of_match_ptr(pic32_dmt_of_ids),
	}
};

module_platform_driver(pic32_dmt_driver);

MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>");
MODULE_DESCRIPTION("Microchip PIC32 DMT Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
b0d8a082 PCM	2	/*
	3	* PIC32 deadman timer driver
	4	*
	5	* Purna Chandra Mandal <purna.mandal@microchip.com>
	6	* Copyright (c) 2016, Microchip Technology Inc.
b0d8a082 PCM	7	*/
	8	#include <linux/clk.h>
	9	#include <linux/device.h>
	10	#include <linux/err.h>
	11	#include <linux/io.h>
	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
	15	#include <linux/of_device.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/pm.h>
	18	#include <linux/watchdog.h>
	19
	20	#include <asm/mach-pic32/pic32.h>
	21
	22	/* Deadman Timer Regs */
	23	#define DMTCON_REG 0x00
	24	#define DMTPRECLR_REG 0x10
	25	#define DMTCLR_REG 0x20
	26	#define DMTSTAT_REG 0x30
	27	#define DMTCNT_REG 0x40
	28	#define DMTPSCNT_REG 0x60
	29	#define DMTPSINTV_REG 0x70
	30
	31	/* Deadman Timer Regs fields */
	32	#define DMT_ON BIT(15)
	33	#define DMT_STEP1_KEY BIT(6)
	34	#define DMT_STEP2_KEY BIT(3)
	35	#define DMTSTAT_WINOPN BIT(0)
	36	#define DMTSTAT_EVENT BIT(5)
	37	#define DMTSTAT_BAD2 BIT(6)
	38	#define DMTSTAT_BAD1 BIT(7)
	39
	40	/* Reset Control Register fields for watchdog */
	41	#define RESETCON_DMT_TIMEOUT BIT(5)
	42
	43	struct pic32_dmt {
	44	void __iomem *regs;
	45	struct clk *clk;
	46	};
	47
	48	static inline void dmt_enable(struct pic32_dmt *dmt)
	49	{
	50	writel(DMT_ON, PIC32_SET(dmt->regs + DMTCON_REG));
	51	}
	52
	53	static inline void dmt_disable(struct pic32_dmt *dmt)
	54	{
	55	writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG));
	56	/*
	57	* Cannot touch registers in the CPU cycle following clearing the
	58	* ON bit.
	59	*/
	60	nop();
	61	}
	62
	63	static inline int dmt_bad_status(struct pic32_dmt *dmt)
	64	{
	65	u32 val;
	66
	67	val = readl(dmt->regs + DMTSTAT_REG);
	68	val &= (DMTSTAT_BAD1 \| DMTSTAT_BAD2 \| DMTSTAT_EVENT);
	69	if (val)
	70	return -EAGAIN;
71
72	return 0;
73	}
74
75	static inline int dmt_keepalive(struct pic32_dmt *dmt)
76	{
77	u32 v;
78	u32 timeout = 500;
79
80	/* set pre-clear key */
81	writel(DMT_STEP1_KEY << 8, dmt->regs + DMTPRECLR_REG);
82
83	/* wait for DMT window to open */
84	while (--timeout) {
85	v = readl(dmt->regs + DMTSTAT_REG) & DMTSTAT_WINOPN;
86	if (v == DMTSTAT_WINOPN)
87	break;
88	}
89
90	/* apply key2 */
91	writel(DMT_STEP2_KEY, dmt->regs + DMTCLR_REG);
92
93	/* check whether keys are latched correctly */
94	return dmt_bad_status(dmt);
95	}
96
97	static inline u32 pic32_dmt_get_timeout_secs(struct pic32_dmt *dmt)
98	{
99	unsigned long rate;
100
101	rate = clk_get_rate(dmt->clk);
102	if (rate)
103	return readl(dmt->regs + DMTPSCNT_REG) / rate;
104
105	return 0;
106	}
107
108	static inline u32 pic32_dmt_bootstatus(struct pic32_dmt *dmt)
109	{
110	u32 v;
111	void __iomem *rst_base;
112
113	rst_base = ioremap(PIC32_BASE_RESET, 0x10);
114	if (!rst_base)
115	return 0;
116
117	v = readl(rst_base);
118
119	writel(RESETCON_DMT_TIMEOUT, PIC32_CLR(rst_base));
120
121	iounmap(rst_base);
122	return v & RESETCON_DMT_TIMEOUT;
123	}
124
125	static int pic32_dmt_start(struct watchdog_device *wdd)
126	{
127	struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
128
129	dmt_enable(dmt);
130	return dmt_keepalive(dmt);
131	}
132
133	static int pic32_dmt_stop(struct watchdog_device *wdd)
134	{
135	struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
136
137	dmt_disable(dmt);
138
139	return 0;
140	}
141
142	static int pic32_dmt_ping(struct watchdog_device *wdd)
143	{
144	struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
145
146	return dmt_keepalive(dmt);
147	}
148
149	static const struct watchdog_ops pic32_dmt_fops = {
150	.owner = THIS_MODULE,
151	.start = pic32_dmt_start,
152	.stop = pic32_dmt_stop,
153	.ping = pic32_dmt_ping,
154	};
155
156	static const struct watchdog_info pic32_dmt_ident = {
157	.options = WDIOF_KEEPALIVEPING \|
158	WDIOF_MAGICCLOSE,
159	.identity = "PIC32 Deadman Timer",
160	};
161
162	static struct watchdog_device pic32_dmt_wdd = {
163	.info = &pic32_dmt_ident,
164	.ops = &pic32_dmt_fops,
165	};
166
a02b3d7c GR	167	static void pic32_clk_disable_unprepare(void *data)
	168	{
	169	clk_disable_unprepare(data);
	170	}
	171
b0d8a082 PCM	172	static int pic32_dmt_probe(struct platform_device *pdev)
b0d8a082 PCM	173	{
a02b3d7c	174	struct device *dev = &pdev->dev;
b0d8a082 PCM	175	int ret;
b0d8a082 PCM	176	struct pic32_dmt *dmt;
b0d8a082 PCM	177	struct watchdog_device *wdd = &pic32_dmt_wdd;
b0d8a082 PCM	178
a02b3d7c	179	dmt = devm_kzalloc(dev, sizeof(*dmt), GFP_KERNEL);
fafdbaba WY	180	if (!dmt)
fafdbaba WY	181	return -ENOMEM;
b0d8a082	182
0f0a6a28	183	dmt->regs = devm_platform_ioremap_resource(pdev, 0);
b0d8a082 PCM	184	if (IS_ERR(dmt->regs))
	185	return PTR_ERR(dmt->regs);
	186
a02b3d7c	187	dmt->clk = devm_clk_get(dev, NULL);
b0d8a082	188	if (IS_ERR(dmt->clk)) {
a02b3d7c	189	dev_err(dev, "clk not found\n");
b0d8a082 PCM	190	return PTR_ERR(dmt->clk);
	191	}
	192
	193	ret = clk_prepare_enable(dmt->clk);
	194	if (ret)
	195	return ret;
a02b3d7c GR	196	ret = devm_add_action_or_reset(dev, pic32_clk_disable_unprepare,
	197	dmt->clk);
	198	if (ret)
	199	return ret;
b0d8a082 PCM	200
	201	wdd->timeout = pic32_dmt_get_timeout_secs(dmt);
	202	if (!wdd->timeout) {
a02b3d7c GR	203	dev_err(dev, "failed to read watchdog register timeout\n");
a02b3d7c GR	204	return -EINVAL;
b0d8a082 PCM	205	}
b0d8a082 PCM	206
a02b3d7c	207	dev_info(dev, "timeout %d\n", wdd->timeout);
b0d8a082 PCM	208
	209	wdd->bootstatus = pic32_dmt_bootstatus(dmt) ? WDIOF_CARDRESET : 0;
	210
	211	watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
	212	watchdog_set_drvdata(wdd, dmt);
	213
a02b3d7c	214	ret = devm_watchdog_register_device(dev, wdd);
b0d8a082	215	if (ret) {
a02b3d7c GR	216	dev_err(dev, "watchdog register failed, err %d\n", ret);
a02b3d7c GR	217	return ret;
b0d8a082 PCM	218	}
	219
	220	platform_set_drvdata(pdev, wdd);
	221	return 0;
b0d8a082 PCM	222	}
	223
	224	static const struct of_device_id pic32_dmt_of_ids[] = {
	225	{ .compatible = "microchip,pic32mzda-dmt",},
	226	{ /* sentinel */ }
	227	};
	228	MODULE_DEVICE_TABLE(of, pic32_dmt_of_ids);
	229
	230	static struct platform_driver pic32_dmt_driver = {
	231	.probe = pic32_dmt_probe,
b0d8a082 PCM	232	.driver = {
b0d8a082 PCM	233	.name = "pic32-dmt",
b0d8a082 PCM	234	.of_match_table = of_match_ptr(pic32_dmt_of_ids),
	235	}
	236	};
	237
	238	module_platform_driver(pic32_dmt_driver);
	239
	240	MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>");
	241	MODULE_DESCRIPTION("Microchip PIC32 DMT Driver");
	242	MODULE_LICENSE("GPL");