omap: headers: Create headers necessary for compile under mach-omap1 and mach-omap2
[linux-2.6-block.git] / drivers / watchdog / omap_wdt.c
CommitLineData
7768a13c 1/*
2817142f 2 * omap_wdt.c
7768a13c 3 *
2817142f 4 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
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5 *
6 * Author: MontaVista Software, Inc.
7 * <gdavis@mvista.com> or <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * History:
15 *
16 * 20030527: George G. Davis <gdavis@mvista.com>
17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
29fa0586 19 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
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20 *
21 * Copyright (c) 2004 Texas Instruments.
22 * 1. Modified to support OMAP1610 32-KHz watchdog timer
23 * 2. Ported to 2.6 kernel
24 *
25 * Copyright (c) 2005 David Brownell
26 * Use the driver model and standard identifiers; handle bigger timeouts.
27 */
28
29#include <linux/module.h>
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30#include <linux/types.h>
31#include <linux/kernel.h>
32#include <linux/fs.h>
33#include <linux/mm.h>
34#include <linux/miscdevice.h>
35#include <linux/watchdog.h>
36#include <linux/reboot.h>
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37#include <linux/init.h>
38#include <linux/err.h>
39#include <linux/platform_device.h>
40#include <linux/moduleparam.h>
41#include <linux/clk.h>
1977f032 42#include <linux/bitops.h>
089ab079 43#include <linux/io.h>
12b9df7d 44#include <linux/uaccess.h>
a09e64fb 45#include <mach/hardware.h>
a09e64fb 46#include <mach/prcm.h>
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47
48#include "omap_wdt.h"
49
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50static struct platform_device *omap_wdt_dev;
51
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52static unsigned timer_margin;
53module_param(timer_margin, uint, 0);
54MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
55
7768a13c 56static unsigned int wdt_trgr_pattern = 0x1234;
12b9df7d 57static spinlock_t wdt_lock;
7768a13c 58
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59struct omap_wdt_dev {
60 void __iomem *base; /* physical */
61 struct device *dev;
62 int omap_wdt_users;
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63 struct clk *ick;
64 struct clk *fck;
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65 struct resource *mem;
66 struct miscdevice omap_wdt_miscdev;
67};
68
69static void omap_wdt_ping(struct omap_wdt_dev *wdev)
7768a13c 70{
2817142f 71 void __iomem *base = wdev->base;
b3112180 72
7768a13c 73 /* wait for posted write to complete */
9f69e3b0 74 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c 75 cpu_relax();
b3112180 76
7768a13c 77 wdt_trgr_pattern = ~wdt_trgr_pattern;
9f69e3b0 78 __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
b3112180 79
7768a13c 80 /* wait for posted write to complete */
9f69e3b0 81 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
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82 cpu_relax();
83 /* reloaded WCRR from WLDR */
84}
85
2817142f 86static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c 87{
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88 void __iomem *base = wdev->base;
89
7768a13c 90 /* Sequence to enable the watchdog */
9f69e3b0
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91 __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
92 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c 93 cpu_relax();
b3112180 94
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95 __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
96 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
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97 cpu_relax();
98}
99
2817142f 100static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c 101{
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102 void __iomem *base = wdev->base;
103
7768a13c 104 /* sequence required to disable watchdog */
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105 __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
106 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c 107 cpu_relax();
b3112180 108
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109 __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
110 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
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111 cpu_relax();
112}
113
114static void omap_wdt_adjust_timeout(unsigned new_timeout)
115{
116 if (new_timeout < TIMER_MARGIN_MIN)
117 new_timeout = TIMER_MARGIN_DEFAULT;
118 if (new_timeout > TIMER_MARGIN_MAX)
119 new_timeout = TIMER_MARGIN_MAX;
120 timer_margin = new_timeout;
121}
122
2817142f 123static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
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124{
125 u32 pre_margin = GET_WLDR_VAL(timer_margin);
b3112180 126 void __iomem *base = wdev->base;
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127
128 /* just count up at 32 KHz */
9f69e3b0 129 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c 130 cpu_relax();
b3112180 131
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132 __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
133 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
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134 cpu_relax();
135}
136
137/*
138 * Allow only one task to hold it open
139 */
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140static int omap_wdt_open(struct inode *inode, struct file *file)
141{
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142 struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
143 void __iomem *base = wdev->base;
144
2817142f 145 if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
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146 return -EBUSY;
147
4c5e1946 148 clk_enable(wdev->ick); /* Enable the interface clock */
39a80c7f 149 clk_enable(wdev->fck); /* Enable the functional clock */
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150
151 /* initialize prescaler */
9f69e3b0 152 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c 153 cpu_relax();
b3112180 154
9f69e3b0
FB
155 __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
156 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
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157 cpu_relax();
158
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159 file->private_data = (void *) wdev;
160
161 omap_wdt_set_timeout(wdev);
789cd470 162 omap_wdt_ping(wdev); /* trigger loading of new timeout value */
2817142f 163 omap_wdt_enable(wdev);
b3112180 164
ec9505a7 165 return nonseekable_open(inode, file);
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166}
167
168static int omap_wdt_release(struct inode *inode, struct file *file)
169{
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170 struct omap_wdt_dev *wdev = file->private_data;
171
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172 /*
173 * Shut off the timer unless NOWAYOUT is defined.
174 */
175#ifndef CONFIG_WATCHDOG_NOWAYOUT
7768a13c 176
2817142f 177 omap_wdt_disable(wdev);
7768a13c 178
4c5e1946 179 clk_disable(wdev->ick);
39a80c7f 180 clk_disable(wdev->fck);
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181#else
182 printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
183#endif
2817142f 184 wdev->omap_wdt_users = 0;
b3112180 185
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186 return 0;
187}
188
12b9df7d 189static ssize_t omap_wdt_write(struct file *file, const char __user *data,
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190 size_t len, loff_t *ppos)
191{
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192 struct omap_wdt_dev *wdev = file->private_data;
193
7768a13c 194 /* Refresh LOAD_TIME. */
12b9df7d
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195 if (len) {
196 spin_lock(&wdt_lock);
2817142f 197 omap_wdt_ping(wdev);
12b9df7d
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198 spin_unlock(&wdt_lock);
199 }
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200 return len;
201}
202
12b9df7d
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203static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
204 unsigned long arg)
7768a13c 205{
2817142f 206 struct omap_wdt_dev *wdev;
7768a13c 207 int new_margin;
12b9df7d 208 static const struct watchdog_info ident = {
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209 .identity = "OMAP Watchdog",
210 .options = WDIOF_SETTIMEOUT,
211 .firmware_version = 0,
212 };
b3112180 213
2817142f 214 wdev = file->private_data;
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215
216 switch (cmd) {
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217 case WDIOC_GETSUPPORT:
218 return copy_to_user((struct watchdog_info __user *)arg, &ident,
219 sizeof(ident));
220 case WDIOC_GETSTATUS:
221 return put_user(0, (int __user *)arg);
222 case WDIOC_GETBOOTSTATUS:
223 if (cpu_is_omap16xx())
9f69e3b0 224 return put_user(__raw_readw(ARM_SYSST),
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225 (int __user *)arg);
226 if (cpu_is_omap24xx())
227 return put_user(omap_prcm_get_reset_sources(),
228 (int __user *)arg);
229 case WDIOC_KEEPALIVE:
12b9df7d 230 spin_lock(&wdt_lock);
2817142f 231 omap_wdt_ping(wdev);
12b9df7d 232 spin_unlock(&wdt_lock);
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233 return 0;
234 case WDIOC_SETTIMEOUT:
235 if (get_user(new_margin, (int __user *)arg))
236 return -EFAULT;
237 omap_wdt_adjust_timeout(new_margin);
238
12b9df7d 239 spin_lock(&wdt_lock);
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240 omap_wdt_disable(wdev);
241 omap_wdt_set_timeout(wdev);
242 omap_wdt_enable(wdev);
7768a13c 243
2817142f 244 omap_wdt_ping(wdev);
12b9df7d 245 spin_unlock(&wdt_lock);
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246 /* Fall */
247 case WDIOC_GETTIMEOUT:
248 return put_user(timer_margin, (int __user *)arg);
0c06090c
WVS
249 default:
250 return -ENOTTY;
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251 }
252}
253
2b8693c0 254static const struct file_operations omap_wdt_fops = {
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255 .owner = THIS_MODULE,
256 .write = omap_wdt_write,
12b9df7d 257 .unlocked_ioctl = omap_wdt_ioctl,
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258 .open = omap_wdt_open,
259 .release = omap_wdt_release,
260};
261
0e3912c7 262static int __devinit omap_wdt_probe(struct platform_device *pdev)
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263{
264 struct resource *res, *mem;
2817142f 265 struct omap_wdt_dev *wdev;
b3112180 266 int ret;
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267
268 /* reserve static register mappings */
269 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b3112180
FB
270 if (!res) {
271 ret = -ENOENT;
272 goto err_get_resource;
273 }
7768a13c 274
b3112180
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275 if (omap_wdt_dev) {
276 ret = -EBUSY;
277 goto err_busy;
278 }
2817142f 279
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280 mem = request_mem_region(res->start, res->end - res->start + 1,
281 pdev->name);
b3112180
FB
282 if (!mem) {
283 ret = -EBUSY;
284 goto err_busy;
285 }
7768a13c 286
2817142f
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287 wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
288 if (!wdev) {
289 ret = -ENOMEM;
b3112180 290 goto err_kzalloc;
2817142f 291 }
b3112180 292
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293 wdev->omap_wdt_users = 0;
294 wdev->mem = mem;
7768a13c 295
4c5e1946
RK
296 wdev->ick = clk_get(&pdev->dev, "ick");
297 if (IS_ERR(wdev->ick)) {
298 ret = PTR_ERR(wdev->ick);
299 wdev->ick = NULL;
300 goto err_clk;
7768a13c 301 }
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RK
302 wdev->fck = clk_get(&pdev->dev, "fck");
303 if (IS_ERR(wdev->fck)) {
304 ret = PTR_ERR(wdev->fck);
305 wdev->fck = NULL;
306 goto err_clk;
2817142f
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307 }
308
9f69e3b0
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309 wdev->base = ioremap(res->start, res->end - res->start + 1);
310 if (!wdev->base) {
311 ret = -ENOMEM;
b3112180 312 goto err_ioremap;
9f69e3b0
FB
313 }
314
2817142f 315 platform_set_drvdata(pdev, wdev);
7768a13c 316
789cd470
UBH
317 clk_enable(wdev->ick);
318 clk_enable(wdev->fck);
319
2817142f 320 omap_wdt_disable(wdev);
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321 omap_wdt_adjust_timeout(timer_margin);
322
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323 wdev->omap_wdt_miscdev.parent = &pdev->dev;
324 wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
325 wdev->omap_wdt_miscdev.name = "watchdog";
326 wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
327
328 ret = misc_register(&(wdev->omap_wdt_miscdev));
7768a13c 329 if (ret)
b3112180 330 goto err_misc;
7768a13c 331
2817142f 332 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
9f69e3b0 333 __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
2817142f 334 timer_margin);
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335
336 /* autogate OCP interface clock */
9f69e3b0 337 __raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG);
2817142f 338
789cd470
UBH
339 clk_disable(wdev->ick);
340 clk_disable(wdev->fck);
341
2817142f
FB
342 omap_wdt_dev = pdev;
343
7768a13c
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344 return 0;
345
b3112180
FB
346err_misc:
347 platform_set_drvdata(pdev, NULL);
348 iounmap(wdev->base);
349
350err_ioremap:
351 wdev->base = NULL;
352
353err_clk:
39a80c7f
RK
354 if (wdev->ick)
355 clk_put(wdev->ick);
356 if (wdev->fck)
357 clk_put(wdev->fck);
b3112180
FB
358 kfree(wdev);
359
360err_kzalloc:
361 release_mem_region(res->start, res->end - res->start + 1);
362
363err_busy:
364err_get_resource:
365
7768a13c
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366 return ret;
367}
368
369static void omap_wdt_shutdown(struct platform_device *pdev)
370{
b3112180 371 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f
FB
372
373 if (wdev->omap_wdt_users)
374 omap_wdt_disable(wdev);
7768a13c
KS
375}
376
0e3912c7 377static int __devexit omap_wdt_remove(struct platform_device *pdev)
7768a13c 378{
b3112180 379 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f
FB
380 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
381
382 if (!res)
383 return -ENOENT;
384
385 misc_deregister(&(wdev->omap_wdt_miscdev));
386 release_mem_region(res->start, res->end - res->start + 1);
387 platform_set_drvdata(pdev, NULL);
b3112180 388
4c5e1946 389 clk_put(wdev->ick);
39a80c7f 390 clk_put(wdev->fck);
9f69e3b0
FB
391 iounmap(wdev->base);
392
2817142f
FB
393 kfree(wdev);
394 omap_wdt_dev = NULL;
b3112180 395
7768a13c
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396 return 0;
397}
398
399#ifdef CONFIG_PM
400
401/* REVISIT ... not clear this is the best way to handle system suspend; and
402 * it's very inappropriate for selective device suspend (e.g. suspending this
403 * through sysfs rather than by stopping the watchdog daemon). Also, this
404 * may not play well enough with NOWAYOUT...
405 */
406
407static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
408{
b3112180
FB
409 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
410
2817142f
FB
411 if (wdev->omap_wdt_users)
412 omap_wdt_disable(wdev);
b3112180 413
7768a13c
KS
414 return 0;
415}
416
417static int omap_wdt_resume(struct platform_device *pdev)
418{
b3112180
FB
419 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
420
2817142f
FB
421 if (wdev->omap_wdt_users) {
422 omap_wdt_enable(wdev);
423 omap_wdt_ping(wdev);
7768a13c 424 }
b3112180 425
7768a13c
KS
426 return 0;
427}
428
429#else
430#define omap_wdt_suspend NULL
431#define omap_wdt_resume NULL
432#endif
433
434static struct platform_driver omap_wdt_driver = {
435 .probe = omap_wdt_probe,
0e3912c7 436 .remove = __devexit_p(omap_wdt_remove),
7768a13c
KS
437 .shutdown = omap_wdt_shutdown,
438 .suspend = omap_wdt_suspend,
439 .resume = omap_wdt_resume,
440 .driver = {
441 .owner = THIS_MODULE,
442 .name = "omap_wdt",
443 },
444};
445
446static int __init omap_wdt_init(void)
447{
12b9df7d 448 spin_lock_init(&wdt_lock);
7768a13c
KS
449 return platform_driver_register(&omap_wdt_driver);
450}
451
452static void __exit omap_wdt_exit(void)
453{
454 platform_driver_unregister(&omap_wdt_driver);
455}
456
457module_init(omap_wdt_init);
458module_exit(omap_wdt_exit);
459
460MODULE_AUTHOR("George G. Davis");
461MODULE_LICENSE("GPL");
462MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
f37d193c 463MODULE_ALIAS("platform:omap_wdt");