Commit | Line | Data |
---|---|---|
7768a13c | 1 | /* |
2817142f | 2 | * omap_wdt.c |
7768a13c | 3 | * |
2817142f | 4 | * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog |
7768a13c KS |
5 | * |
6 | * Author: MontaVista Software, Inc. | |
7 | * <gdavis@mvista.com> or <source@mvista.com> | |
8 | * | |
9 | * 2003 (c) MontaVista Software, Inc. This file is licensed under the | |
10 | * terms of the GNU General Public License version 2. This program is | |
11 | * licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | * | |
14 | * History: | |
15 | * | |
16 | * 20030527: George G. Davis <gdavis@mvista.com> | |
17 | * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c | |
18 | * (c) Copyright 2000 Oleg Drokin <green@crimea.edu> | |
29fa0586 | 19 | * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk> |
7768a13c KS |
20 | * |
21 | * Copyright (c) 2004 Texas Instruments. | |
22 | * 1. Modified to support OMAP1610 32-KHz watchdog timer | |
23 | * 2. Ported to 2.6 kernel | |
24 | * | |
25 | * Copyright (c) 2005 David Brownell | |
26 | * Use the driver model and standard identifiers; handle bigger timeouts. | |
27 | */ | |
28 | ||
27c766aa JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
7768a13c | 31 | #include <linux/module.h> |
7768a13c KS |
32 | #include <linux/types.h> |
33 | #include <linux/kernel.h> | |
7768a13c | 34 | #include <linux/mm.h> |
7768a13c KS |
35 | #include <linux/watchdog.h> |
36 | #include <linux/reboot.h> | |
7768a13c KS |
37 | #include <linux/err.h> |
38 | #include <linux/platform_device.h> | |
39 | #include <linux/moduleparam.h> | |
089ab079 | 40 | #include <linux/io.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
7ec5ad0f | 42 | #include <linux/pm_runtime.h> |
129f5577 | 43 | #include <linux/platform_data/omap-wd-timer.h> |
7768a13c KS |
44 | |
45 | #include "omap_wdt.h" | |
46 | ||
2dd7b244 PR |
47 | static bool nowayout = WATCHDOG_NOWAYOUT; |
48 | module_param(nowayout, bool, 0); | |
49 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " | |
50 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
51 | ||
7768a13c KS |
52 | static unsigned timer_margin; |
53 | module_param(timer_margin, uint, 0); | |
54 | MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); | |
55 | ||
d2f78268 UKK |
56 | #define to_omap_wdt_dev(_wdog) container_of(_wdog, struct omap_wdt_dev, wdog) |
57 | ||
2817142f | 58 | struct omap_wdt_dev { |
d2f78268 | 59 | struct watchdog_device wdog; |
2817142f FB |
60 | void __iomem *base; /* physical */ |
61 | struct device *dev; | |
67c0f554 | 62 | bool omap_wdt_users; |
67c0f554 AK |
63 | int wdt_trgr_pattern; |
64 | struct mutex lock; /* to avoid races with PM */ | |
2817142f FB |
65 | }; |
66 | ||
67c0f554 | 67 | static void omap_wdt_reload(struct omap_wdt_dev *wdev) |
7768a13c | 68 | { |
2817142f | 69 | void __iomem *base = wdev->base; |
b3112180 | 70 | |
7768a13c | 71 | /* wait for posted write to complete */ |
4a7e94a0 | 72 | while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c | 73 | cpu_relax(); |
b3112180 | 74 | |
67c0f554 | 75 | wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern; |
4a7e94a0 | 76 | writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); |
b3112180 | 77 | |
7768a13c | 78 | /* wait for posted write to complete */ |
4a7e94a0 | 79 | while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c KS |
80 | cpu_relax(); |
81 | /* reloaded WCRR from WLDR */ | |
82 | } | |
83 | ||
2817142f | 84 | static void omap_wdt_enable(struct omap_wdt_dev *wdev) |
7768a13c | 85 | { |
b3112180 FB |
86 | void __iomem *base = wdev->base; |
87 | ||
7768a13c | 88 | /* Sequence to enable the watchdog */ |
4a7e94a0 VK |
89 | writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR); |
90 | while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c | 91 | cpu_relax(); |
b3112180 | 92 | |
4a7e94a0 VK |
93 | writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR); |
94 | while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c KS |
95 | cpu_relax(); |
96 | } | |
97 | ||
2817142f | 98 | static void omap_wdt_disable(struct omap_wdt_dev *wdev) |
7768a13c | 99 | { |
b3112180 FB |
100 | void __iomem *base = wdev->base; |
101 | ||
7768a13c | 102 | /* sequence required to disable watchdog */ |
4a7e94a0 VK |
103 | writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
104 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c | 105 | cpu_relax(); |
b3112180 | 106 | |
4a7e94a0 VK |
107 | writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
108 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c KS |
109 | cpu_relax(); |
110 | } | |
111 | ||
67c0f554 AK |
112 | static void omap_wdt_set_timer(struct omap_wdt_dev *wdev, |
113 | unsigned int timeout) | |
7768a13c | 114 | { |
67c0f554 | 115 | u32 pre_margin = GET_WLDR_VAL(timeout); |
b3112180 | 116 | void __iomem *base = wdev->base; |
7768a13c KS |
117 | |
118 | /* just count up at 32 KHz */ | |
4a7e94a0 | 119 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) |
7768a13c | 120 | cpu_relax(); |
b3112180 | 121 | |
4a7e94a0 VK |
122 | writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR); |
123 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) | |
7768a13c KS |
124 | cpu_relax(); |
125 | } | |
126 | ||
67c0f554 | 127 | static int omap_wdt_start(struct watchdog_device *wdog) |
7768a13c | 128 | { |
d2f78268 | 129 | struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog); |
b3112180 FB |
130 | void __iomem *base = wdev->base; |
131 | ||
67c0f554 AK |
132 | mutex_lock(&wdev->lock); |
133 | ||
134 | wdev->omap_wdt_users = true; | |
7768a13c | 135 | |
7ec5ad0f | 136 | pm_runtime_get_sync(wdev->dev); |
7768a13c KS |
137 | |
138 | /* initialize prescaler */ | |
4a7e94a0 | 139 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) |
7768a13c | 140 | cpu_relax(); |
b3112180 | 141 | |
4a7e94a0 VK |
142 | writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); |
143 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) | |
7768a13c KS |
144 | cpu_relax(); |
145 | ||
67c0f554 AK |
146 | omap_wdt_set_timer(wdev, wdog->timeout); |
147 | omap_wdt_reload(wdev); /* trigger loading of new timeout value */ | |
2817142f | 148 | omap_wdt_enable(wdev); |
b3112180 | 149 | |
67c0f554 AK |
150 | mutex_unlock(&wdev->lock); |
151 | ||
152 | return 0; | |
7768a13c KS |
153 | } |
154 | ||
67c0f554 | 155 | static int omap_wdt_stop(struct watchdog_device *wdog) |
7768a13c | 156 | { |
d2f78268 | 157 | struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog); |
b3112180 | 158 | |
67c0f554 | 159 | mutex_lock(&wdev->lock); |
2817142f | 160 | omap_wdt_disable(wdev); |
7ec5ad0f | 161 | pm_runtime_put_sync(wdev->dev); |
67c0f554 AK |
162 | wdev->omap_wdt_users = false; |
163 | mutex_unlock(&wdev->lock); | |
7768a13c KS |
164 | return 0; |
165 | } | |
166 | ||
67c0f554 | 167 | static int omap_wdt_ping(struct watchdog_device *wdog) |
7768a13c | 168 | { |
d2f78268 | 169 | struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog); |
b3112180 | 170 | |
67c0f554 AK |
171 | mutex_lock(&wdev->lock); |
172 | omap_wdt_reload(wdev); | |
173 | mutex_unlock(&wdev->lock); | |
174 | ||
175 | return 0; | |
7768a13c KS |
176 | } |
177 | ||
67c0f554 AK |
178 | static int omap_wdt_set_timeout(struct watchdog_device *wdog, |
179 | unsigned int timeout) | |
7768a13c | 180 | { |
d2f78268 | 181 | struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog); |
7768a13c | 182 | |
67c0f554 AK |
183 | mutex_lock(&wdev->lock); |
184 | omap_wdt_disable(wdev); | |
185 | omap_wdt_set_timer(wdev, timeout); | |
186 | omap_wdt_enable(wdev); | |
187 | omap_wdt_reload(wdev); | |
188 | wdog->timeout = timeout; | |
189 | mutex_unlock(&wdev->lock); | |
190 | ||
191 | return 0; | |
7768a13c KS |
192 | } |
193 | ||
67c0f554 | 194 | static const struct watchdog_info omap_wdt_info = { |
fb1cbeae | 195 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, |
67c0f554 AK |
196 | .identity = "OMAP Watchdog", |
197 | }; | |
198 | ||
199 | static const struct watchdog_ops omap_wdt_ops = { | |
200 | .owner = THIS_MODULE, | |
201 | .start = omap_wdt_start, | |
202 | .stop = omap_wdt_stop, | |
203 | .ping = omap_wdt_ping, | |
204 | .set_timeout = omap_wdt_set_timeout, | |
7768a13c KS |
205 | }; |
206 | ||
2d991a16 | 207 | static int omap_wdt_probe(struct platform_device *pdev) |
7768a13c | 208 | { |
bc8fdfbe | 209 | struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev); |
6e272061 | 210 | struct resource *res; |
2817142f | 211 | struct omap_wdt_dev *wdev; |
b3112180 | 212 | int ret; |
7768a13c | 213 | |
4f4753d9 AK |
214 | wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL); |
215 | if (!wdev) | |
216 | return -ENOMEM; | |
b3112180 | 217 | |
67c0f554 | 218 | wdev->omap_wdt_users = false; |
67c0f554 AK |
219 | wdev->dev = &pdev->dev; |
220 | wdev->wdt_trgr_pattern = 0x1234; | |
221 | mutex_init(&wdev->lock); | |
2817142f | 222 | |
6e272061 JH |
223 | /* reserve static register mappings */ |
224 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
225 | wdev->base = devm_ioremap_resource(&pdev->dev, res); | |
226 | if (IS_ERR(wdev->base)) | |
227 | return PTR_ERR(wdev->base); | |
9f69e3b0 | 228 | |
d2f78268 UKK |
229 | wdev->wdog.info = &omap_wdt_info; |
230 | wdev->wdog.ops = &omap_wdt_ops; | |
231 | wdev->wdog.min_timeout = TIMER_MARGIN_MIN; | |
232 | wdev->wdog.max_timeout = TIMER_MARGIN_MAX; | |
67c0f554 | 233 | |
d2f78268 UKK |
234 | if (watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev) < 0) |
235 | wdev->wdog.timeout = TIMER_MARGIN_DEFAULT; | |
67c0f554 | 236 | |
d2f78268 | 237 | watchdog_set_nowayout(&wdev->wdog, nowayout); |
67c0f554 | 238 | |
d2f78268 | 239 | platform_set_drvdata(pdev, wdev); |
7768a13c | 240 | |
7ec5ad0f VC |
241 | pm_runtime_enable(wdev->dev); |
242 | pm_runtime_get_sync(wdev->dev); | |
789cd470 | 243 | |
0b3330f3 UKK |
244 | if (pdata && pdata->read_reset_sources) { |
245 | u32 rs = pdata->read_reset_sources(); | |
246 | if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT)) | |
247 | wdev->wdog.bootstatus = WDIOF_CARDRESET; | |
248 | } | |
7768a13c | 249 | |
67c0f554 | 250 | omap_wdt_disable(wdev); |
2817142f | 251 | |
d2f78268 | 252 | ret = watchdog_register_device(&wdev->wdog); |
1ba85387 AK |
253 | if (ret) { |
254 | pm_runtime_disable(wdev->dev); | |
255 | return ret; | |
256 | } | |
7768a13c | 257 | |
2817142f | 258 | pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n", |
4a7e94a0 | 259 | readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, |
d2f78268 | 260 | wdev->wdog.timeout); |
7768a13c | 261 | |
7ec5ad0f | 262 | pm_runtime_put_sync(wdev->dev); |
789cd470 | 263 | |
7768a13c | 264 | return 0; |
7768a13c KS |
265 | } |
266 | ||
267 | static void omap_wdt_shutdown(struct platform_device *pdev) | |
268 | { | |
d2f78268 | 269 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
2817142f | 270 | |
67c0f554 | 271 | mutex_lock(&wdev->lock); |
0503add9 | 272 | if (wdev->omap_wdt_users) { |
2817142f | 273 | omap_wdt_disable(wdev); |
0503add9 PW |
274 | pm_runtime_put_sync(wdev->dev); |
275 | } | |
67c0f554 | 276 | mutex_unlock(&wdev->lock); |
7768a13c KS |
277 | } |
278 | ||
4b12b896 | 279 | static int omap_wdt_remove(struct platform_device *pdev) |
7768a13c | 280 | { |
d2f78268 | 281 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
2817142f | 282 | |
12c583d8 | 283 | pm_runtime_disable(wdev->dev); |
d2f78268 | 284 | watchdog_unregister_device(&wdev->wdog); |
b3112180 | 285 | |
7768a13c KS |
286 | return 0; |
287 | } | |
288 | ||
289 | #ifdef CONFIG_PM | |
290 | ||
291 | /* REVISIT ... not clear this is the best way to handle system suspend; and | |
292 | * it's very inappropriate for selective device suspend (e.g. suspending this | |
293 | * through sysfs rather than by stopping the watchdog daemon). Also, this | |
294 | * may not play well enough with NOWAYOUT... | |
295 | */ | |
296 | ||
297 | static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state) | |
298 | { | |
d2f78268 | 299 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
b3112180 | 300 | |
67c0f554 | 301 | mutex_lock(&wdev->lock); |
0503add9 | 302 | if (wdev->omap_wdt_users) { |
2817142f | 303 | omap_wdt_disable(wdev); |
0503add9 PW |
304 | pm_runtime_put_sync(wdev->dev); |
305 | } | |
67c0f554 | 306 | mutex_unlock(&wdev->lock); |
b3112180 | 307 | |
7768a13c KS |
308 | return 0; |
309 | } | |
310 | ||
311 | static int omap_wdt_resume(struct platform_device *pdev) | |
312 | { | |
d2f78268 | 313 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
b3112180 | 314 | |
67c0f554 | 315 | mutex_lock(&wdev->lock); |
2817142f | 316 | if (wdev->omap_wdt_users) { |
0503add9 | 317 | pm_runtime_get_sync(wdev->dev); |
2817142f | 318 | omap_wdt_enable(wdev); |
67c0f554 | 319 | omap_wdt_reload(wdev); |
7768a13c | 320 | } |
67c0f554 | 321 | mutex_unlock(&wdev->lock); |
b3112180 | 322 | |
7768a13c KS |
323 | return 0; |
324 | } | |
325 | ||
326 | #else | |
327 | #define omap_wdt_suspend NULL | |
328 | #define omap_wdt_resume NULL | |
329 | #endif | |
330 | ||
e6ca04ea XJ |
331 | static const struct of_device_id omap_wdt_of_match[] = { |
332 | { .compatible = "ti,omap3-wdt", }, | |
333 | {}, | |
334 | }; | |
335 | MODULE_DEVICE_TABLE(of, omap_wdt_of_match); | |
336 | ||
7768a13c KS |
337 | static struct platform_driver omap_wdt_driver = { |
338 | .probe = omap_wdt_probe, | |
82268714 | 339 | .remove = omap_wdt_remove, |
7768a13c KS |
340 | .shutdown = omap_wdt_shutdown, |
341 | .suspend = omap_wdt_suspend, | |
342 | .resume = omap_wdt_resume, | |
343 | .driver = { | |
7768a13c | 344 | .name = "omap_wdt", |
e6ca04ea | 345 | .of_match_table = omap_wdt_of_match, |
7768a13c KS |
346 | }, |
347 | }; | |
348 | ||
b8ec6118 | 349 | module_platform_driver(omap_wdt_driver); |
7768a13c KS |
350 | |
351 | MODULE_AUTHOR("George G. Davis"); | |
352 | MODULE_LICENSE("GPL"); | |
f37d193c | 353 | MODULE_ALIAS("platform:omap_wdt"); |