[linux-2.6-block.git] / drivers / watchdog / omap_wdt.c

/*
 * omap_wdt.c
 *
 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
 *
 * Author: MontaVista Software, Inc.
 *	 <gdavis@mvista.com> or <source@mvista.com>
 *
 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * History:
 *
 * 20030527: George G. Davis <gdavis@mvista.com>
 *	Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
 *	(c) Copyright 2000 Oleg Drokin <green@crimea.edu>
 *	Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
 *
 * Copyright (c) 2004 Texas Instruments.
 *	1. Modified to support OMAP1610 32-KHz watchdog timer
 *	2. Ported to 2.6 kernel
 *
 * Copyright (c) 2005 David Brownell
 *	Use the driver model and standard identifiers; handle bigger timeouts.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/moduleparam.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/omap-wd-timer.h>

#include "omap_wdt.h"

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static unsigned timer_margin;
module_param(timer_margin, uint, 0);
MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");

#define to_omap_wdt_dev(_wdog)	container_of(_wdog, struct omap_wdt_dev, wdog)

static bool early_enable;
module_param(early_enable, bool, 0);
MODULE_PARM_DESC(early_enable,
	"Watchdog is started on module insertion (default=0)");

struct omap_wdt_dev {
	struct watchdog_device wdog;
	void __iomem    *base;          /* physical */
	struct device   *dev;
	bool		omap_wdt_users;
	int		wdt_trgr_pattern;
	struct mutex	lock;		/* to avoid races with PM */
};

static void omap_wdt_reload(struct omap_wdt_dev *wdev)
{
	void __iomem    *base = wdev->base;

	/* wait for posted write to complete */
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();

	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));

	/* wait for posted write to complete */
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();
	/* reloaded WCRR from WLDR */
}

static void omap_wdt_enable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* Sequence to enable the watchdog */
	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();

	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();
}

static void omap_wdt_disable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* sequence required to disable watchdog */
	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();

	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();
}

static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
				   unsigned int timeout)
{
	u32 pre_margin = GET_WLDR_VAL(timeout);
	void __iomem *base = wdev->base;

	/* just count up at 32 KHz */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();

	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();
}

static int omap_wdt_start(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
	void __iomem *base = wdev->base;

	mutex_lock(&wdev->lock);

	wdev->omap_wdt_users = true;

	pm_runtime_get_sync(wdev->dev);

	/*
	 * Make sure the watchdog is disabled. This is unfortunately required
	 * because writing to various registers with the watchdog running has no
	 * effect.
	 */
	omap_wdt_disable(wdev);

	/* initialize prescaler */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	omap_wdt_set_timer(wdev, wdog->timeout);
	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
	omap_wdt_enable(wdev);

	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_stop(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_disable(wdev);
	pm_runtime_put_sync(wdev->dev);
	wdev->omap_wdt_users = false;
	mutex_unlock(&wdev->lock);
	return 0;
}

static int omap_wdt_ping(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_reload(wdev);
	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int timeout)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_disable(wdev);
	omap_wdt_set_timer(wdev, timeout);
	omap_wdt_enable(wdev);
	omap_wdt_reload(wdev);
	wdog->timeout = timeout;
	mutex_unlock(&wdev->lock);

	return 0;
}

static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
	void __iomem *base = wdev->base;
	u32 value;

	value = readl_relaxed(base + OMAP_WATCHDOG_CRR);
	return GET_WCCR_SECS(value);
}

static const struct watchdog_info omap_wdt_info = {
	.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
	.identity = "OMAP Watchdog",
};

static const struct watchdog_ops omap_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= omap_wdt_start,
	.stop		= omap_wdt_stop,
	.ping		= omap_wdt_ping,
	.set_timeout	= omap_wdt_set_timeout,
	.get_timeleft	= omap_wdt_get_timeleft,
};

static int omap_wdt_probe(struct platform_device *pdev)
{
	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct resource *res;
	struct omap_wdt_dev *wdev;
	int ret;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	wdev->omap_wdt_users	= false;
	wdev->dev		= &pdev->dev;
	wdev->wdt_trgr_pattern	= 0x1234;
	mutex_init(&wdev->lock);

	/* reserve static register mappings */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	wdev->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(wdev->base))
		return PTR_ERR(wdev->base);

	wdev->wdog.info = &omap_wdt_info;
	wdev->wdog.ops = &omap_wdt_ops;
	wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
	wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
	wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;
	wdev->wdog.parent = &pdev->dev;

	watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev);

	watchdog_set_nowayout(&wdev->wdog, nowayout);

	platform_set_drvdata(pdev, wdev);

	pm_runtime_enable(wdev->dev);
	pm_runtime_get_sync(wdev->dev);

	if (pdata && pdata->read_reset_sources) {
		u32 rs = pdata->read_reset_sources();
		if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
			wdev->wdog.bootstatus = WDIOF_CARDRESET;
	}

	if (!early_enable)
		omap_wdt_disable(wdev);

	ret = watchdog_register_device(&wdev->wdog);
	if (ret) {
		pm_runtime_disable(wdev->dev);
		return ret;
	}

	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
		readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
		wdev->wdog.timeout);

	if (early_enable)
		omap_wdt_start(&wdev->wdog);

	pm_runtime_put(wdev->dev);

	return 0;
}

static void omap_wdt_shutdown(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		omap_wdt_disable(wdev);
		pm_runtime_put_sync(wdev->dev);
	}
	mutex_unlock(&wdev->lock);
}

static int omap_wdt_remove(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	pm_runtime_disable(wdev->dev);
	watchdog_unregister_device(&wdev->wdog);

	return 0;
}

#ifdef	CONFIG_PM

/* REVISIT ... not clear this is the best way to handle system suspend; and
 * it's very inappropriate for selective device suspend (e.g. suspending this
 * through sysfs rather than by stopping the watchdog daemon).  Also, this
 * may not play well enough with NOWAYOUT...
 */

static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		omap_wdt_disable(wdev);
		pm_runtime_put_sync(wdev->dev);
	}
	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_resume(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		pm_runtime_get_sync(wdev->dev);
		omap_wdt_enable(wdev);
		omap_wdt_reload(wdev);
	}
	mutex_unlock(&wdev->lock);

	return 0;
}

#else
#define	omap_wdt_suspend	NULL
#define	omap_wdt_resume		NULL
#endif

static const struct of_device_id omap_wdt_of_match[] = {
	{ .compatible = "ti,omap3-wdt", },
	{},
};
MODULE_DEVICE_TABLE(of, omap_wdt_of_match);

static struct platform_driver omap_wdt_driver = {
	.probe		= omap_wdt_probe,
	.remove		= omap_wdt_remove,
	.shutdown	= omap_wdt_shutdown,
	.suspend	= omap_wdt_suspend,
	.resume		= omap_wdt_resume,
	.driver		= {
		.name	= "omap_wdt",
		.of_match_table = omap_wdt_of_match,
	},
};

module_platform_driver(omap_wdt_driver);

MODULE_AUTHOR("George G. Davis");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:omap_wdt");
Commit	Line	Data
7768a13c	1	/*
2817142f	2	* omap_wdt.c
7768a13c	3	*
2817142f	4	* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
7768a13c KS	5	*
	6	* Author: MontaVista Software, Inc.
	7	* <gdavis@mvista.com> or <source@mvista.com>
	8	*
	9	* 2003 (c) MontaVista Software, Inc. This file is licensed under the
	10	* terms of the GNU General Public License version 2. This program is
	11	* licensed "as is" without any warranty of any kind, whether express
	12	* or implied.
	13	*
	14	* History:
	15	*
	16	* 20030527: George G. Davis <gdavis@mvista.com>
	17	* Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
	18	* (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
29fa0586	19	* Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
7768a13c KS	20	*
	21	* Copyright (c) 2004 Texas Instruments.
	22	* 1. Modified to support OMAP1610 32-KHz watchdog timer
	23	* 2. Ported to 2.6 kernel
	24	*
	25	* Copyright (c) 2005 David Brownell
	26	* Use the driver model and standard identifiers; handle bigger timeouts.
	27	*/
	28
27c766aa JP	29	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	30
7768a13c	31	#include <linux/module.h>
ac316725	32	#include <linux/mod_devicetable.h>
7768a13c KS	33	#include <linux/types.h>
7768a13c KS	34	#include <linux/kernel.h>
7768a13c	35	#include <linux/mm.h>
7768a13c KS	36	#include <linux/watchdog.h>
7768a13c KS	37	#include <linux/reboot.h>
7768a13c KS	38	#include <linux/err.h>
	39	#include <linux/platform_device.h>
	40	#include <linux/moduleparam.h>
089ab079	41	#include <linux/io.h>
5a0e3ad6	42	#include <linux/slab.h>
7ec5ad0f	43	#include <linux/pm_runtime.h>
129f5577	44	#include <linux/platform_data/omap-wd-timer.h>
7768a13c KS	45
	46	#include "omap_wdt.h"
	47
2dd7b244 PR	48	static bool nowayout = WATCHDOG_NOWAYOUT;
	49	module_param(nowayout, bool, 0);
	50	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	51	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	52
7768a13c KS	53	static unsigned timer_margin;
	54	module_param(timer_margin, uint, 0);
	55	MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
	56
d2f78268 UKK	57	#define to_omap_wdt_dev(_wdog) container_of(_wdog, struct omap_wdt_dev, wdog)
d2f78268 UKK	58
b2102eb3 LP	59	static bool early_enable;
	60	module_param(early_enable, bool, 0);
	61	MODULE_PARM_DESC(early_enable,
	62	"Watchdog is started on module insertion (default=0)");
	63
2817142f	64	struct omap_wdt_dev {
d2f78268	65	struct watchdog_device wdog;
2817142f FB	66	void __iomem base; / physical */
2817142f FB	67	struct device *dev;
67c0f554	68	bool omap_wdt_users;
67c0f554 AK	69	int wdt_trgr_pattern;
67c0f554 AK	70	struct mutex lock; /* to avoid races with PM */
2817142f FB	71	};
2817142f FB	72
67c0f554	73	static void omap_wdt_reload(struct omap_wdt_dev *wdev)
7768a13c	74	{
2817142f	75	void __iomem *base = wdev->base;
b3112180	76
7768a13c	77	/* wait for posted write to complete */
4a7e94a0	78	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c	79	cpu_relax();
b3112180	80
67c0f554	81	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
4a7e94a0	82	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
b3112180	83
7768a13c	84	/* wait for posted write to complete */
4a7e94a0	85	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c KS	86	cpu_relax();
	87	/* reloaded WCRR from WLDR */
	88	}
	89
2817142f	90	static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c	91	{
b3112180 FB	92	void __iomem *base = wdev->base;
b3112180 FB	93
7768a13c	94	/* Sequence to enable the watchdog */
4a7e94a0 VK	95	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
4a7e94a0 VK	96	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c	97	cpu_relax();
b3112180	98
4a7e94a0 VK	99	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
4a7e94a0 VK	100	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c KS	101	cpu_relax();
	102	}
	103
2817142f	104	static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c	105	{
b3112180 FB	106	void __iomem *base = wdev->base;
b3112180 FB	107
7768a13c	108	/* sequence required to disable watchdog */
4a7e94a0 VK	109	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
4a7e94a0 VK	110	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c	111	cpu_relax();
b3112180	112
4a7e94a0 VK	113	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
4a7e94a0 VK	114	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c KS	115	cpu_relax();
	116	}
	117
67c0f554 AK	118	static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
67c0f554 AK	119	unsigned int timeout)
7768a13c	120	{
67c0f554	121	u32 pre_margin = GET_WLDR_VAL(timeout);
b3112180	122	void __iomem *base = wdev->base;
7768a13c KS	123
7768a13c KS	124	/* just count up at 32 KHz */
4a7e94a0	125	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c	126	cpu_relax();
b3112180	127
4a7e94a0 VK	128	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
4a7e94a0 VK	129	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c KS	130	cpu_relax();
	131	}
	132
67c0f554	133	static int omap_wdt_start(struct watchdog_device *wdog)
7768a13c	134	{
d2f78268	135	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180 FB	136	void __iomem *base = wdev->base;
b3112180 FB	137
67c0f554 AK	138	mutex_lock(&wdev->lock);
	139
	140	wdev->omap_wdt_users = true;
7768a13c	141
7ec5ad0f	142	pm_runtime_get_sync(wdev->dev);
7768a13c	143
530c11d4 UKK	144	/*
	145	* Make sure the watchdog is disabled. This is unfortunately required
	146	* because writing to various registers with the watchdog running has no
	147	* effect.
	148	*/
	149	omap_wdt_disable(wdev);
	150
7768a13c	151	/* initialize prescaler */
4a7e94a0	152	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c	153	cpu_relax();
b3112180	154
4a7e94a0 VK	155	writel_relaxed((1 << 5) \| (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
4a7e94a0 VK	156	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c KS	157	cpu_relax();
7768a13c KS	158
67c0f554 AK	159	omap_wdt_set_timer(wdev, wdog->timeout);
67c0f554 AK	160	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
2817142f	161	omap_wdt_enable(wdev);
b3112180	162
67c0f554 AK	163	mutex_unlock(&wdev->lock);
	164
	165	return 0;
7768a13c KS	166	}
7768a13c KS	167
67c0f554	168	static int omap_wdt_stop(struct watchdog_device *wdog)
7768a13c	169	{
d2f78268	170	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180	171
67c0f554	172	mutex_lock(&wdev->lock);
2817142f	173	omap_wdt_disable(wdev);
7ec5ad0f	174	pm_runtime_put_sync(wdev->dev);
67c0f554 AK	175	wdev->omap_wdt_users = false;
67c0f554 AK	176	mutex_unlock(&wdev->lock);
7768a13c KS	177	return 0;
	178	}
	179
67c0f554	180	static int omap_wdt_ping(struct watchdog_device *wdog)
7768a13c	181	{
d2f78268	182	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180	183
67c0f554 AK	184	mutex_lock(&wdev->lock);
	185	omap_wdt_reload(wdev);
	186	mutex_unlock(&wdev->lock);
	187
	188	return 0;
7768a13c KS	189	}
7768a13c KS	190
67c0f554 AK	191	static int omap_wdt_set_timeout(struct watchdog_device *wdog,
67c0f554 AK	192	unsigned int timeout)
7768a13c	193	{
d2f78268	194	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
7768a13c	195
67c0f554 AK	196	mutex_lock(&wdev->lock);
	197	omap_wdt_disable(wdev);
	198	omap_wdt_set_timer(wdev, timeout);
	199	omap_wdt_enable(wdev);
	200	omap_wdt_reload(wdev);
	201	wdog->timeout = timeout;
	202	mutex_unlock(&wdev->lock);
	203
	204	return 0;
7768a13c KS	205	}
7768a13c KS	206
452fafed LP	207	static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)
452fafed LP	208	{
de55acd1	209	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
452fafed LP	210	void __iomem *base = wdev->base;
	211	u32 value;
	212
	213	value = readl_relaxed(base + OMAP_WATCHDOG_CRR);
	214	return GET_WCCR_SECS(value);
	215	}
	216
67c0f554	217	static const struct watchdog_info omap_wdt_info = {
fb1cbeae	218	.options = WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING,
67c0f554 AK	219	.identity = "OMAP Watchdog",
	220	};
	221
	222	static const struct watchdog_ops omap_wdt_ops = {
	223	.owner = THIS_MODULE,
	224	.start = omap_wdt_start,
	225	.stop = omap_wdt_stop,
	226	.ping = omap_wdt_ping,
	227	.set_timeout = omap_wdt_set_timeout,
452fafed	228	.get_timeleft = omap_wdt_get_timeleft,
7768a13c KS	229	};
7768a13c KS	230
2d991a16	231	static int omap_wdt_probe(struct platform_device *pdev)
7768a13c	232	{
bc8fdfbe	233	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
6e272061	234	struct resource *res;
2817142f	235	struct omap_wdt_dev *wdev;
b3112180	236	int ret;
7768a13c	237
4f4753d9 AK	238	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	239	if (!wdev)
	240	return -ENOMEM;
b3112180	241
67c0f554	242	wdev->omap_wdt_users = false;
67c0f554 AK	243	wdev->dev = &pdev->dev;
	244	wdev->wdt_trgr_pattern = 0x1234;
	245	mutex_init(&wdev->lock);
2817142f	246
6e272061 JH	247	/* reserve static register mappings */
	248	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	249	wdev->base = devm_ioremap_resource(&pdev->dev, res);
	250	if (IS_ERR(wdev->base))
	251	return PTR_ERR(wdev->base);
9f69e3b0	252
d2f78268 UKK	253	wdev->wdog.info = &omap_wdt_info;
	254	wdev->wdog.ops = &omap_wdt_ops;
	255	wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
	256	wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
1253730e	257	wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;
6551881c	258	wdev->wdog.parent = &pdev->dev;
67c0f554	259
1253730e	260	watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev);
67c0f554	261
d2f78268	262	watchdog_set_nowayout(&wdev->wdog, nowayout);
67c0f554	263
d2f78268	264	platform_set_drvdata(pdev, wdev);
7768a13c	265
7ec5ad0f VC	266	pm_runtime_enable(wdev->dev);
7ec5ad0f VC	267	pm_runtime_get_sync(wdev->dev);
789cd470	268
0b3330f3 UKK	269	if (pdata && pdata->read_reset_sources) {
	270	u32 rs = pdata->read_reset_sources();
	271	if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
	272	wdev->wdog.bootstatus = WDIOF_CARDRESET;
	273	}
7768a13c	274
8605fec1 UKK	275	if (!early_enable)
8605fec1 UKK	276	omap_wdt_disable(wdev);
2817142f	277
d2f78268	278	ret = watchdog_register_device(&wdev->wdog);
1ba85387 AK	279	if (ret) {
	280	pm_runtime_disable(wdev->dev);
	281	return ret;
	282	}
7768a13c	283
2817142f	284	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
4a7e94a0	285	readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
d2f78268	286	wdev->wdog.timeout);
7768a13c	287
b2102eb3 LP	288	if (early_enable)
	289	omap_wdt_start(&wdev->wdog);
	290
a6392490 UKK	291	pm_runtime_put(wdev->dev);
a6392490 UKK	292
7768a13c	293	return 0;
7768a13c KS	294	}
	295
	296	static void omap_wdt_shutdown(struct platform_device *pdev)
	297	{
d2f78268	298	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f	299
67c0f554	300	mutex_lock(&wdev->lock);
0503add9	301	if (wdev->omap_wdt_users) {
2817142f	302	omap_wdt_disable(wdev);
0503add9 PW	303	pm_runtime_put_sync(wdev->dev);
0503add9 PW	304	}
67c0f554	305	mutex_unlock(&wdev->lock);
7768a13c KS	306	}
7768a13c KS	307
4b12b896	308	static int omap_wdt_remove(struct platform_device *pdev)
7768a13c	309	{
d2f78268	310	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f	311
12c583d8	312	pm_runtime_disable(wdev->dev);
d2f78268	313	watchdog_unregister_device(&wdev->wdog);
b3112180	314
7768a13c KS	315	return 0;
	316	}
	317
	318	#ifdef CONFIG_PM
	319
	320	/* REVISIT ... not clear this is the best way to handle system suspend; and
	321	* it's very inappropriate for selective device suspend (e.g. suspending this
	322	* through sysfs rather than by stopping the watchdog daemon). Also, this
	323	* may not play well enough with NOWAYOUT...
	324	*/
	325
	326	static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
	327	{
d2f78268	328	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180	329
67c0f554	330	mutex_lock(&wdev->lock);
0503add9	331	if (wdev->omap_wdt_users) {
2817142f	332	omap_wdt_disable(wdev);
0503add9 PW	333	pm_runtime_put_sync(wdev->dev);
0503add9 PW	334	}
67c0f554	335	mutex_unlock(&wdev->lock);
b3112180	336
7768a13c KS	337	return 0;
	338	}
	339
	340	static int omap_wdt_resume(struct platform_device *pdev)
	341	{
d2f78268	342	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180	343
67c0f554	344	mutex_lock(&wdev->lock);
2817142f	345	if (wdev->omap_wdt_users) {
0503add9	346	pm_runtime_get_sync(wdev->dev);
2817142f	347	omap_wdt_enable(wdev);
67c0f554	348	omap_wdt_reload(wdev);
7768a13c	349	}
67c0f554	350	mutex_unlock(&wdev->lock);
b3112180	351
7768a13c KS	352	return 0;
	353	}
	354
	355	#else
	356	#define omap_wdt_suspend NULL
	357	#define omap_wdt_resume NULL
	358	#endif
	359
e6ca04ea XJ	360	static const struct of_device_id omap_wdt_of_match[] = {
	361	{ .compatible = "ti,omap3-wdt", },
	362	{},
	363	};
	364	MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
	365
7768a13c KS	366	static struct platform_driver omap_wdt_driver = {
7768a13c KS	367	.probe = omap_wdt_probe,
82268714	368	.remove = omap_wdt_remove,
7768a13c KS	369	.shutdown = omap_wdt_shutdown,
	370	.suspend = omap_wdt_suspend,
	371	.resume = omap_wdt_resume,
	372	.driver = {
7768a13c	373	.name = "omap_wdt",
e6ca04ea	374	.of_match_table = omap_wdt_of_match,
7768a13c KS	375	},
	376	};
	377
b8ec6118	378	module_platform_driver(omap_wdt_driver);
7768a13c KS	379
	380	MODULE_AUTHOR("George G. Davis");
	381	MODULE_LICENSE("GPL");
f37d193c	382	MODULE_ALIAS("platform:omap_wdt");