Commit | Line | Data |
---|---|---|
e9659e69 | 1 | /* |
9419c07c MS |
2 | * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt |
3 | * | |
d14fd964 | 4 | * (C) Copyright 2013 - 2014 Xilinx, Inc. |
9419c07c MS |
5 | * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
e9659e69 | 12 | |
9d6b4efc | 13 | #include <linux/clk.h> |
f06cdfd1 | 14 | #include <linux/err.h> |
e9659e69 AC |
15 | #include <linux/module.h> |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
e9659e69 AC |
18 | #include <linux/ioport.h> |
19 | #include <linux/watchdog.h> | |
20 | #include <linux/io.h> | |
e9659e69 AC |
21 | #include <linux/of.h> |
22 | #include <linux/of_device.h> | |
23 | #include <linux/of_address.h> | |
24 | ||
25 | /* Register offsets for the Wdt device */ | |
26 | #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */ | |
27 | #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */ | |
28 | #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */ | |
29 | ||
30 | /* Control/Status Register Masks */ | |
31 | #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */ | |
32 | #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */ | |
33 | #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */ | |
34 | ||
35 | /* Control/Status Register 0/1 bits */ | |
36 | #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */ | |
37 | ||
38 | /* SelfTest constants */ | |
39 | #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000 | |
40 | #define XWT_TIMER_FAILED 0xFFFFFFFF | |
41 | ||
42 | #define WATCHDOG_NAME "Xilinx Watchdog" | |
e9659e69 AC |
43 | |
44 | struct xwdt_device { | |
e9659e69 | 45 | void __iomem *base; |
e9659e69 | 46 | u32 wdt_interval; |
90663171 MS |
47 | spinlock_t spinlock; |
48 | struct watchdog_device xilinx_wdt_wdd; | |
9d6b4efc | 49 | struct clk *clk; |
e9659e69 AC |
50 | }; |
51 | ||
d14fd964 | 52 | static int xilinx_wdt_start(struct watchdog_device *wdd) |
e9659e69 | 53 | { |
5cf4e69d | 54 | u32 control_status_reg; |
90663171 | 55 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 56 | |
90663171 | 57 | spin_lock(&xdev->spinlock); |
e9659e69 AC |
58 | |
59 | /* Clean previous status and enable the watchdog timer */ | |
90663171 | 60 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 AC |
61 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
62 | ||
63 | iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), | |
90663171 | 64 | xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 65 | |
90663171 | 66 | iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET); |
e9659e69 | 67 | |
90663171 | 68 | spin_unlock(&xdev->spinlock); |
d14fd964 MS |
69 | |
70 | return 0; | |
e9659e69 AC |
71 | } |
72 | ||
d14fd964 | 73 | static int xilinx_wdt_stop(struct watchdog_device *wdd) |
e9659e69 | 74 | { |
5cf4e69d | 75 | u32 control_status_reg; |
90663171 | 76 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 77 | |
90663171 | 78 | spin_lock(&xdev->spinlock); |
e9659e69 | 79 | |
90663171 | 80 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 AC |
81 | |
82 | iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), | |
90663171 | 83 | xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 84 | |
90663171 | 85 | iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET); |
e9659e69 | 86 | |
90663171 | 87 | spin_unlock(&xdev->spinlock); |
27c766aa | 88 | pr_info("Stopped!\n"); |
d14fd964 MS |
89 | |
90 | return 0; | |
e9659e69 AC |
91 | } |
92 | ||
d14fd964 | 93 | static int xilinx_wdt_keepalive(struct watchdog_device *wdd) |
e9659e69 | 94 | { |
5cf4e69d | 95 | u32 control_status_reg; |
90663171 | 96 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 97 | |
90663171 | 98 | spin_lock(&xdev->spinlock); |
e9659e69 | 99 | |
90663171 | 100 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 101 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
90663171 | 102 | iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 103 | |
90663171 | 104 | spin_unlock(&xdev->spinlock); |
e9659e69 | 105 | |
d14fd964 MS |
106 | return 0; |
107 | } | |
e9659e69 | 108 | |
d14fd964 MS |
109 | static const struct watchdog_info xilinx_wdt_ident = { |
110 | .options = WDIOF_MAGICCLOSE | | |
111 | WDIOF_KEEPALIVEPING, | |
112 | .firmware_version = 1, | |
113 | .identity = WATCHDOG_NAME, | |
114 | }; | |
e9659e69 | 115 | |
d14fd964 MS |
116 | static const struct watchdog_ops xilinx_wdt_ops = { |
117 | .owner = THIS_MODULE, | |
118 | .start = xilinx_wdt_start, | |
119 | .stop = xilinx_wdt_stop, | |
120 | .ping = xilinx_wdt_keepalive, | |
121 | }; | |
e9659e69 | 122 | |
90663171 | 123 | static u32 xwdt_selftest(struct xwdt_device *xdev) |
e9659e69 AC |
124 | { |
125 | int i; | |
126 | u32 timer_value1; | |
127 | u32 timer_value2; | |
128 | ||
90663171 | 129 | spin_lock(&xdev->spinlock); |
e9659e69 | 130 | |
90663171 MS |
131 | timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET); |
132 | timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); | |
e9659e69 AC |
133 | |
134 | for (i = 0; | |
135 | ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) && | |
136 | (timer_value2 == timer_value1)); i++) { | |
90663171 | 137 | timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); |
e9659e69 AC |
138 | } |
139 | ||
90663171 | 140 | spin_unlock(&xdev->spinlock); |
e9659e69 AC |
141 | |
142 | if (timer_value2 != timer_value1) | |
143 | return ~XWT_TIMER_FAILED; | |
144 | else | |
145 | return XWT_TIMER_FAILED; | |
146 | } | |
147 | ||
2d991a16 | 148 | static int xwdt_probe(struct platform_device *pdev) |
e9659e69 AC |
149 | { |
150 | int rc; | |
8d6a140b | 151 | u32 pfreq = 0, enable_once = 0; |
f06cdfd1 | 152 | struct resource *res; |
90663171 | 153 | struct xwdt_device *xdev; |
90663171 MS |
154 | struct watchdog_device *xilinx_wdt_wdd; |
155 | ||
156 | xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); | |
157 | if (!xdev) | |
158 | return -ENOMEM; | |
159 | ||
160 | xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd; | |
161 | xilinx_wdt_wdd->info = &xilinx_wdt_ident; | |
162 | xilinx_wdt_wdd->ops = &xilinx_wdt_ops; | |
163 | xilinx_wdt_wdd->parent = &pdev->dev; | |
e9659e69 | 164 | |
f06cdfd1 | 165 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
90663171 MS |
166 | xdev->base = devm_ioremap_resource(&pdev->dev, res); |
167 | if (IS_ERR(xdev->base)) | |
168 | return PTR_ERR(xdev->base); | |
f06cdfd1 | 169 | |
2e79a368 | 170 | rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &pfreq); |
8d6a140b | 171 | if (rc) |
4c7fbbc4 MS |
172 | dev_warn(&pdev->dev, |
173 | "The watchdog clock frequency cannot be obtained\n"); | |
e9659e69 | 174 | |
2e79a368 MS |
175 | rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval", |
176 | &xdev->wdt_interval); | |
8d6a140b | 177 | if (rc) |
4c7fbbc4 MS |
178 | dev_warn(&pdev->dev, |
179 | "Parameter \"xlnx,wdt-interval\" not found\n"); | |
e9659e69 | 180 | |
2e79a368 MS |
181 | rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-enable-once", |
182 | &enable_once); | |
183 | if (rc) | |
4c7fbbc4 MS |
184 | dev_warn(&pdev->dev, |
185 | "Parameter \"xlnx,wdt-enable-once\" not found\n"); | |
2e79a368 MS |
186 | |
187 | watchdog_set_nowayout(xilinx_wdt_wdd, enable_once); | |
e9659e69 | 188 | |
75b3c5a8 MS |
189 | /* |
190 | * Twice of the 2^wdt_interval / freq because the first wdt overflow is | |
191 | * ignored (interrupt), reset is only generated at second wdt overflow | |
192 | */ | |
8d6a140b | 193 | if (pfreq && xdev->wdt_interval) |
90663171 | 194 | xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) / |
2e79a368 | 195 | pfreq); |
90663171 MS |
196 | |
197 | spin_lock_init(&xdev->spinlock); | |
198 | watchdog_set_drvdata(xilinx_wdt_wdd, xdev); | |
e9659e69 | 199 | |
9d6b4efc SD |
200 | xdev->clk = devm_clk_get(&pdev->dev, NULL); |
201 | if (IS_ERR(xdev->clk)) { | |
202 | if (PTR_ERR(xdev->clk) == -ENOENT) | |
203 | xdev->clk = NULL; | |
204 | else | |
205 | return PTR_ERR(xdev->clk); | |
206 | } | |
207 | ||
208 | rc = clk_prepare_enable(xdev->clk); | |
209 | if (rc) { | |
210 | dev_err(&pdev->dev, "unable to enable clock\n"); | |
211 | return rc; | |
212 | } | |
213 | ||
90663171 | 214 | rc = xwdt_selftest(xdev); |
e9659e69 | 215 | if (rc == XWT_TIMER_FAILED) { |
4c7fbbc4 | 216 | dev_err(&pdev->dev, "SelfTest routine error\n"); |
9d6b4efc | 217 | goto err_clk_disable; |
e9659e69 AC |
218 | } |
219 | ||
90663171 | 220 | rc = watchdog_register_device(xilinx_wdt_wdd); |
e9659e69 | 221 | if (rc) { |
4c7fbbc4 | 222 | dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc); |
9d6b4efc | 223 | goto err_clk_disable; |
e9659e69 AC |
224 | } |
225 | ||
d14fd964 | 226 | dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n", |
90663171 MS |
227 | xdev->base, xilinx_wdt_wdd->timeout); |
228 | ||
229 | platform_set_drvdata(pdev, xdev); | |
e9659e69 AC |
230 | |
231 | return 0; | |
9d6b4efc SD |
232 | err_clk_disable: |
233 | clk_disable_unprepare(xdev->clk); | |
234 | ||
235 | return rc; | |
e9659e69 AC |
236 | } |
237 | ||
90663171 | 238 | static int xwdt_remove(struct platform_device *pdev) |
e9659e69 | 239 | { |
90663171 MS |
240 | struct xwdt_device *xdev = platform_get_drvdata(pdev); |
241 | ||
242 | watchdog_unregister_device(&xdev->xilinx_wdt_wdd); | |
9d6b4efc | 243 | clk_disable_unprepare(xdev->clk); |
e9659e69 AC |
244 | |
245 | return 0; | |
246 | } | |
247 | ||
248 | /* Match table for of_platform binding */ | |
9ebf1855 | 249 | static const struct of_device_id xwdt_of_match[] = { |
8fce9b36 | 250 | { .compatible = "xlnx,xps-timebase-wdt-1.00.a", }, |
e9659e69 AC |
251 | { .compatible = "xlnx,xps-timebase-wdt-1.01.a", }, |
252 | {}, | |
253 | }; | |
254 | MODULE_DEVICE_TABLE(of, xwdt_of_match); | |
255 | ||
256 | static struct platform_driver xwdt_driver = { | |
257 | .probe = xwdt_probe, | |
82268714 | 258 | .remove = xwdt_remove, |
e9659e69 | 259 | .driver = { |
e9659e69 AC |
260 | .name = WATCHDOG_NAME, |
261 | .of_match_table = xwdt_of_match, | |
262 | }, | |
263 | }; | |
264 | ||
b8ec6118 | 265 | module_platform_driver(xwdt_driver); |
e9659e69 AC |
266 | |
267 | MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>"); | |
268 | MODULE_DESCRIPTION("Xilinx Watchdog driver"); | |
9419c07c | 269 | MODULE_LICENSE("GPL v2"); |