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2e62c498 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
e9659e69 | 2 | /* |
9419c07c MS |
3 | * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt |
4 | * | |
d14fd964 | 5 | * (C) Copyright 2013 - 2014 Xilinx, Inc. |
9419c07c | 6 | * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>) |
9419c07c | 7 | */ |
e9659e69 | 8 | |
73ec9440 | 9 | #include <linux/bits.h> |
9d6b4efc | 10 | #include <linux/clk.h> |
f06cdfd1 | 11 | #include <linux/err.h> |
e9659e69 | 12 | #include <linux/module.h> |
cc85f87a | 13 | #include <linux/platform_device.h> |
e9659e69 AC |
14 | #include <linux/types.h> |
15 | #include <linux/kernel.h> | |
e9659e69 AC |
16 | #include <linux/ioport.h> |
17 | #include <linux/watchdog.h> | |
18 | #include <linux/io.h> | |
e9659e69 | 19 | #include <linux/of.h> |
e9659e69 AC |
20 | |
21 | /* Register offsets for the Wdt device */ | |
22 | #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */ | |
23 | #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */ | |
24 | #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */ | |
25 | ||
26 | /* Control/Status Register Masks */ | |
73ec9440 SG |
27 | #define XWT_CSR0_WRS_MASK BIT(3) /* Reset status */ |
28 | #define XWT_CSR0_WDS_MASK BIT(2) /* Timer state */ | |
29 | #define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */ | |
e9659e69 AC |
30 | |
31 | /* Control/Status Register 0/1 bits */ | |
73ec9440 | 32 | #define XWT_CSRX_EWDT2_MASK BIT(0) /* Enable bit 2 */ |
e9659e69 AC |
33 | |
34 | /* SelfTest constants */ | |
35 | #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000 | |
36 | #define XWT_TIMER_FAILED 0xFFFFFFFF | |
37 | ||
38 | #define WATCHDOG_NAME "Xilinx Watchdog" | |
e9659e69 AC |
39 | |
40 | struct xwdt_device { | |
e9659e69 | 41 | void __iomem *base; |
e9659e69 | 42 | u32 wdt_interval; |
b2802e78 | 43 | spinlock_t spinlock; /* spinlock for register handling */ |
90663171 | 44 | struct watchdog_device xilinx_wdt_wdd; |
9d6b4efc | 45 | struct clk *clk; |
e9659e69 AC |
46 | }; |
47 | ||
d14fd964 | 48 | static int xilinx_wdt_start(struct watchdog_device *wdd) |
e9659e69 | 49 | { |
b6bc4164 | 50 | int ret; |
5cf4e69d | 51 | u32 control_status_reg; |
90663171 | 52 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 53 | |
b6bc4164 MJ |
54 | ret = clk_enable(xdev->clk); |
55 | if (ret) { | |
56 | dev_err(wdd->parent, "Failed to enable clock\n"); | |
57 | return ret; | |
58 | } | |
59 | ||
90663171 | 60 | spin_lock(&xdev->spinlock); |
e9659e69 AC |
61 | |
62 | /* Clean previous status and enable the watchdog timer */ | |
90663171 | 63 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 AC |
64 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
65 | ||
66 | iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), | |
90663171 | 67 | xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 68 | |
90663171 | 69 | iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET); |
e9659e69 | 70 | |
90663171 | 71 | spin_unlock(&xdev->spinlock); |
d14fd964 | 72 | |
a40b2c3d SG |
73 | dev_dbg(wdd->parent, "Watchdog Started!\n"); |
74 | ||
d14fd964 | 75 | return 0; |
e9659e69 AC |
76 | } |
77 | ||
d14fd964 | 78 | static int xilinx_wdt_stop(struct watchdog_device *wdd) |
e9659e69 | 79 | { |
5cf4e69d | 80 | u32 control_status_reg; |
90663171 | 81 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 82 | |
90663171 | 83 | spin_lock(&xdev->spinlock); |
e9659e69 | 84 | |
90663171 | 85 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 AC |
86 | |
87 | iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), | |
90663171 | 88 | xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 89 | |
90663171 | 90 | iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET); |
e9659e69 | 91 | |
90663171 | 92 | spin_unlock(&xdev->spinlock); |
b6bc4164 MJ |
93 | |
94 | clk_disable(xdev->clk); | |
95 | ||
a40b2c3d | 96 | dev_dbg(wdd->parent, "Watchdog Stopped!\n"); |
d14fd964 MS |
97 | |
98 | return 0; | |
e9659e69 AC |
99 | } |
100 | ||
d14fd964 | 101 | static int xilinx_wdt_keepalive(struct watchdog_device *wdd) |
e9659e69 | 102 | { |
5cf4e69d | 103 | u32 control_status_reg; |
90663171 | 104 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 105 | |
90663171 | 106 | spin_lock(&xdev->spinlock); |
e9659e69 | 107 | |
90663171 | 108 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 109 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
90663171 | 110 | iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 111 | |
90663171 | 112 | spin_unlock(&xdev->spinlock); |
e9659e69 | 113 | |
d14fd964 MS |
114 | return 0; |
115 | } | |
e9659e69 | 116 | |
d14fd964 MS |
117 | static const struct watchdog_info xilinx_wdt_ident = { |
118 | .options = WDIOF_MAGICCLOSE | | |
119 | WDIOF_KEEPALIVEPING, | |
120 | .firmware_version = 1, | |
121 | .identity = WATCHDOG_NAME, | |
122 | }; | |
e9659e69 | 123 | |
d14fd964 MS |
124 | static const struct watchdog_ops xilinx_wdt_ops = { |
125 | .owner = THIS_MODULE, | |
126 | .start = xilinx_wdt_start, | |
127 | .stop = xilinx_wdt_stop, | |
128 | .ping = xilinx_wdt_keepalive, | |
129 | }; | |
e9659e69 | 130 | |
90663171 | 131 | static u32 xwdt_selftest(struct xwdt_device *xdev) |
e9659e69 AC |
132 | { |
133 | int i; | |
134 | u32 timer_value1; | |
135 | u32 timer_value2; | |
136 | ||
90663171 | 137 | spin_lock(&xdev->spinlock); |
e9659e69 | 138 | |
90663171 MS |
139 | timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET); |
140 | timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); | |
e9659e69 AC |
141 | |
142 | for (i = 0; | |
143 | ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) && | |
144 | (timer_value2 == timer_value1)); i++) { | |
90663171 | 145 | timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); |
e9659e69 AC |
146 | } |
147 | ||
90663171 | 148 | spin_unlock(&xdev->spinlock); |
e9659e69 AC |
149 | |
150 | if (timer_value2 != timer_value1) | |
151 | return ~XWT_TIMER_FAILED; | |
152 | else | |
153 | return XWT_TIMER_FAILED; | |
154 | } | |
155 | ||
2d991a16 | 156 | static int xwdt_probe(struct platform_device *pdev) |
e9659e69 | 157 | { |
801cdffe | 158 | struct device *dev = &pdev->dev; |
e9659e69 | 159 | int rc; |
8d6a140b | 160 | u32 pfreq = 0, enable_once = 0; |
90663171 | 161 | struct xwdt_device *xdev; |
90663171 MS |
162 | struct watchdog_device *xilinx_wdt_wdd; |
163 | ||
801cdffe | 164 | xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL); |
90663171 MS |
165 | if (!xdev) |
166 | return -ENOMEM; | |
167 | ||
168 | xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd; | |
169 | xilinx_wdt_wdd->info = &xilinx_wdt_ident; | |
170 | xilinx_wdt_wdd->ops = &xilinx_wdt_ops; | |
801cdffe | 171 | xilinx_wdt_wdd->parent = dev; |
e9659e69 | 172 | |
0f0a6a28 | 173 | xdev->base = devm_platform_ioremap_resource(pdev, 0); |
90663171 MS |
174 | if (IS_ERR(xdev->base)) |
175 | return PTR_ERR(xdev->base); | |
f06cdfd1 | 176 | |
801cdffe | 177 | rc = of_property_read_u32(dev->of_node, "xlnx,wdt-interval", |
2e79a368 | 178 | &xdev->wdt_interval); |
8d6a140b | 179 | if (rc) |
801cdffe | 180 | dev_warn(dev, "Parameter \"xlnx,wdt-interval\" not found\n"); |
e9659e69 | 181 | |
801cdffe | 182 | rc = of_property_read_u32(dev->of_node, "xlnx,wdt-enable-once", |
2e79a368 MS |
183 | &enable_once); |
184 | if (rc) | |
801cdffe | 185 | dev_warn(dev, |
4c7fbbc4 | 186 | "Parameter \"xlnx,wdt-enable-once\" not found\n"); |
2e79a368 MS |
187 | |
188 | watchdog_set_nowayout(xilinx_wdt_wdd, enable_once); | |
e9659e69 | 189 | |
15f0f6d2 | 190 | xdev->clk = devm_clk_get_prepared(dev, NULL); |
b6bc4164 MJ |
191 | if (IS_ERR(xdev->clk)) { |
192 | if (PTR_ERR(xdev->clk) != -ENOENT) | |
193 | return PTR_ERR(xdev->clk); | |
194 | ||
195 | /* | |
196 | * Clock framework support is optional, continue on | |
197 | * anyways if we don't find a matching clock. | |
198 | */ | |
199 | xdev->clk = NULL; | |
200 | ||
801cdffe | 201 | rc = of_property_read_u32(dev->of_node, "clock-frequency", |
b6bc4164 MJ |
202 | &pfreq); |
203 | if (rc) | |
801cdffe | 204 | dev_warn(dev, |
b6bc4164 MJ |
205 | "The watchdog clock freq cannot be obtained\n"); |
206 | } else { | |
207 | pfreq = clk_get_rate(xdev->clk); | |
208 | } | |
209 | ||
75b3c5a8 MS |
210 | /* |
211 | * Twice of the 2^wdt_interval / freq because the first wdt overflow is | |
212 | * ignored (interrupt), reset is only generated at second wdt overflow | |
213 | */ | |
8d6a140b | 214 | if (pfreq && xdev->wdt_interval) |
90663171 | 215 | xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) / |
2e79a368 | 216 | pfreq); |
90663171 MS |
217 | |
218 | spin_lock_init(&xdev->spinlock); | |
219 | watchdog_set_drvdata(xilinx_wdt_wdd, xdev); | |
e9659e69 | 220 | |
15f0f6d2 SN |
221 | rc = clk_enable(xdev->clk); |
222 | if (rc) { | |
223 | dev_err(dev, "unable to enable clock\n"); | |
224 | return rc; | |
225 | } | |
226 | ||
90663171 | 227 | rc = xwdt_selftest(xdev); |
e9659e69 | 228 | if (rc == XWT_TIMER_FAILED) { |
801cdffe | 229 | dev_err(dev, "SelfTest routine error\n"); |
15f0f6d2 | 230 | clk_disable(xdev->clk); |
801cdffe | 231 | return rc; |
e9659e69 AC |
232 | } |
233 | ||
15f0f6d2 SN |
234 | clk_disable(xdev->clk); |
235 | ||
801cdffe | 236 | rc = devm_watchdog_register_device(dev, xilinx_wdt_wdd); |
0fa6cf71 | 237 | if (rc) |
801cdffe | 238 | return rc; |
e9659e69 | 239 | |
48027d0d SN |
240 | dev_info(dev, "Xilinx Watchdog Timer with timeout %ds\n", |
241 | xilinx_wdt_wdd->timeout); | |
90663171 MS |
242 | |
243 | platform_set_drvdata(pdev, xdev); | |
e9659e69 | 244 | |
e9659e69 AC |
245 | return 0; |
246 | } | |
247 | ||
6f671c6b MS |
248 | /** |
249 | * xwdt_suspend - Suspend the device. | |
250 | * | |
251 | * @dev: handle to the device structure. | |
252 | * Return: 0 always. | |
253 | */ | |
254 | static int __maybe_unused xwdt_suspend(struct device *dev) | |
255 | { | |
20745634 | 256 | struct xwdt_device *xdev = dev_get_drvdata(dev); |
6f671c6b MS |
257 | |
258 | if (watchdog_active(&xdev->xilinx_wdt_wdd)) | |
259 | xilinx_wdt_stop(&xdev->xilinx_wdt_wdd); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | /** | |
265 | * xwdt_resume - Resume the device. | |
266 | * | |
267 | * @dev: handle to the device structure. | |
268 | * Return: 0 on success, errno otherwise. | |
269 | */ | |
270 | static int __maybe_unused xwdt_resume(struct device *dev) | |
271 | { | |
20745634 | 272 | struct xwdt_device *xdev = dev_get_drvdata(dev); |
6f671c6b MS |
273 | int ret = 0; |
274 | ||
275 | if (watchdog_active(&xdev->xilinx_wdt_wdd)) | |
276 | ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd); | |
277 | ||
278 | return ret; | |
279 | } | |
280 | ||
281 | static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume); | |
282 | ||
e9659e69 | 283 | /* Match table for of_platform binding */ |
9ebf1855 | 284 | static const struct of_device_id xwdt_of_match[] = { |
8fce9b36 | 285 | { .compatible = "xlnx,xps-timebase-wdt-1.00.a", }, |
e9659e69 AC |
286 | { .compatible = "xlnx,xps-timebase-wdt-1.01.a", }, |
287 | {}, | |
288 | }; | |
289 | MODULE_DEVICE_TABLE(of, xwdt_of_match); | |
290 | ||
291 | static struct platform_driver xwdt_driver = { | |
292 | .probe = xwdt_probe, | |
e9659e69 | 293 | .driver = { |
e9659e69 AC |
294 | .name = WATCHDOG_NAME, |
295 | .of_match_table = xwdt_of_match, | |
6f671c6b | 296 | .pm = &xwdt_pm_ops, |
e9659e69 AC |
297 | }, |
298 | }; | |
299 | ||
b8ec6118 | 300 | module_platform_driver(xwdt_driver); |
e9659e69 AC |
301 | |
302 | MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>"); | |
303 | MODULE_DESCRIPTION("Xilinx Watchdog driver"); | |
2e62c498 | 304 | MODULE_LICENSE("GPL"); |