Commit | Line | Data |
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4c076fb4 DD |
1 | /* |
2 | * Octeon Watchdog driver | |
3 | * | |
381cec02 | 4 | * Copyright (C) 2007-2017 Cavium, Inc. |
4c076fb4 | 5 | * |
3d588c93 AK |
6 | * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>. |
7 | * | |
4c076fb4 DD |
8 | * Some parts derived from wdt.c |
9 | * | |
10 | * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>, | |
11 | * All Rights Reserved. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | * | |
18 | * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide | |
19 | * warranty for any of this software. This material is provided | |
20 | * "AS-IS" and at no charge. | |
21 | * | |
22 | * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> | |
23 | * | |
24 | * This file is subject to the terms and conditions of the GNU General Public | |
25 | * License. See the file "COPYING" in the main directory of this archive | |
26 | * for more details. | |
27 | * | |
28 | * | |
29 | * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock. | |
30 | * For most systems this is less than 10 seconds, so to allow for | |
31 | * software to request longer watchdog heartbeats, we maintain software | |
32 | * counters to count multiples of the base rate. If the system locks | |
33 | * up in such a manner that we can not run the software counters, the | |
34 | * only result is a watchdog reset sooner than was requested. But | |
35 | * that is OK, because in this case userspace would likely not be able | |
36 | * to do anything anyhow. | |
37 | * | |
38 | * The hardware watchdog interval we call the period. The OCTEON | |
39 | * watchdog goes through several stages, after the first period an | |
40 | * irq is asserted, then if it is not reset, after the next period NMI | |
41 | * is asserted, then after an additional period a chip wide soft reset. | |
42 | * So for the software counters, we reset watchdog after each period | |
43 | * and decrement the counter. But for the last two periods we need to | |
44 | * let the watchdog progress to the NMI stage so we disable the irq | |
45 | * and let it proceed. Once in the NMI, we print the register state | |
46 | * to the serial port and then wait for the reset. | |
47 | * | |
48 | * A watchdog is maintained for each CPU in the system, that way if | |
49 | * one CPU suffers a lockup, we also get a register dump and reset. | |
50 | * The userspace ping resets the watchdog on all CPUs. | |
51 | * | |
52 | * Before userspace opens the watchdog device, we still run the | |
53 | * watchdogs to catch any lockups that may be kernel related. | |
54 | * | |
55 | */ | |
56 | ||
27c766aa JP |
57 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
58 | ||
4c076fb4 DD |
59 | #include <linux/interrupt.h> |
60 | #include <linux/watchdog.h> | |
61 | #include <linux/cpumask.h> | |
4c076fb4 | 62 | #include <linux/module.h> |
4c076fb4 DD |
63 | #include <linux/delay.h> |
64 | #include <linux/cpu.h> | |
ca4d3e67 | 65 | #include <linux/irq.h> |
4c076fb4 DD |
66 | |
67 | #include <asm/mipsregs.h> | |
68 | #include <asm/uasm.h> | |
69 | ||
70 | #include <asm/octeon/octeon.h> | |
49d148b4 | 71 | #include <asm/octeon/cvmx-boot-vector.h> |
4c076fb4 DD |
72 | |
73 | /* The count needed to achieve timeout_sec. */ | |
74 | static unsigned int timeout_cnt; | |
75 | ||
76 | /* The maximum period supported. */ | |
77 | static unsigned int max_timeout_sec; | |
78 | ||
79 | /* The current period. */ | |
80 | static unsigned int timeout_sec; | |
81 | ||
82 | /* Set to non-zero when userspace countdown mode active */ | |
381cec02 | 83 | static bool do_countdown; |
4c076fb4 DD |
84 | static unsigned int countdown_reset; |
85 | static unsigned int per_cpu_countdown[NR_CPUS]; | |
86 | ||
87 | static cpumask_t irq_enabled_cpus; | |
88 | ||
89 | #define WD_TIMO 60 /* Default heartbeat = 60 seconds */ | |
90 | ||
91 | static int heartbeat = WD_TIMO; | |
381cec02 | 92 | module_param(heartbeat, int, 0444); |
4c076fb4 DD |
93 | MODULE_PARM_DESC(heartbeat, |
94 | "Watchdog heartbeat in seconds. (0 < heartbeat, default=" | |
95 | __MODULE_STRING(WD_TIMO) ")"); | |
96 | ||
86a1e189 | 97 | static bool nowayout = WATCHDOG_NOWAYOUT; |
381cec02 | 98 | module_param(nowayout, bool, 0444); |
4c076fb4 DD |
99 | MODULE_PARM_DESC(nowayout, |
100 | "Watchdog cannot be stopped once started (default=" | |
101 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
102 | ||
381cec02 SH |
103 | static int disable; |
104 | module_param(disable, int, 0444); | |
105 | MODULE_PARM_DESC(disable, | |
106 | "Disable the watchdog entirely (default=0)"); | |
107 | ||
49d148b4 | 108 | static struct cvmx_boot_vector_element *octeon_wdt_bootvector; |
4c076fb4 DD |
109 | |
110 | void octeon_wdt_nmi_stage2(void); | |
111 | ||
4c076fb4 DD |
112 | static int cpu2core(int cpu) |
113 | { | |
114 | #ifdef CONFIG_SMP | |
115 | return cpu_logical_map(cpu); | |
116 | #else | |
117 | return cvmx_get_core_num(); | |
118 | #endif | |
119 | } | |
120 | ||
121 | static int core2cpu(int coreid) | |
122 | { | |
123 | #ifdef CONFIG_SMP | |
124 | return cpu_number_map(coreid); | |
125 | #else | |
126 | return 0; | |
127 | #endif | |
128 | } | |
129 | ||
130 | /** | |
131 | * Poke the watchdog when an interrupt is received | |
132 | * | |
133 | * @cpl: | |
134 | * @dev_id: | |
135 | * | |
136 | * Returns | |
137 | */ | |
138 | static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) | |
139 | { | |
140 | unsigned int core = cvmx_get_core_num(); | |
141 | int cpu = core2cpu(core); | |
142 | ||
381cec02 | 143 | if (do_countdown) { |
4c076fb4 DD |
144 | if (per_cpu_countdown[cpu] > 0) { |
145 | /* We're alive, poke the watchdog */ | |
146 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
147 | per_cpu_countdown[cpu]--; | |
148 | } else { | |
149 | /* Bad news, you are about to reboot. */ | |
150 | disable_irq_nosync(cpl); | |
151 | cpumask_clear_cpu(cpu, &irq_enabled_cpus); | |
152 | } | |
153 | } else { | |
154 | /* Not open, just ping away... */ | |
155 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
156 | } | |
157 | return IRQ_HANDLED; | |
158 | } | |
159 | ||
160 | /* From setup.c */ | |
161 | extern int prom_putchar(char c); | |
162 | ||
163 | /** | |
164 | * Write a string to the uart | |
165 | * | |
166 | * @str: String to write | |
167 | */ | |
168 | static void octeon_wdt_write_string(const char *str) | |
169 | { | |
170 | /* Just loop writing one byte at a time */ | |
171 | while (*str) | |
172 | prom_putchar(*str++); | |
173 | } | |
174 | ||
175 | /** | |
176 | * Write a hex number out of the uart | |
177 | * | |
178 | * @value: Number to display | |
179 | * @digits: Number of digits to print (1 to 16) | |
180 | */ | |
181 | static void octeon_wdt_write_hex(u64 value, int digits) | |
182 | { | |
183 | int d; | |
184 | int v; | |
8692cf0a | 185 | |
4c076fb4 DD |
186 | for (d = 0; d < digits; d++) { |
187 | v = (value >> ((digits - d - 1) * 4)) & 0xf; | |
188 | if (v >= 10) | |
189 | prom_putchar('a' + v - 10); | |
190 | else | |
191 | prom_putchar('0' + v); | |
192 | } | |
193 | } | |
194 | ||
3a30c07e | 195 | static const char reg_name[][3] = { |
4c076fb4 DD |
196 | "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
197 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
198 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
199 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
200 | }; | |
201 | ||
202 | /** | |
203 | * NMI stage 3 handler. NMIs are handled in the following manner: | |
204 | * 1) The first NMI handler enables CVMSEG and transfers from | |
205 | * the bootbus region into normal memory. It is careful to not | |
206 | * destroy any registers. | |
207 | * 2) The second stage handler uses CVMSEG to save the registers | |
208 | * and create a stack for C code. It then calls the third level | |
209 | * handler with one argument, a pointer to the register values. | |
210 | * 3) The third, and final, level handler is the following C | |
211 | * function that prints out some useful infomration. | |
212 | * | |
213 | * @reg: Pointer to register state before the NMI | |
214 | */ | |
215 | void octeon_wdt_nmi_stage3(u64 reg[32]) | |
216 | { | |
217 | u64 i; | |
218 | ||
219 | unsigned int coreid = cvmx_get_core_num(); | |
220 | /* | |
221 | * Save status and cause early to get them before any changes | |
222 | * might happen. | |
223 | */ | |
224 | u64 cp0_cause = read_c0_cause(); | |
225 | u64 cp0_status = read_c0_status(); | |
226 | u64 cp0_error_epc = read_c0_errorepc(); | |
227 | u64 cp0_epc = read_c0_epc(); | |
228 | ||
229 | /* Delay so output from all cores output is not jumbled together. */ | |
230 | __delay(100000000ull * coreid); | |
231 | ||
232 | octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x"); | |
233 | octeon_wdt_write_hex(coreid, 1); | |
234 | octeon_wdt_write_string(" ***\r\n"); | |
235 | for (i = 0; i < 32; i++) { | |
236 | octeon_wdt_write_string("\t"); | |
237 | octeon_wdt_write_string(reg_name[i]); | |
238 | octeon_wdt_write_string("\t0x"); | |
239 | octeon_wdt_write_hex(reg[i], 16); | |
240 | if (i & 1) | |
241 | octeon_wdt_write_string("\r\n"); | |
242 | } | |
243 | octeon_wdt_write_string("\terr_epc\t0x"); | |
244 | octeon_wdt_write_hex(cp0_error_epc, 16); | |
245 | ||
246 | octeon_wdt_write_string("\tepc\t0x"); | |
247 | octeon_wdt_write_hex(cp0_epc, 16); | |
248 | octeon_wdt_write_string("\r\n"); | |
249 | ||
250 | octeon_wdt_write_string("\tstatus\t0x"); | |
251 | octeon_wdt_write_hex(cp0_status, 16); | |
252 | octeon_wdt_write_string("\tcause\t0x"); | |
253 | octeon_wdt_write_hex(cp0_cause, 16); | |
254 | octeon_wdt_write_string("\r\n"); | |
255 | ||
256 | octeon_wdt_write_string("\tsum0\t0x"); | |
257 | octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); | |
258 | octeon_wdt_write_string("\ten0\t0x"); | |
259 | octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); | |
260 | octeon_wdt_write_string("\r\n"); | |
261 | ||
262 | octeon_wdt_write_string("*** Chip soft reset soon ***\r\n"); | |
263 | } | |
264 | ||
948b9c60 | 265 | static int octeon_wdt_cpu_pre_down(unsigned int cpu) |
4c076fb4 DD |
266 | { |
267 | unsigned int core; | |
268 | unsigned int irq; | |
269 | union cvmx_ciu_wdogx ciu_wdog; | |
270 | ||
271 | core = cpu2core(cpu); | |
272 | ||
273 | irq = OCTEON_IRQ_WDOG0 + core; | |
274 | ||
275 | /* Poke the watchdog to clear out its state */ | |
276 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
277 | ||
278 | /* Disable the hardware. */ | |
279 | ciu_wdog.u64 = 0; | |
280 | cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); | |
281 | ||
282 | free_irq(irq, octeon_wdt_poke_irq); | |
948b9c60 | 283 | return 0; |
4c076fb4 DD |
284 | } |
285 | ||
948b9c60 | 286 | static int octeon_wdt_cpu_online(unsigned int cpu) |
4c076fb4 DD |
287 | { |
288 | unsigned int core; | |
289 | unsigned int irq; | |
290 | union cvmx_ciu_wdogx ciu_wdog; | |
291 | ||
292 | core = cpu2core(cpu); | |
293 | ||
49d148b4 SH |
294 | octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2; |
295 | ||
4c076fb4 DD |
296 | /* Disable it before doing anything with the interrupts. */ |
297 | ciu_wdog.u64 = 0; | |
298 | cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); | |
299 | ||
300 | per_cpu_countdown[cpu] = countdown_reset; | |
301 | ||
302 | irq = OCTEON_IRQ_WDOG0 + core; | |
303 | ||
304 | if (request_irq(irq, octeon_wdt_poke_irq, | |
47bfd058 | 305 | IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) |
4c076fb4 DD |
306 | panic("octeon_wdt: Couldn't obtain irq %d", irq); |
307 | ||
308 | cpumask_set_cpu(cpu, &irq_enabled_cpus); | |
309 | ||
310 | /* Poke the watchdog to clear out its state */ | |
311 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
312 | ||
313 | /* Finally enable the watchdog now that all handlers are installed */ | |
314 | ciu_wdog.u64 = 0; | |
315 | ciu_wdog.s.len = timeout_cnt; | |
316 | ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ | |
317 | cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); | |
4c076fb4 | 318 | |
948b9c60 | 319 | return 0; |
4c076fb4 DD |
320 | } |
321 | ||
3d588c93 | 322 | static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog) |
4c076fb4 DD |
323 | { |
324 | int cpu; | |
325 | int coreid; | |
326 | ||
381cec02 SH |
327 | if (disable) |
328 | return 0; | |
329 | ||
4c076fb4 DD |
330 | for_each_online_cpu(cpu) { |
331 | coreid = cpu2core(cpu); | |
332 | cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); | |
333 | per_cpu_countdown[cpu] = countdown_reset; | |
381cec02 | 334 | if ((countdown_reset || !do_countdown) && |
4c076fb4 DD |
335 | !cpumask_test_cpu(cpu, &irq_enabled_cpus)) { |
336 | /* We have to enable the irq */ | |
337 | int irq = OCTEON_IRQ_WDOG0 + coreid; | |
8692cf0a | 338 | |
4c076fb4 DD |
339 | enable_irq(irq); |
340 | cpumask_set_cpu(cpu, &irq_enabled_cpus); | |
341 | } | |
342 | } | |
3d588c93 | 343 | return 0; |
4c076fb4 DD |
344 | } |
345 | ||
346 | static void octeon_wdt_calc_parameters(int t) | |
347 | { | |
348 | unsigned int periods; | |
349 | ||
350 | timeout_sec = max_timeout_sec; | |
351 | ||
352 | ||
353 | /* | |
354 | * Find the largest interrupt period, that can evenly divide | |
355 | * the requested heartbeat time. | |
356 | */ | |
357 | while ((t % timeout_sec) != 0) | |
358 | timeout_sec--; | |
359 | ||
360 | periods = t / timeout_sec; | |
361 | ||
362 | /* | |
363 | * The last two periods are after the irq is disabled, and | |
364 | * then to the nmi, so we subtract them off. | |
365 | */ | |
366 | ||
367 | countdown_reset = periods > 2 ? periods - 2 : 0; | |
368 | heartbeat = t; | |
468ffde4 | 369 | timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8; |
4c076fb4 DD |
370 | } |
371 | ||
3d588c93 AK |
372 | static int octeon_wdt_set_timeout(struct watchdog_device *wdog, |
373 | unsigned int t) | |
4c076fb4 DD |
374 | { |
375 | int cpu; | |
376 | int coreid; | |
377 | union cvmx_ciu_wdogx ciu_wdog; | |
378 | ||
379 | if (t <= 0) | |
380 | return -1; | |
381 | ||
382 | octeon_wdt_calc_parameters(t); | |
383 | ||
381cec02 SH |
384 | if (disable) |
385 | return 0; | |
386 | ||
4c076fb4 DD |
387 | for_each_online_cpu(cpu) { |
388 | coreid = cpu2core(cpu); | |
389 | cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); | |
390 | ciu_wdog.u64 = 0; | |
391 | ciu_wdog.s.len = timeout_cnt; | |
392 | ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ | |
393 | cvmx_write_csr(CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); | |
394 | cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); | |
395 | } | |
3d588c93 | 396 | octeon_wdt_ping(wdog); /* Get the irqs back on. */ |
4c076fb4 DD |
397 | return 0; |
398 | } | |
399 | ||
3d588c93 | 400 | static int octeon_wdt_start(struct watchdog_device *wdog) |
4c076fb4 | 401 | { |
3d588c93 | 402 | octeon_wdt_ping(wdog); |
381cec02 | 403 | do_countdown = 1; |
3d588c93 | 404 | return 0; |
4c076fb4 DD |
405 | } |
406 | ||
3d588c93 | 407 | static int octeon_wdt_stop(struct watchdog_device *wdog) |
4c076fb4 | 408 | { |
381cec02 | 409 | do_countdown = 0; |
3d588c93 | 410 | octeon_wdt_ping(wdog); |
4c076fb4 DD |
411 | return 0; |
412 | } | |
413 | ||
3d588c93 AK |
414 | static const struct watchdog_info octeon_wdt_info = { |
415 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, | |
416 | .identity = "OCTEON", | |
4c076fb4 DD |
417 | }; |
418 | ||
3d588c93 AK |
419 | static const struct watchdog_ops octeon_wdt_ops = { |
420 | .owner = THIS_MODULE, | |
421 | .start = octeon_wdt_start, | |
422 | .stop = octeon_wdt_stop, | |
423 | .ping = octeon_wdt_ping, | |
424 | .set_timeout = octeon_wdt_set_timeout, | |
4c076fb4 DD |
425 | }; |
426 | ||
3d588c93 AK |
427 | static struct watchdog_device octeon_wdt = { |
428 | .info = &octeon_wdt_info, | |
429 | .ops = &octeon_wdt_ops, | |
430 | }; | |
4c076fb4 | 431 | |
948b9c60 | 432 | static enum cpuhp_state octeon_wdt_online; |
4c076fb4 DD |
433 | /** |
434 | * Module/ driver initialization. | |
435 | * | |
436 | * Returns Zero on success | |
437 | */ | |
438 | static int __init octeon_wdt_init(void) | |
439 | { | |
440 | int i; | |
441 | int ret; | |
4c076fb4 DD |
442 | u64 *ptr; |
443 | ||
49d148b4 SH |
444 | octeon_wdt_bootvector = cvmx_boot_vector_get(); |
445 | if (!octeon_wdt_bootvector) { | |
446 | pr_err("Error: Cannot allocate boot vector.\n"); | |
447 | return -ENOMEM; | |
448 | } | |
449 | ||
4c076fb4 DD |
450 | /* |
451 | * Watchdog time expiration length = The 16 bits of LEN | |
452 | * represent the most significant bits of a 24 bit decrementer | |
453 | * that decrements every 256 cycles. | |
454 | * | |
455 | * Try for a timeout of 5 sec, if that fails a smaller number | |
456 | * of even seconds, | |
457 | */ | |
458 | max_timeout_sec = 6; | |
459 | do { | |
460 | max_timeout_sec--; | |
8692cf0a AK |
461 | timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * |
462 | max_timeout_sec) >> 8; | |
4c076fb4 DD |
463 | } while (timeout_cnt > 65535); |
464 | ||
465 | BUG_ON(timeout_cnt == 0); | |
466 | ||
467 | octeon_wdt_calc_parameters(heartbeat); | |
468 | ||
27c766aa | 469 | pr_info("Initial granularity %d Sec\n", timeout_sec); |
4c076fb4 | 470 | |
3d588c93 AK |
471 | octeon_wdt.timeout = timeout_sec; |
472 | octeon_wdt.max_timeout = UINT_MAX; | |
473 | ||
474 | watchdog_set_nowayout(&octeon_wdt, nowayout); | |
475 | ||
476 | ret = watchdog_register_device(&octeon_wdt); | |
4c076fb4 | 477 | if (ret) { |
3d588c93 AK |
478 | pr_err("watchdog_register_device() failed: %d\n", ret); |
479 | return ret; | |
4c076fb4 DD |
480 | } |
481 | ||
381cec02 SH |
482 | if (disable) { |
483 | pr_notice("disabled\n"); | |
484 | return 0; | |
485 | } | |
486 | ||
4c076fb4 DD |
487 | cpumask_clear(&irq_enabled_cpus); |
488 | ||
948b9c60 SAS |
489 | ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online", |
490 | octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down); | |
491 | if (ret < 0) | |
492 | goto err; | |
493 | octeon_wdt_online = ret; | |
3d588c93 | 494 | return 0; |
948b9c60 SAS |
495 | err: |
496 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); | |
497 | watchdog_unregister_device(&octeon_wdt); | |
498 | return ret; | |
4c076fb4 DD |
499 | } |
500 | ||
501 | /** | |
502 | * Module / driver shutdown | |
503 | */ | |
504 | static void __exit octeon_wdt_cleanup(void) | |
505 | { | |
3d588c93 | 506 | watchdog_unregister_device(&octeon_wdt); |
381cec02 SH |
507 | |
508 | if (disable) | |
509 | return; | |
510 | ||
948b9c60 | 511 | cpuhp_remove_state(octeon_wdt_online); |
99c3bf36 | 512 | |
4c076fb4 DD |
513 | /* |
514 | * Disable the boot-bus memory, the code it points to is soon | |
515 | * to go missing. | |
516 | */ | |
517 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); | |
518 | } | |
519 | ||
520 | MODULE_LICENSE("GPL"); | |
381cec02 SH |
521 | MODULE_AUTHOR("Cavium Inc. <support@cavium.com>"); |
522 | MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver."); | |
4c076fb4 DD |
523 | module_init(octeon_wdt_init); |
524 | module_exit(octeon_wdt_cleanup); |