[linux-2.6-block.git] / drivers / watchdog / mtk_wdt.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Mediatek Watchdog Driver
 *
 * Copyright (C) 2014 Matthias Brugger
 *
 * Matthias Brugger <matthias.bgg@gmail.com>
 *
 * Based on sunxi_wdt.c
 */

#include <dt-bindings/reset/mt2712-resets.h>
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
#include <dt-bindings/reset/mt7986-resets.h>
#include <dt-bindings/reset/mt8183-resets.h>
#include <dt-bindings/reset/mt8186-resets.h>
#include <dt-bindings/reset/mt8188-resets.h>
#include <dt-bindings/reset/mt8192-resets.h>
#include <dt-bindings/reset/mt8195-resets.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/interrupt.h>

#define WDT_MAX_TIMEOUT		31
#define WDT_MIN_TIMEOUT		2
#define WDT_LENGTH_TIMEOUT(n)	((n) << 5)

#define WDT_LENGTH		0x04
#define WDT_LENGTH_KEY		0x8

#define WDT_RST			0x08
#define WDT_RST_RELOAD		0x1971

#define WDT_MODE		0x00
#define WDT_MODE_EN		(1 << 0)
#define WDT_MODE_EXT_POL_LOW	(0 << 1)
#define WDT_MODE_EXT_POL_HIGH	(1 << 1)
#define WDT_MODE_EXRST_EN	(1 << 2)
#define WDT_MODE_IRQ_EN		(1 << 3)
#define WDT_MODE_AUTO_START	(1 << 4)
#define WDT_MODE_DUAL_EN	(1 << 6)
#define WDT_MODE_CNT_SEL	(1 << 8)
#define WDT_MODE_KEY		0x22000000

#define WDT_SWRST		0x14
#define WDT_SWRST_KEY		0x1209

#define WDT_SWSYSRST		0x18U
#define WDT_SWSYS_RST_KEY	0x88000000

#define DRV_NAME		"mtk-wdt"
#define DRV_VERSION		"1.0"

static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned int timeout;

struct mtk_wdt_dev {
	struct watchdog_device wdt_dev;
	void __iomem *wdt_base;
	spinlock_t lock; /* protects WDT_SWSYSRST reg */
	struct reset_controller_dev rcdev;
	bool disable_wdt_extrst;
	bool reset_by_toprgu;
};

struct mtk_wdt_data {
	int toprgu_sw_rst_num;
};

static const struct mtk_wdt_data mt2712_data = {
	.toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
};

static const struct mtk_wdt_data mt6795_data = {
	.toprgu_sw_rst_num = MT6795_TOPRGU_SW_RST_NUM,
};

static const struct mtk_wdt_data mt7986_data = {
	.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
};

static const struct mtk_wdt_data mt8183_data = {
	.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
};

static const struct mtk_wdt_data mt8186_data = {
	.toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM,
};

static const struct mtk_wdt_data mt8188_data = {
	.toprgu_sw_rst_num = MT8188_TOPRGU_SW_RST_NUM,
};

static const struct mtk_wdt_data mt8192_data = {
	.toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
};

static const struct mtk_wdt_data mt8195_data = {
	.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
};

static int toprgu_reset_update(struct reset_controller_dev *rcdev,
			       unsigned long id, bool assert)
{
	unsigned int tmp;
	unsigned long flags;
	struct mtk_wdt_dev *data =
		 container_of(rcdev, struct mtk_wdt_dev, rcdev);

	spin_lock_irqsave(&data->lock, flags);

	tmp = readl(data->wdt_base + WDT_SWSYSRST);
	if (assert)
		tmp |= BIT(id);
	else
		tmp &= ~BIT(id);
	tmp |= WDT_SWSYS_RST_KEY;
	writel(tmp, data->wdt_base + WDT_SWSYSRST);

	spin_unlock_irqrestore(&data->lock, flags);

	return 0;
}

static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
			       unsigned long id)
{
	return toprgu_reset_update(rcdev, id, true);
}

static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
				 unsigned long id)
{
	return toprgu_reset_update(rcdev, id, false);
}

static int toprgu_reset(struct reset_controller_dev *rcdev,
			unsigned long id)
{
	int ret;

	ret = toprgu_reset_assert(rcdev, id);
	if (ret)
		return ret;

	return toprgu_reset_deassert(rcdev, id);
}

static const struct reset_control_ops toprgu_reset_ops = {
	.assert = toprgu_reset_assert,
	.deassert = toprgu_reset_deassert,
	.reset = toprgu_reset,
};

static int toprgu_register_reset_controller(struct platform_device *pdev,
					    int rst_num)
{
	int ret;
	struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);

	spin_lock_init(&mtk_wdt->lock);

	mtk_wdt->rcdev.owner = THIS_MODULE;
	mtk_wdt->rcdev.nr_resets = rst_num;
	mtk_wdt->rcdev.ops = &toprgu_reset_ops;
	mtk_wdt->rcdev.of_node = pdev->dev.of_node;
	ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
	if (ret != 0)
		dev_err(&pdev->dev,
			"couldn't register wdt reset controller: %d\n", ret);
	return ret;
}

static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
			   unsigned long action, void *data)
{
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base;

	wdt_base = mtk_wdt->wdt_base;

	while (1) {
		writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
		mdelay(5);
	}

	return 0;
}

static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
{
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = mtk_wdt->wdt_base;

	iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);

	return 0;
}

static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
				unsigned int timeout)
{
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = mtk_wdt->wdt_base;
	u32 reg;

	wdt_dev->timeout = timeout;
	/*
	 * In dual mode, irq will be triggered at timeout / 2
	 * the real timeout occurs at timeout
	 */
	if (wdt_dev->pretimeout)
		wdt_dev->pretimeout = timeout / 2;

	/*
	 * One bit is the value of 512 ticks
	 * The clock has 32 KHz
	 */
	reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)
			| WDT_LENGTH_KEY;
	iowrite32(reg, wdt_base + WDT_LENGTH);

	mtk_wdt_ping(wdt_dev);

	return 0;
}

static void mtk_wdt_init(struct watchdog_device *wdt_dev)
{
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base;

	wdt_base = mtk_wdt->wdt_base;

	if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) {
		set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
		mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
	}
}

static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
{
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = mtk_wdt->wdt_base;
	u32 reg;

	reg = readl(wdt_base + WDT_MODE);
	reg &= ~WDT_MODE_EN;
	reg |= WDT_MODE_KEY;
	iowrite32(reg, wdt_base + WDT_MODE);

	return 0;
}

static int mtk_wdt_start(struct watchdog_device *wdt_dev)
{
	u32 reg;
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = mtk_wdt->wdt_base;
	int ret;

	ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
	if (ret < 0)
		return ret;

	reg = ioread32(wdt_base + WDT_MODE);
	if (wdt_dev->pretimeout)
		reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
	else
		reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
	if (mtk_wdt->disable_wdt_extrst)
		reg &= ~WDT_MODE_EXRST_EN;
	if (mtk_wdt->reset_by_toprgu)
		reg |= WDT_MODE_CNT_SEL;
	reg |= (WDT_MODE_EN | WDT_MODE_KEY);
	iowrite32(reg, wdt_base + WDT_MODE);

	return 0;
}

static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd,
				  unsigned int timeout)
{
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd);
	void __iomem *wdt_base = mtk_wdt->wdt_base;
	u32 reg = ioread32(wdt_base + WDT_MODE);

	if (timeout && !wdd->pretimeout) {
		wdd->pretimeout = wdd->timeout / 2;
		reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
	} else if (!timeout && wdd->pretimeout) {
		wdd->pretimeout = 0;
		reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
	} else {
		return 0;
	}

	reg |= WDT_MODE_KEY;
	iowrite32(reg, wdt_base + WDT_MODE);

	return mtk_wdt_set_timeout(wdd, wdd->timeout);
}

static irqreturn_t mtk_wdt_isr(int irq, void *arg)
{
	struct watchdog_device *wdd = arg;

	watchdog_notify_pretimeout(wdd);

	return IRQ_HANDLED;
}

static const struct watchdog_info mtk_wdt_info = {
	.identity	= DRV_NAME,
	.options	= WDIOF_SETTIMEOUT |
			  WDIOF_KEEPALIVEPING |
			  WDIOF_MAGICCLOSE,
};

static const struct watchdog_info mtk_wdt_pt_info = {
	.identity	= DRV_NAME,
	.options	= WDIOF_SETTIMEOUT |
			  WDIOF_PRETIMEOUT |
			  WDIOF_KEEPALIVEPING |
			  WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops mtk_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= mtk_wdt_start,
	.stop		= mtk_wdt_stop,
	.ping		= mtk_wdt_ping,
	.set_timeout	= mtk_wdt_set_timeout,
	.set_pretimeout	= mtk_wdt_set_pretimeout,
	.restart	= mtk_wdt_restart,
};

static int mtk_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct mtk_wdt_dev *mtk_wdt;
	const struct mtk_wdt_data *wdt_data;
	int err, irq;

	mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
	if (!mtk_wdt)
		return -ENOMEM;

	platform_set_drvdata(pdev, mtk_wdt);

	mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(mtk_wdt->wdt_base))
		return PTR_ERR(mtk_wdt->wdt_base);

	irq = platform_get_irq_optional(pdev, 0);
	if (irq > 0) {
		err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",
				       &mtk_wdt->wdt_dev);
		if (err)
			return err;

		mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;
		mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;
	} else {
		if (irq == -EPROBE_DEFER)
			return -EPROBE_DEFER;

		mtk_wdt->wdt_dev.info = &mtk_wdt_info;
	}

	mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
	mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
	mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
	mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
	mtk_wdt->wdt_dev.parent = dev;

	watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
	watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
	watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);

	watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);

	mtk_wdt_init(&mtk_wdt->wdt_dev);

	watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
	err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
	if (unlikely(err))
		return err;

	dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
		 mtk_wdt->wdt_dev.timeout, nowayout);

	wdt_data = of_device_get_match_data(dev);
	if (wdt_data) {
		err = toprgu_register_reset_controller(pdev,
						       wdt_data->toprgu_sw_rst_num);
		if (err)
			return err;
	}

	mtk_wdt->disable_wdt_extrst =
		of_property_read_bool(dev->of_node, "mediatek,disable-extrst");

	mtk_wdt->reset_by_toprgu =
		of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu");

	return 0;
}

static int mtk_wdt_suspend(struct device *dev)
{
	struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);

	if (watchdog_active(&mtk_wdt->wdt_dev))
		mtk_wdt_stop(&mtk_wdt->wdt_dev);

	return 0;
}

static int mtk_wdt_resume(struct device *dev)
{
	struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);

	if (watchdog_active(&mtk_wdt->wdt_dev)) {
		mtk_wdt_start(&mtk_wdt->wdt_dev);
		mtk_wdt_ping(&mtk_wdt->wdt_dev);
	}

	return 0;
}

static const struct of_device_id mtk_wdt_dt_ids[] = {
	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
	{ .compatible = "mediatek,mt6589-wdt" },
	{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
	{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
	{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
	{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);

static DEFINE_SIMPLE_DEV_PM_OPS(mtk_wdt_pm_ops,
				mtk_wdt_suspend, mtk_wdt_resume);

static struct platform_driver mtk_wdt_driver = {
	.probe		= mtk_wdt_probe,
	.driver		= {
		.name		= DRV_NAME,
		.pm		= pm_sleep_ptr(&mtk_wdt_pm_ops),
		.of_match_table	= mtk_wdt_dt_ids,
	},
};

module_platform_driver(mtk_wdt_driver);

module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
			__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
2e62c498	1	// SPDX-License-Identifier: GPL-2.0+
a44a4553 MB	2	/*
	3	* Mediatek Watchdog Driver
	4	*
	5	* Copyright (C) 2014 Matthias Brugger
	6	*
	7	* Matthias Brugger <matthias.bgg@gmail.com>
	8	*
a44a4553 MB	9	* Based on sunxi_wdt.c
	10	*/
	11
f07c776f	12	#include <dt-bindings/reset/mt2712-resets.h>
28927f6c	13	#include <dt-bindings/reset/mediatek,mt6795-resets.h>
711a5b25	14	#include <dt-bindings/reset/mt7986-resets.h>
f07c776f	15	#include <dt-bindings/reset/mt8183-resets.h>
4dbabc4d	16	#include <dt-bindings/reset/mt8186-resets.h>
bc731365	17	#include <dt-bindings/reset/mt8188-resets.h>
f07c776f	18	#include <dt-bindings/reset/mt8192-resets.h>
8c6b5ea6	19	#include <dt-bindings/reset/mt8195-resets.h>
c254e103	20	#include <linux/delay.h>
a44a4553 MB	21	#include <linux/err.h>
	22	#include <linux/init.h>
	23	#include <linux/io.h>
	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/moduleparam.h>
	27	#include <linux/of.h>
c254e103	28	#include <linux/of_device.h>
a44a4553	29	#include <linux/platform_device.h>
c254e103	30	#include <linux/reset-controller.h>
a44a4553 MB	31	#include <linux/types.h>
a44a4553 MB	32	#include <linux/watchdog.h>
1bbce779	33	#include <linux/interrupt.h>
a44a4553 MB	34
a44a4553 MB	35	#define WDT_MAX_TIMEOUT 31
1bbce779	36	#define WDT_MIN_TIMEOUT 2
a44a4553 MB	37	#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
	38
	39	#define WDT_LENGTH 0x04
	40	#define WDT_LENGTH_KEY 0x8
	41
	42	#define WDT_RST 0x08
	43	#define WDT_RST_RELOAD 0x1971
	44
	45	#define WDT_MODE 0x00
	46	#define WDT_MODE_EN (1 << 0)
	47	#define WDT_MODE_EXT_POL_LOW (0 << 1)
	48	#define WDT_MODE_EXT_POL_HIGH (1 << 1)
	49	#define WDT_MODE_EXRST_EN (1 << 2)
	50	#define WDT_MODE_IRQ_EN (1 << 3)
	51	#define WDT_MODE_AUTO_START (1 << 4)
	52	#define WDT_MODE_DUAL_EN (1 << 6)
a224764f	53	#define WDT_MODE_CNT_SEL (1 << 8)
a44a4553 MB	54	#define WDT_MODE_KEY 0x22000000
	55
	56	#define WDT_SWRST 0x14
	57	#define WDT_SWRST_KEY 0x1209
	58
c254e103	59	#define WDT_SWSYSRST 0x18U
	60	#define WDT_SWSYS_RST_KEY 0x88000000
	61
a44a4553 MB	62	#define DRV_NAME "mtk-wdt"
	63	#define DRV_VERSION "1.0"
	64
	65	static bool nowayout = WATCHDOG_NOWAYOUT;
b82e6953	66	static unsigned int timeout;
a44a4553 MB	67
	68	struct mtk_wdt_dev {
	69	struct watchdog_device wdt_dev;
	70	void __iomem *wdt_base;
c254e103	71	spinlock_t lock; /* protects WDT_SWSYSRST reg */
c254e103	72	struct reset_controller_dev rcdev;
59b0f513	73	bool disable_wdt_extrst;
a224764f	74	bool reset_by_toprgu;
c254e103	75	};
	76
	77	struct mtk_wdt_data {
	78	int toprgu_sw_rst_num;
a44a4553 MB	79	};
a44a4553 MB	80
9e5236e7	81	static const struct mtk_wdt_data mt2712_data = {
	82	.toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
	83	};
	84
28927f6c ADR	85	static const struct mtk_wdt_data mt6795_data = {
	86	.toprgu_sw_rst_num = MT6795_TOPRGU_SW_RST_NUM,
	87	};
	88
711a5b25 SS	89	static const struct mtk_wdt_data mt7986_data = {
	90	.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
	91	};
	92
c254e103	93	static const struct mtk_wdt_data mt8183_data = {
	94	.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
	95	};
	96
4dbabc4d RC	97	static const struct mtk_wdt_data mt8186_data = {
	98	.toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM,
	99	};
	100
bc731365 RC	101	static const struct mtk_wdt_data mt8188_data = {
	102	.toprgu_sw_rst_num = MT8188_TOPRGU_SW_RST_NUM,
	103	};
	104
adc318a3 CG	105	static const struct mtk_wdt_data mt8192_data = {
	106	.toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
	107	};
	108
8c6b5ea6 CZ	109	static const struct mtk_wdt_data mt8195_data = {
	110	.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
	111	};
	112
c254e103	113	static int toprgu_reset_update(struct reset_controller_dev *rcdev,
	114	unsigned long id, bool assert)
	115	{
	116	unsigned int tmp;
	117	unsigned long flags;
	118	struct mtk_wdt_dev *data =
	119	container_of(rcdev, struct mtk_wdt_dev, rcdev);
	120
	121	spin_lock_irqsave(&data->lock, flags);
	122
	123	tmp = readl(data->wdt_base + WDT_SWSYSRST);
	124	if (assert)
	125	tmp \|= BIT(id);
	126	else
	127	tmp &= ~BIT(id);
	128	tmp \|= WDT_SWSYS_RST_KEY;
	129	writel(tmp, data->wdt_base + WDT_SWSYSRST);
	130
	131	spin_unlock_irqrestore(&data->lock, flags);
	132
	133	return 0;
	134	}
	135
	136	static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
	137	unsigned long id)
	138	{
	139	return toprgu_reset_update(rcdev, id, true);
	140	}
	141
	142	static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
	143	unsigned long id)
	144	{
	145	return toprgu_reset_update(rcdev, id, false);
	146	}
	147
	148	static int toprgu_reset(struct reset_controller_dev *rcdev,
	149	unsigned long id)
	150	{
	151	int ret;
	152
	153	ret = toprgu_reset_assert(rcdev, id);
	154	if (ret)
	155	return ret;
	156
	157	return toprgu_reset_deassert(rcdev, id);
	158	}
	159
	160	static const struct reset_control_ops toprgu_reset_ops = {
	161	.assert = toprgu_reset_assert,
	162	.deassert = toprgu_reset_deassert,
	163	.reset = toprgu_reset,
	164	};
	165
	166	static int toprgu_register_reset_controller(struct platform_device *pdev,
	167	int rst_num)
	168	{
	169	int ret;
	170	struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
	171
	172	spin_lock_init(&mtk_wdt->lock);
	173
	174	mtk_wdt->rcdev.owner = THIS_MODULE;
	175	mtk_wdt->rcdev.nr_resets = rst_num;
	176	mtk_wdt->rcdev.ops = &toprgu_reset_ops;
177	mtk_wdt->rcdev.of_node = pdev->dev.of_node;
178	ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
179	if (ret != 0)
180	dev_err(&pdev->dev,
181	"couldn't register wdt reset controller: %d\n", ret);
182	return ret;
183	}
184
4d8b229d GR	185	static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
4d8b229d GR	186	unsigned long action, void *data)
a44a4553	187	{
e86adc3f	188	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
a44a4553 MB	189	void __iomem *wdt_base;
a44a4553 MB	190
a44a4553 MB	191	wdt_base = mtk_wdt->wdt_base;
	192
	193	while (1) {
	194	writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
	195	mdelay(5);
	196	}
	197
e86adc3f	198	return 0;
a44a4553 MB	199	}
	200
	201	static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
	202	{
	203	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	204	void __iomem *wdt_base = mtk_wdt->wdt_base;
	205
	206	iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
	207
	208	return 0;
	209	}
	210
	211	static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
	212	unsigned int timeout)
	213	{
	214	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	215	void __iomem *wdt_base = mtk_wdt->wdt_base;
	216	u32 reg;
	217
	218	wdt_dev->timeout = timeout;
1bbce779 WQ	219	/*
	220	* In dual mode, irq will be triggered at timeout / 2
	221	* the real timeout occurs at timeout
	222	*/
	223	if (wdt_dev->pretimeout)
	224	wdt_dev->pretimeout = timeout / 2;
a44a4553 MB	225
	226	/*
	227	* One bit is the value of 512 ticks
	228	* The clock has 32 KHz
	229	*/
1bbce779 WQ	230	reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)
1bbce779 WQ	231	\| WDT_LENGTH_KEY;
a44a4553 MB	232	iowrite32(reg, wdt_base + WDT_LENGTH);
	233
	234	mtk_wdt_ping(wdt_dev);
	235
	236	return 0;
	237	}
	238
bbece05c	239	static void mtk_wdt_init(struct watchdog_device *wdt_dev)
	240	{
	241	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	242	void __iomem *wdt_base;
	243
	244	wdt_base = mtk_wdt->wdt_base;
	245
	246	if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) {
	247	set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
	248	mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
	249	}
	250	}
	251
a44a4553 MB	252	static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
	253	{
	254	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	255	void __iomem *wdt_base = mtk_wdt->wdt_base;
	256	u32 reg;
	257
	258	reg = readl(wdt_base + WDT_MODE);
	259	reg &= ~WDT_MODE_EN;
5da2bf1a	260	reg \|= WDT_MODE_KEY;
a44a4553 MB	261	iowrite32(reg, wdt_base + WDT_MODE);
	262
	263	return 0;
	264	}
	265
	266	static int mtk_wdt_start(struct watchdog_device *wdt_dev)
	267	{
	268	u32 reg;
	269	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	270	void __iomem *wdt_base = mtk_wdt->wdt_base;
9ffd906d	271	int ret;
a44a4553 MB	272
	273	ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
	274	if (ret < 0)
	275	return ret;
	276
	277	reg = ioread32(wdt_base + WDT_MODE);
1bbce779 WQ	278	if (wdt_dev->pretimeout)
	279	reg \|= (WDT_MODE_IRQ_EN \| WDT_MODE_DUAL_EN);
	280	else
	281	reg &= ~(WDT_MODE_IRQ_EN \| WDT_MODE_DUAL_EN);
59b0f513 FC	282	if (mtk_wdt->disable_wdt_extrst)
59b0f513 FC	283	reg &= ~WDT_MODE_EXRST_EN;
a224764f AKC	284	if (mtk_wdt->reset_by_toprgu)
a224764f AKC	285	reg \|= WDT_MODE_CNT_SEL;
a44a4553 MB	286	reg \|= (WDT_MODE_EN \| WDT_MODE_KEY);
	287	iowrite32(reg, wdt_base + WDT_MODE);
	288
	289	return 0;
	290	}
	291
1bbce779 WQ	292	static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd,
	293	unsigned int timeout)
	294	{
	295	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd);
	296	void __iomem *wdt_base = mtk_wdt->wdt_base;
	297	u32 reg = ioread32(wdt_base + WDT_MODE);
	298
	299	if (timeout && !wdd->pretimeout) {
	300	wdd->pretimeout = wdd->timeout / 2;
	301	reg \|= (WDT_MODE_IRQ_EN \| WDT_MODE_DUAL_EN);
	302	} else if (!timeout && wdd->pretimeout) {
	303	wdd->pretimeout = 0;
	304	reg &= ~(WDT_MODE_IRQ_EN \| WDT_MODE_DUAL_EN);
	305	} else {
	306	return 0;
	307	}
	308
	309	reg \|= WDT_MODE_KEY;
	310	iowrite32(reg, wdt_base + WDT_MODE);
	311
	312	return mtk_wdt_set_timeout(wdd, wdd->timeout);
	313	}
	314
	315	static irqreturn_t mtk_wdt_isr(int irq, void *arg)
	316	{
	317	struct watchdog_device *wdd = arg;
	318
	319	watchdog_notify_pretimeout(wdd);
	320
	321	return IRQ_HANDLED;
	322	}
	323
a44a4553 MB	324	static const struct watchdog_info mtk_wdt_info = {
	325	.identity = DRV_NAME,
	326	.options = WDIOF_SETTIMEOUT \|
	327	WDIOF_KEEPALIVEPING \|
	328	WDIOF_MAGICCLOSE,
	329	};
	330
1bbce779 WQ	331	static const struct watchdog_info mtk_wdt_pt_info = {
	332	.identity = DRV_NAME,
	333	.options = WDIOF_SETTIMEOUT \|
	334	WDIOF_PRETIMEOUT \|
	335	WDIOF_KEEPALIVEPING \|
	336	WDIOF_MAGICCLOSE,
	337	};
	338
a44a4553 MB	339	static const struct watchdog_ops mtk_wdt_ops = {
	340	.owner = THIS_MODULE,
	341	.start = mtk_wdt_start,
	342	.stop = mtk_wdt_stop,
	343	.ping = mtk_wdt_ping,
	344	.set_timeout = mtk_wdt_set_timeout,
1bbce779	345	.set_pretimeout = mtk_wdt_set_pretimeout,
e86adc3f	346	.restart = mtk_wdt_restart,
a44a4553 MB	347	};
	348
	349	static int mtk_wdt_probe(struct platform_device *pdev)
	350	{
a15f6e64	351	struct device *dev = &pdev->dev;
a44a4553	352	struct mtk_wdt_dev *mtk_wdt;
c254e103	353	const struct mtk_wdt_data *wdt_data;
1bbce779	354	int err, irq;
a44a4553	355
a15f6e64	356	mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
a44a4553 MB	357	if (!mtk_wdt)
	358	return -ENOMEM;
	359
	360	platform_set_drvdata(pdev, mtk_wdt);
	361
0f0a6a28	362	mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
a44a4553 MB	363	if (IS_ERR(mtk_wdt->wdt_base))
	364	return PTR_ERR(mtk_wdt->wdt_base);
	365
1bafac47	366	irq = platform_get_irq_optional(pdev, 0);
1bbce779 WQ	367	if (irq > 0) {
	368	err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",
	369	&mtk_wdt->wdt_dev);
	370	if (err)
	371	return err;
	372
	373	mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;
	374	mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;
	375	} else {
	376	if (irq == -EPROBE_DEFER)
	377	return -EPROBE_DEFER;
	378
	379	mtk_wdt->wdt_dev.info = &mtk_wdt_info;
	380	}
	381
a44a4553 MB	382	mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
a44a4553 MB	383	mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
bbece05c	384	mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
a44a4553	385	mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
a15f6e64	386	mtk_wdt->wdt_dev.parent = dev;
a44a4553	387
a15f6e64	388	watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
a44a4553	389	watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
e86adc3f	390	watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
a44a4553 MB	391
	392	watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
	393
bbece05c	394	mtk_wdt_init(&mtk_wdt->wdt_dev);
a44a4553	395
a15f6e64 GR	396	watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
a15f6e64 GR	397	err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
a44a4553 MB	398	if (unlikely(err))
	399	return err;
	400
a15f6e64 GR	401	dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
a15f6e64 GR	402	mtk_wdt->wdt_dev.timeout, nowayout);
a44a4553	403
c254e103	404	wdt_data = of_device_get_match_data(dev);
	405	if (wdt_data) {
	406	err = toprgu_register_reset_controller(pdev,
	407	wdt_data->toprgu_sw_rst_num);
	408	if (err)
	409	return err;
	410	}
59b0f513 FC	411
	412	mtk_wdt->disable_wdt_extrst =
	413	of_property_read_bool(dev->of_node, "mediatek,disable-extrst");
	414
a224764f AKC	415	mtk_wdt->reset_by_toprgu =
	416	of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu");
	417
a44a4553 MB	418	return 0;
	419	}
	420
9fab0692 GZ	421	static int mtk_wdt_suspend(struct device *dev)
	422	{
	423	struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
	424
	425	if (watchdog_active(&mtk_wdt->wdt_dev))
	426	mtk_wdt_stop(&mtk_wdt->wdt_dev);
	427
	428	return 0;
	429	}
	430
	431	static int mtk_wdt_resume(struct device *dev)
	432	{
	433	struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
	434
	435	if (watchdog_active(&mtk_wdt->wdt_dev)) {
	436	mtk_wdt_start(&mtk_wdt->wdt_dev);
	437	mtk_wdt_ping(&mtk_wdt->wdt_dev);
	438	}
	439
	440	return 0;
	441	}
9fab0692	442
a44a4553	443	static const struct of_device_id mtk_wdt_dt_ids[] = {
9e5236e7	444	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
a44a4553	445	{ .compatible = "mediatek,mt6589-wdt" },
28927f6c	446	{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
711a5b25	447	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
c254e103	448	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
4dbabc4d	449	{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
bc731365	450	{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
adc318a3	451	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
8c6b5ea6	452	{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
a44a4553 MB	453	{ /* sentinel */ }
	454	};
	455	MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
	456
d4777d0f PC	457	static DEFINE_SIMPLE_DEV_PM_OPS(mtk_wdt_pm_ops,
d4777d0f PC	458	mtk_wdt_suspend, mtk_wdt_resume);
9fab0692	459
a44a4553 MB	460	static struct platform_driver mtk_wdt_driver = {
a44a4553 MB	461	.probe = mtk_wdt_probe,
a44a4553 MB	462	.driver = {
a44a4553 MB	463	.name = DRV_NAME,
d4777d0f	464	.pm = pm_sleep_ptr(&mtk_wdt_pm_ops),
a44a4553 MB	465	.of_match_table = mtk_wdt_dt_ids,
	466	},
	467	};
	468
	469	module_platform_driver(mtk_wdt_driver);
	470
	471	module_param(timeout, uint, 0);
	472	MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
	473
	474	module_param(nowayout, bool, 0);
	475	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	476	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	477
	478	MODULE_LICENSE("GPL");
	479	MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
	480	MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
	481	MODULE_VERSION(DRV_VERSION);