[linux-2.6-block.git] / drivers / watchdog / mt7621_wdt.c

/*
 * Ralink MT7621/MT7628 built-in hardware watchdog timer
 *
 * Copyright (C) 2014 John Crispin <john@phrozen.org>
 *
 * This driver was based on: drivers/watchdog/rt2880_wdt.c
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>

#include <asm/mach-ralink/ralink_regs.h>

#define SYSC_RSTSTAT			0x38
#define WDT_RST_CAUSE			BIT(1)

#define RALINK_WDT_TIMEOUT		30

#define TIMER_REG_TMRSTAT		0x00
#define TIMER_REG_TMR1LOAD		0x24
#define TIMER_REG_TMR1CTL		0x20

#define TMR1CTL_ENABLE			BIT(7)
#define TMR1CTL_RESTART			BIT(9)
#define TMR1CTL_PRESCALE_SHIFT		16

static void __iomem *mt7621_wdt_base;
static struct reset_control *mt7621_wdt_reset;

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
		 "Watchdog cannot be stopped once started (default="
		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static inline void rt_wdt_w32(unsigned reg, u32 val)
{
	iowrite32(val, mt7621_wdt_base + reg);
}

static inline u32 rt_wdt_r32(unsigned reg)
{
	return ioread32(mt7621_wdt_base + reg);
}

static int mt7621_wdt_ping(struct watchdog_device *w)
{
	rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);

	return 0;
}

static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
{
	w->timeout = t;
	rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
	mt7621_wdt_ping(w);

	return 0;
}

static int mt7621_wdt_start(struct watchdog_device *w)
{
	u32 t;

	/* set the prescaler to 1ms == 1000us */
	rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);

	mt7621_wdt_set_timeout(w, w->timeout);

	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
	t |= TMR1CTL_ENABLE;
	rt_wdt_w32(TIMER_REG_TMR1CTL, t);

	return 0;
}

static int mt7621_wdt_stop(struct watchdog_device *w)
{
	u32 t;

	mt7621_wdt_ping(w);

	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
	t &= ~TMR1CTL_ENABLE;
	rt_wdt_w32(TIMER_REG_TMR1CTL, t);

	return 0;
}

static int mt7621_wdt_bootcause(void)
{
	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
		return WDIOF_CARDRESET;

	return 0;
}

static int mt7621_wdt_is_running(struct watchdog_device *w)
{
	return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
}

static const struct watchdog_info mt7621_wdt_info = {
	.identity = "Mediatek Watchdog",
	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops mt7621_wdt_ops = {
	.owner = THIS_MODULE,
	.start = mt7621_wdt_start,
	.stop = mt7621_wdt_stop,
	.ping = mt7621_wdt_ping,
	.set_timeout = mt7621_wdt_set_timeout,
};

static struct watchdog_device mt7621_wdt_dev = {
	.info = &mt7621_wdt_info,
	.ops = &mt7621_wdt_ops,
	.min_timeout = 1,
	.max_timeout = 0xfffful / 1000,
};

static int mt7621_wdt_probe(struct platform_device *pdev)
{
	struct resource *res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mt7621_wdt_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mt7621_wdt_base))
		return PTR_ERR(mt7621_wdt_base);

	mt7621_wdt_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
	if (!IS_ERR(mt7621_wdt_reset))
		reset_control_deassert(mt7621_wdt_reset);

	mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();

	watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
			      &pdev->dev);
	watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);
	if (mt7621_wdt_is_running(&mt7621_wdt_dev)) {
		/*
		 * Make sure to apply timeout from watchdog core, taking
		 * the prescaler of this driver here into account (the
		 * boot loader might be using a different prescaler).
		 *
		 * To avoid spurious resets because of different scaling,
		 * we first disable the watchdog, set the new prescaler
		 * and timeout, and then re-enable the watchdog.
		 */
		mt7621_wdt_stop(&mt7621_wdt_dev);
		mt7621_wdt_start(&mt7621_wdt_dev);
		set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status);
	}

	return devm_watchdog_register_device(&pdev->dev, &mt7621_wdt_dev);
}

static void mt7621_wdt_shutdown(struct platform_device *pdev)
{
	mt7621_wdt_stop(&mt7621_wdt_dev);
}

static const struct of_device_id mt7621_wdt_match[] = {
	{ .compatible = "mediatek,mt7621-wdt" },
	{},
};
MODULE_DEVICE_TABLE(of, mt7621_wdt_match);

static struct platform_driver mt7621_wdt_driver = {
	.probe		= mt7621_wdt_probe,
	.shutdown	= mt7621_wdt_shutdown,
	.driver		= {
		.name		= KBUILD_MODNAME,
		.of_match_table	= mt7621_wdt_match,
	},
};

module_platform_driver(mt7621_wdt_driver);

MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
MODULE_AUTHOR("John Crispin <john@phrozen.org");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ab3f09fe JC	1	/*
	2	* Ralink MT7621/MT7628 built-in hardware watchdog timer
	3	*
f3519a66	4	* Copyright (C) 2014 John Crispin <john@phrozen.org>
ab3f09fe JC	5	*
	6	* This driver was based on: drivers/watchdog/rt2880_wdt.c
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License version 2 as published
	10	* by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/reset.h>
	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/watchdog.h>
	18	#include <linux/moduleparam.h>
	19	#include <linux/platform_device.h>
	20
	21	#include <asm/mach-ralink/ralink_regs.h>
	22
	23	#define SYSC_RSTSTAT 0x38
	24	#define WDT_RST_CAUSE BIT(1)
	25
	26	#define RALINK_WDT_TIMEOUT 30
	27
	28	#define TIMER_REG_TMRSTAT 0x00
	29	#define TIMER_REG_TMR1LOAD 0x24
	30	#define TIMER_REG_TMR1CTL 0x20
	31
	32	#define TMR1CTL_ENABLE BIT(7)
	33	#define TMR1CTL_RESTART BIT(9)
	34	#define TMR1CTL_PRESCALE_SHIFT 16
	35
	36	static void __iomem *mt7621_wdt_base;
	37	static struct reset_control *mt7621_wdt_reset;
	38
	39	static bool nowayout = WATCHDOG_NOWAYOUT;
	40	module_param(nowayout, bool, 0);
	41	MODULE_PARM_DESC(nowayout,
	42	"Watchdog cannot be stopped once started (default="
	43	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	44
	45	static inline void rt_wdt_w32(unsigned reg, u32 val)
	46	{
	47	iowrite32(val, mt7621_wdt_base + reg);
	48	}
	49
	50	static inline u32 rt_wdt_r32(unsigned reg)
	51	{
	52	return ioread32(mt7621_wdt_base + reg);
	53	}
	54
	55	static int mt7621_wdt_ping(struct watchdog_device *w)
	56	{
	57	rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
	58
	59	return 0;
	60	}
	61
	62	static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
	63	{
	64	w->timeout = t;
	65	rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
	66	mt7621_wdt_ping(w);
	67
	68	return 0;
69	}
70
71	static int mt7621_wdt_start(struct watchdog_device *w)
72	{
73	u32 t;
74
75	/* set the prescaler to 1ms == 1000us */
76	rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
77
78	mt7621_wdt_set_timeout(w, w->timeout);
79
80	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
81	t \|= TMR1CTL_ENABLE;
82	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
83
84	return 0;
85	}
86
87	static int mt7621_wdt_stop(struct watchdog_device *w)
88	{
89	u32 t;
90
91	mt7621_wdt_ping(w);
92
93	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
94	t &= ~TMR1CTL_ENABLE;
95	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
96
97	return 0;
98	}
99
100	static int mt7621_wdt_bootcause(void)
101	{
102	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
103	return WDIOF_CARDRESET;
104
105	return 0;
106	}
107
392d39a8 AD	108	static int mt7621_wdt_is_running(struct watchdog_device *w)
	109	{
	110	return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
	111	}
	112
323edb2e	113	static const struct watchdog_info mt7621_wdt_info = {
ab3f09fe JC	114	.identity = "Mediatek Watchdog",
	115	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE,
	116	};
	117
b893e344	118	static const struct watchdog_ops mt7621_wdt_ops = {
ab3f09fe JC	119	.owner = THIS_MODULE,
	120	.start = mt7621_wdt_start,
	121	.stop = mt7621_wdt_stop,
	122	.ping = mt7621_wdt_ping,
	123	.set_timeout = mt7621_wdt_set_timeout,
	124	};
	125
	126	static struct watchdog_device mt7621_wdt_dev = {
	127	.info = &mt7621_wdt_info,
	128	.ops = &mt7621_wdt_ops,
	129	.min_timeout = 1,
	130	.max_timeout = 0xfffful / 1000,
	131	};
	132
	133	static int mt7621_wdt_probe(struct platform_device *pdev)
	134	{
	135	struct resource *res;
ab3f09fe JC	136
	137	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	138	mt7621_wdt_base = devm_ioremap_resource(&pdev->dev, res);
	139	if (IS_ERR(mt7621_wdt_base))
	140	return PTR_ERR(mt7621_wdt_base);
	141
0bade021	142	mt7621_wdt_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
ab3f09fe JC	143	if (!IS_ERR(mt7621_wdt_reset))
	144	reset_control_deassert(mt7621_wdt_reset);
	145
ab3f09fe JC	146	mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();
	147
	148	watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
	149	&pdev->dev);
	150	watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);
392d39a8 AD	151	if (mt7621_wdt_is_running(&mt7621_wdt_dev)) {
	152	/*
	153	* Make sure to apply timeout from watchdog core, taking
	154	* the prescaler of this driver here into account (the
	155	* boot loader might be using a different prescaler).
	156	*
	157	* To avoid spurious resets because of different scaling,
	158	* we first disable the watchdog, set the new prescaler
	159	* and timeout, and then re-enable the watchdog.
	160	*/
	161	mt7621_wdt_stop(&mt7621_wdt_dev);
	162	mt7621_wdt_start(&mt7621_wdt_dev);
	163	set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status);
	164	}
ab3f09fe	165
1d2e5eb5	166	return devm_watchdog_register_device(&pdev->dev, &mt7621_wdt_dev);
ab3f09fe JC	167	}
	168
	169	static void mt7621_wdt_shutdown(struct platform_device *pdev)
	170	{
	171	mt7621_wdt_stop(&mt7621_wdt_dev);
	172	}
	173
	174	static const struct of_device_id mt7621_wdt_match[] = {
	175	{ .compatible = "mediatek,mt7621-wdt" },
	176	{},
	177	};
	178	MODULE_DEVICE_TABLE(of, mt7621_wdt_match);
	179
	180	static struct platform_driver mt7621_wdt_driver = {
	181	.probe = mt7621_wdt_probe,
ab3f09fe JC	182	.shutdown = mt7621_wdt_shutdown,
	183	.driver = {
	184	.name = KBUILD_MODNAME,
	185	.of_match_table = mt7621_wdt_match,
	186	},
	187	};
	188
	189	module_platform_driver(mt7621_wdt_driver);
	190
	191	MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
f3519a66	192	MODULE_AUTHOR("John Crispin <john@phrozen.org");
ab3f09fe	193	MODULE_LICENSE("GPL v2");