[linux-block.git] / drivers / watchdog / mt7621_wdt.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Ralink MT7621/MT7628 built-in hardware watchdog timer
 *
 * Copyright (C) 2014 John Crispin <john@phrozen.org>
 *
 * This driver was based on: drivers/watchdog/rt2880_wdt.c
 */

#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#define SYSC_RSTSTAT			0x38
#define WDT_RST_CAUSE			BIT(1)

#define RALINK_WDT_TIMEOUT		30

#define TIMER_REG_TMRSTAT		0x00
#define TIMER_REG_TMR1LOAD		0x24
#define TIMER_REG_TMR1CTL		0x20

#define TMR1CTL_ENABLE			BIT(7)
#define TMR1CTL_RESTART			BIT(9)
#define TMR1CTL_PRESCALE_SHIFT		16

struct mt7621_wdt_data {
	void __iomem *base;
	struct reset_control *rst;
	struct regmap *sysc;
	struct watchdog_device wdt;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
		 "Watchdog cannot be stopped once started (default="
		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val)
{
	iowrite32(val, base + reg);
}

static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg)
{
	return ioread32(base + reg);
}

static int mt7621_wdt_ping(struct watchdog_device *w)
{
	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);

	rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART);

	return 0;
}

static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
{
	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);

	w->timeout = t;
	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000);
	mt7621_wdt_ping(w);

	return 0;
}

static int mt7621_wdt_start(struct watchdog_device *w)
{
	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
	u32 t;

	/* set the prescaler to 1ms == 1000us */
	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);

	mt7621_wdt_set_timeout(w, w->timeout);

	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
	t |= TMR1CTL_ENABLE;
	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);

	return 0;
}

static int mt7621_wdt_stop(struct watchdog_device *w)
{
	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
	u32 t;

	mt7621_wdt_ping(w);

	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
	t &= ~TMR1CTL_ENABLE;
	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);

	return 0;
}

static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d)
{
	u32 val;

	regmap_read(d->sysc, SYSC_RSTSTAT, &val);
	if (val & WDT_RST_CAUSE)
		return WDIOF_CARDRESET;

	return 0;
}

static int mt7621_wdt_is_running(struct watchdog_device *w)
{
	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);

	return !!(rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
}

static const struct watchdog_info mt7621_wdt_info = {
	.identity = "Mediatek Watchdog",
	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops mt7621_wdt_ops = {
	.owner = THIS_MODULE,
	.start = mt7621_wdt_start,
	.stop = mt7621_wdt_stop,
	.ping = mt7621_wdt_ping,
	.set_timeout = mt7621_wdt_set_timeout,
};

static int mt7621_wdt_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	struct watchdog_device *mt7621_wdt;
	struct mt7621_wdt_data *drvdata;
	int err;

	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
	if (!drvdata)
		return -ENOMEM;

	drvdata->sysc = syscon_regmap_lookup_by_phandle(np, "mediatek,sysctl");
	if (IS_ERR(drvdata->sysc)) {
		drvdata->sysc = syscon_regmap_lookup_by_compatible("mediatek,mt7621-sysc");
		if (IS_ERR(drvdata->sysc))
			return PTR_ERR(drvdata->sysc);
	}

	drvdata->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(drvdata->base))
		return PTR_ERR(drvdata->base);

	drvdata->rst = devm_reset_control_get_exclusive(dev, NULL);
	if (!IS_ERR(drvdata->rst))
		reset_control_deassert(drvdata->rst);

	mt7621_wdt = &drvdata->wdt;
	mt7621_wdt->info = &mt7621_wdt_info;
	mt7621_wdt->ops = &mt7621_wdt_ops;
	mt7621_wdt->min_timeout = 1;
	mt7621_wdt->max_timeout = 0xfffful / 1000;
	mt7621_wdt->parent = dev;

	mt7621_wdt->bootstatus = mt7621_wdt_bootcause(drvdata);

	watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev);
	watchdog_set_nowayout(mt7621_wdt, nowayout);
	watchdog_set_drvdata(mt7621_wdt, drvdata);

	if (mt7621_wdt_is_running(mt7621_wdt)) {
		/*
		 * Make sure to apply timeout from watchdog core, taking
		 * the prescaler of this driver here into account (the
		 * boot loader might be using a different prescaler).
		 *
		 * To avoid spurious resets because of different scaling,
		 * we first disable the watchdog, set the new prescaler
		 * and timeout, and then re-enable the watchdog.
		 */
		mt7621_wdt_stop(mt7621_wdt);
		mt7621_wdt_start(mt7621_wdt);
		set_bit(WDOG_HW_RUNNING, &mt7621_wdt->status);
	}

	err = devm_watchdog_register_device(dev, &drvdata->wdt);
	if (err)
		return err;

	platform_set_drvdata(pdev, drvdata);

	return 0;
}

static void mt7621_wdt_shutdown(struct platform_device *pdev)
{
	struct mt7621_wdt_data *drvdata = platform_get_drvdata(pdev);

	mt7621_wdt_stop(&drvdata->wdt);
}

static const struct of_device_id mt7621_wdt_match[] = {
	{ .compatible = "mediatek,mt7621-wdt" },
	{},
};
MODULE_DEVICE_TABLE(of, mt7621_wdt_match);

static struct platform_driver mt7621_wdt_driver = {
	.probe		= mt7621_wdt_probe,
	.shutdown	= mt7621_wdt_shutdown,
	.driver		= {
		.name		= KBUILD_MODNAME,
		.of_match_table	= mt7621_wdt_match,
	},
};

module_platform_driver(mt7621_wdt_driver);

MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
MODULE_AUTHOR("John Crispin <john@phrozen.org");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
ab3f09fe JC	2	/*
	3	* Ralink MT7621/MT7628 built-in hardware watchdog timer
	4	*
f3519a66	5	* Copyright (C) 2014 John Crispin <john@phrozen.org>
ab3f09fe JC	6	*
ab3f09fe JC	7	* This driver was based on: drivers/watchdog/rt2880_wdt.c
ab3f09fe JC	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/reset.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/watchdog.h>
	15	#include <linux/moduleparam.h>
	16	#include <linux/platform_device.h>
3aa8b8bb	17	#include <linux/mod_devicetable.h>
ff8ec4ac SP	18	#include <linux/mfd/syscon.h>
ff8ec4ac SP	19	#include <linux/regmap.h>
ab3f09fe JC	20
	21	#define SYSC_RSTSTAT 0x38
	22	#define WDT_RST_CAUSE BIT(1)
	23
	24	#define RALINK_WDT_TIMEOUT 30
	25
	26	#define TIMER_REG_TMRSTAT 0x00
	27	#define TIMER_REG_TMR1LOAD 0x24
	28	#define TIMER_REG_TMR1CTL 0x20
	29
	30	#define TMR1CTL_ENABLE BIT(7)
	31	#define TMR1CTL_RESTART BIT(9)
	32	#define TMR1CTL_PRESCALE_SHIFT 16
	33
783c7cb4 SP	34	struct mt7621_wdt_data {
	35	void __iomem *base;
	36	struct reset_control *rst;
ff8ec4ac	37	struct regmap *sysc;
783c7cb4 SP	38	struct watchdog_device wdt;
783c7cb4 SP	39	};
ab3f09fe JC	40
	41	static bool nowayout = WATCHDOG_NOWAYOUT;
	42	module_param(nowayout, bool, 0);
	43	MODULE_PARM_DESC(nowayout,
	44	"Watchdog cannot be stopped once started (default="
	45	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	46
783c7cb4	47	static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val)
ab3f09fe	48	{
783c7cb4	49	iowrite32(val, base + reg);
ab3f09fe JC	50	}
ab3f09fe JC	51
783c7cb4	52	static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg)
ab3f09fe	53	{
783c7cb4	54	return ioread32(base + reg);
ab3f09fe JC	55	}
	56
	57	static int mt7621_wdt_ping(struct watchdog_device *w)
	58	{
783c7cb4 SP	59	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
	60
	61	rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
ab3f09fe JC	62
	63	return 0;
	64	}
	65
	66	static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
	67	{
783c7cb4 SP	68	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
783c7cb4 SP	69
ab3f09fe	70	w->timeout = t;
783c7cb4	71	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000);
ab3f09fe JC	72	mt7621_wdt_ping(w);
	73
	74	return 0;
	75	}
	76
	77	static int mt7621_wdt_start(struct watchdog_device *w)
	78	{
783c7cb4	79	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
ab3f09fe JC	80	u32 t;
	81
	82	/* set the prescaler to 1ms == 1000us */
783c7cb4	83	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
ab3f09fe JC	84
	85	mt7621_wdt_set_timeout(w, w->timeout);
	86
783c7cb4	87	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
ab3f09fe	88	t \|= TMR1CTL_ENABLE;
783c7cb4	89	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
ab3f09fe JC	90
	91	return 0;
	92	}
	93
	94	static int mt7621_wdt_stop(struct watchdog_device *w)
	95	{
783c7cb4	96	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
ab3f09fe JC	97	u32 t;
	98
	99	mt7621_wdt_ping(w);
	100
783c7cb4	101	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
ab3f09fe	102	t &= ~TMR1CTL_ENABLE;
783c7cb4	103	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
ab3f09fe JC	104
	105	return 0;
	106	}
	107
ff8ec4ac	108	static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d)
ab3f09fe	109	{
ff8ec4ac SP	110	u32 val;
	111
	112	regmap_read(d->sysc, SYSC_RSTSTAT, &val);
	113	if (val & WDT_RST_CAUSE)
ab3f09fe JC	114	return WDIOF_CARDRESET;
	115
	116	return 0;
	117	}
	118
392d39a8 AD	119	static int mt7621_wdt_is_running(struct watchdog_device *w)
392d39a8 AD	120	{
783c7cb4 SP	121	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
	122
	123	return !!(rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
392d39a8 AD	124	}
392d39a8 AD	125
323edb2e	126	static const struct watchdog_info mt7621_wdt_info = {
ab3f09fe JC	127	.identity = "Mediatek Watchdog",
	128	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE,
	129	};
	130
b893e344	131	static const struct watchdog_ops mt7621_wdt_ops = {
ab3f09fe JC	132	.owner = THIS_MODULE,
	133	.start = mt7621_wdt_start,
	134	.stop = mt7621_wdt_stop,
	135	.ping = mt7621_wdt_ping,
	136	.set_timeout = mt7621_wdt_set_timeout,
	137	};
	138
ab3f09fe JC	139	static int mt7621_wdt_probe(struct platform_device *pdev)
ab3f09fe JC	140	{
ff8ec4ac	141	struct device_node *np = pdev->dev.of_node;
6fef817e	142	struct device *dev = &pdev->dev;
783c7cb4 SP	143	struct watchdog_device *mt7621_wdt;
	144	struct mt7621_wdt_data *drvdata;
	145	int err;
	146
	147	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
	148	if (!drvdata)
	149	return -ENOMEM;
ab3f09fe	150
ff8ec4ac SP	151	drvdata->sysc = syscon_regmap_lookup_by_phandle(np, "mediatek,sysctl");
	152	if (IS_ERR(drvdata->sysc)) {
	153	drvdata->sysc = syscon_regmap_lookup_by_compatible("mediatek,mt7621-sysc");
	154	if (IS_ERR(drvdata->sysc))
	155	return PTR_ERR(drvdata->sysc);
	156	}
	157
783c7cb4 SP	158	drvdata->base = devm_platform_ioremap_resource(pdev, 0);
	159	if (IS_ERR(drvdata->base))
	160	return PTR_ERR(drvdata->base);
ab3f09fe	161
783c7cb4 SP	162	drvdata->rst = devm_reset_control_get_exclusive(dev, NULL);
	163	if (!IS_ERR(drvdata->rst))
	164	reset_control_deassert(drvdata->rst);
ab3f09fe	165
783c7cb4 SP	166	mt7621_wdt = &drvdata->wdt;
	167	mt7621_wdt->info = &mt7621_wdt_info;
	168	mt7621_wdt->ops = &mt7621_wdt_ops;
	169	mt7621_wdt->min_timeout = 1;
	170	mt7621_wdt->max_timeout = 0xfffful / 1000;
	171	mt7621_wdt->parent = dev;
	172
ff8ec4ac	173	mt7621_wdt->bootstatus = mt7621_wdt_bootcause(drvdata);
783c7cb4 SP	174
	175	watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev);
	176	watchdog_set_nowayout(mt7621_wdt, nowayout);
	177	watchdog_set_drvdata(mt7621_wdt, drvdata);
	178
	179	if (mt7621_wdt_is_running(mt7621_wdt)) {
392d39a8 AD	180	/*
	181	* Make sure to apply timeout from watchdog core, taking
	182	* the prescaler of this driver here into account (the
	183	* boot loader might be using a different prescaler).
	184	*
	185	* To avoid spurious resets because of different scaling,
	186	* we first disable the watchdog, set the new prescaler
	187	* and timeout, and then re-enable the watchdog.
	188	*/
783c7cb4 SP	189	mt7621_wdt_stop(mt7621_wdt);
	190	mt7621_wdt_start(mt7621_wdt);
	191	set_bit(WDOG_HW_RUNNING, &mt7621_wdt->status);
392d39a8	192	}
ab3f09fe	193
783c7cb4 SP	194	err = devm_watchdog_register_device(dev, &drvdata->wdt);
	195	if (err)
	196	return err;
	197
	198	platform_set_drvdata(pdev, drvdata);
	199
	200	return 0;
ab3f09fe JC	201	}
	202
	203	static void mt7621_wdt_shutdown(struct platform_device *pdev)
	204	{
783c7cb4 SP	205	struct mt7621_wdt_data *drvdata = platform_get_drvdata(pdev);
	206
	207	mt7621_wdt_stop(&drvdata->wdt);
ab3f09fe JC	208	}
	209
	210	static const struct of_device_id mt7621_wdt_match[] = {
	211	{ .compatible = "mediatek,mt7621-wdt" },
	212	{},
	213	};
	214	MODULE_DEVICE_TABLE(of, mt7621_wdt_match);
	215
	216	static struct platform_driver mt7621_wdt_driver = {
	217	.probe = mt7621_wdt_probe,
ab3f09fe JC	218	.shutdown = mt7621_wdt_shutdown,
	219	.driver = {
	220	.name = KBUILD_MODNAME,
	221	.of_match_table = mt7621_wdt_match,
	222	},
	223	};
	224
	225	module_platform_driver(mt7621_wdt_driver);
	226
	227	MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
f3519a66	228	MODULE_AUTHOR("John Crispin <john@phrozen.org");
ab3f09fe	229	MODULE_LICENSE("GPL v2");