Commit | Line | Data |
---|---|---|
b9d36b85 RK |
1 | /* |
2 | * Watchdog driver for the mpcore watchdog timer | |
3 | * | |
4 | * (c) Copyright 2004 ARM Limited | |
5 | * | |
6 | * Based on the SoftDog driver: | |
29fa0586 | 7 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>, |
143a2e54 | 8 | * All Rights Reserved. |
b9d36b85 RK |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide | |
16 | * warranty for any of this software. This material is provided | |
17 | * "AS-IS" and at no charge. | |
18 | * | |
19 | * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> | |
20 | * | |
21 | */ | |
27c766aa JP |
22 | |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
24 | ||
b9d36b85 RK |
25 | #include <linux/module.h> |
26 | #include <linux/moduleparam.h> | |
b9d36b85 RK |
27 | #include <linux/types.h> |
28 | #include <linux/miscdevice.h> | |
29 | #include <linux/watchdog.h> | |
30 | #include <linux/fs.h> | |
31 | #include <linux/reboot.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/interrupt.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
83ab1a53 | 35 | #include <linux/uaccess.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
98af0570 | 37 | #include <linux/io.h> |
ad4162f3 | 38 | |
98af0570 | 39 | #include <asm/smp_twd.h> |
b9d36b85 RK |
40 | |
41 | struct mpcore_wdt { | |
42 | unsigned long timer_alive; | |
43 | struct device *dev; | |
44 | void __iomem *base; | |
45 | int irq; | |
46 | unsigned int perturb; | |
47 | char expect_close; | |
48 | }; | |
49 | ||
50 | static struct platform_device *mpcore_wdt_dev; | |
98af0570 | 51 | static DEFINE_SPINLOCK(wdt_lock); |
b9d36b85 RK |
52 | |
53 | #define TIMER_MARGIN 60 | |
54 | static int mpcore_margin = TIMER_MARGIN; | |
55 | module_param(mpcore_margin, int, 0); | |
83ab1a53 AC |
56 | MODULE_PARM_DESC(mpcore_margin, |
57 | "MPcore timer margin in seconds. (0 < mpcore_margin < 65536, default=" | |
58 | __MODULE_STRING(TIMER_MARGIN) ")"); | |
b9d36b85 | 59 | |
86a1e189 WVS |
60 | static bool nowayout = WATCHDOG_NOWAYOUT; |
61 | module_param(nowayout, bool, 0); | |
83ab1a53 AC |
62 | MODULE_PARM_DESC(nowayout, |
63 | "Watchdog cannot be stopped once started (default=" | |
64 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
b9d36b85 RK |
65 | |
66 | #define ONLY_TESTING 0 | |
67 | static int mpcore_noboot = ONLY_TESTING; | |
68 | module_param(mpcore_noboot, int, 0); | |
a77dba7e WVS |
69 | MODULE_PARM_DESC(mpcore_noboot, "MPcore watchdog action, " |
70 | "set to 1 to ignore reboots, 0 to reboot (default=" | |
71 | __MODULE_STRING(ONLY_TESTING) ")"); | |
b9d36b85 RK |
72 | |
73 | /* | |
74 | * This is the interrupt handler. Note that we only use this | |
75 | * in testing mode, so don't actually do a reboot here. | |
76 | */ | |
7d12e780 | 77 | static irqreturn_t mpcore_wdt_fire(int irq, void *arg) |
b9d36b85 RK |
78 | { |
79 | struct mpcore_wdt *wdt = arg; | |
80 | ||
81 | /* Check it really was our interrupt */ | |
82 | if (readl(wdt->base + TWD_WDOG_INTSTAT)) { | |
83ab1a53 AC |
83 | dev_printk(KERN_CRIT, wdt->dev, |
84 | "Triggered - Reboot ignored.\n"); | |
b9d36b85 RK |
85 | /* Clear the interrupt on the watchdog */ |
86 | writel(1, wdt->base + TWD_WDOG_INTSTAT); | |
b9d36b85 RK |
87 | return IRQ_HANDLED; |
88 | } | |
b9d36b85 RK |
89 | return IRQ_NONE; |
90 | } | |
91 | ||
92 | /* | |
93 | * mpcore_wdt_keepalive - reload the timer | |
94 | * | |
95 | * Note that the spec says a DIFFERENT value must be written to the reload | |
96 | * register each time. The "perturb" variable deals with this by adding 1 | |
97 | * to the count every other time the function is called. | |
98 | */ | |
99 | static void mpcore_wdt_keepalive(struct mpcore_wdt *wdt) | |
100 | { | |
98af0570 | 101 | unsigned long count; |
b9d36b85 | 102 | |
98af0570 | 103 | spin_lock(&wdt_lock); |
b9d36b85 | 104 | /* Assume prescale is set to 256 */ |
98af0570 SK |
105 | count = __raw_readl(wdt->base + TWD_WDOG_COUNTER); |
106 | count = (0xFFFFFFFFU - count) * (HZ / 5); | |
107 | count = (count / 256) * mpcore_margin; | |
b9d36b85 RK |
108 | |
109 | /* Reload the counter */ | |
110 | writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD); | |
b9d36b85 | 111 | wdt->perturb = wdt->perturb ? 0 : 1; |
83ab1a53 | 112 | spin_unlock(&wdt_lock); |
b9d36b85 RK |
113 | } |
114 | ||
115 | static void mpcore_wdt_stop(struct mpcore_wdt *wdt) | |
116 | { | |
83ab1a53 | 117 | spin_lock(&wdt_lock); |
b9d36b85 RK |
118 | writel(0x12345678, wdt->base + TWD_WDOG_DISABLE); |
119 | writel(0x87654321, wdt->base + TWD_WDOG_DISABLE); | |
120 | writel(0x0, wdt->base + TWD_WDOG_CONTROL); | |
83ab1a53 | 121 | spin_unlock(&wdt_lock); |
b9d36b85 RK |
122 | } |
123 | ||
124 | static void mpcore_wdt_start(struct mpcore_wdt *wdt) | |
125 | { | |
126 | dev_printk(KERN_INFO, wdt->dev, "enabling watchdog.\n"); | |
127 | ||
128 | /* This loads the count register but does NOT start the count yet */ | |
129 | mpcore_wdt_keepalive(wdt); | |
130 | ||
131 | if (mpcore_noboot) { | |
132 | /* Enable watchdog - prescale=256, watchdog mode=0, enable=1 */ | |
133 | writel(0x0000FF01, wdt->base + TWD_WDOG_CONTROL); | |
134 | } else { | |
135 | /* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */ | |
136 | writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL); | |
137 | } | |
138 | } | |
139 | ||
140 | static int mpcore_wdt_set_heartbeat(int t) | |
141 | { | |
142 | if (t < 0x0001 || t > 0xFFFF) | |
143 | return -EINVAL; | |
144 | ||
145 | mpcore_margin = t; | |
146 | return 0; | |
147 | } | |
148 | ||
149 | /* | |
150 | * /dev/watchdog handling | |
151 | */ | |
152 | static int mpcore_wdt_open(struct inode *inode, struct file *file) | |
153 | { | |
3ae5eaec | 154 | struct mpcore_wdt *wdt = platform_get_drvdata(mpcore_wdt_dev); |
b9d36b85 RK |
155 | |
156 | if (test_and_set_bit(0, &wdt->timer_alive)) | |
157 | return -EBUSY; | |
158 | ||
159 | if (nowayout) | |
160 | __module_get(THIS_MODULE); | |
161 | ||
162 | file->private_data = wdt; | |
163 | ||
164 | /* | |
165 | * Activate timer | |
166 | */ | |
167 | mpcore_wdt_start(wdt); | |
168 | ||
169 | return nonseekable_open(inode, file); | |
170 | } | |
171 | ||
172 | static int mpcore_wdt_release(struct inode *inode, struct file *file) | |
173 | { | |
174 | struct mpcore_wdt *wdt = file->private_data; | |
175 | ||
176 | /* | |
177 | * Shut off the timer. | |
5f3b2756 | 178 | * Lock it in if it's a module and we set nowayout |
b9d36b85 | 179 | */ |
83ab1a53 | 180 | if (wdt->expect_close == 42) |
b9d36b85 | 181 | mpcore_wdt_stop(wdt); |
83ab1a53 AC |
182 | else { |
183 | dev_printk(KERN_CRIT, wdt->dev, | |
184 | "unexpected close, not stopping watchdog!\n"); | |
b9d36b85 RK |
185 | mpcore_wdt_keepalive(wdt); |
186 | } | |
187 | clear_bit(0, &wdt->timer_alive); | |
188 | wdt->expect_close = 0; | |
189 | return 0; | |
190 | } | |
191 | ||
83ab1a53 AC |
192 | static ssize_t mpcore_wdt_write(struct file *file, const char *data, |
193 | size_t len, loff_t *ppos) | |
b9d36b85 RK |
194 | { |
195 | struct mpcore_wdt *wdt = file->private_data; | |
196 | ||
b9d36b85 RK |
197 | /* |
198 | * Refresh the timer. | |
199 | */ | |
200 | if (len) { | |
201 | if (!nowayout) { | |
202 | size_t i; | |
203 | ||
204 | /* In case it was set long ago */ | |
205 | wdt->expect_close = 0; | |
206 | ||
207 | for (i = 0; i != len; i++) { | |
208 | char c; | |
209 | ||
210 | if (get_user(c, data + i)) | |
211 | return -EFAULT; | |
212 | if (c == 'V') | |
213 | wdt->expect_close = 42; | |
214 | } | |
215 | } | |
216 | mpcore_wdt_keepalive(wdt); | |
217 | } | |
218 | return len; | |
219 | } | |
220 | ||
42747d71 | 221 | static const struct watchdog_info ident = { |
b9d36b85 RK |
222 | .options = WDIOF_SETTIMEOUT | |
223 | WDIOF_KEEPALIVEPING | | |
224 | WDIOF_MAGICCLOSE, | |
225 | .identity = "MPcore Watchdog", | |
226 | }; | |
227 | ||
83ab1a53 AC |
228 | static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd, |
229 | unsigned long arg) | |
b9d36b85 RK |
230 | { |
231 | struct mpcore_wdt *wdt = file->private_data; | |
232 | int ret; | |
233 | union { | |
234 | struct watchdog_info ident; | |
235 | int i; | |
236 | } uarg; | |
237 | ||
238 | if (_IOC_DIR(cmd) && _IOC_SIZE(cmd) > sizeof(uarg)) | |
795b89d2 | 239 | return -ENOTTY; |
b9d36b85 RK |
240 | |
241 | if (_IOC_DIR(cmd) & _IOC_WRITE) { | |
242 | ret = copy_from_user(&uarg, (void __user *)arg, _IOC_SIZE(cmd)); | |
243 | if (ret) | |
244 | return -EFAULT; | |
245 | } | |
246 | ||
247 | switch (cmd) { | |
248 | case WDIOC_GETSUPPORT: | |
249 | uarg.ident = ident; | |
250 | ret = 0; | |
251 | break; | |
252 | ||
0c06090c WVS |
253 | case WDIOC_GETSTATUS: |
254 | case WDIOC_GETBOOTSTATUS: | |
255 | uarg.i = 0; | |
256 | ret = 0; | |
257 | break; | |
258 | ||
b9d36b85 RK |
259 | case WDIOC_SETOPTIONS: |
260 | ret = -EINVAL; | |
261 | if (uarg.i & WDIOS_DISABLECARD) { | |
262 | mpcore_wdt_stop(wdt); | |
263 | ret = 0; | |
264 | } | |
265 | if (uarg.i & WDIOS_ENABLECARD) { | |
266 | mpcore_wdt_start(wdt); | |
267 | ret = 0; | |
268 | } | |
269 | break; | |
270 | ||
b9d36b85 RK |
271 | case WDIOC_KEEPALIVE: |
272 | mpcore_wdt_keepalive(wdt); | |
273 | ret = 0; | |
274 | break; | |
275 | ||
276 | case WDIOC_SETTIMEOUT: | |
277 | ret = mpcore_wdt_set_heartbeat(uarg.i); | |
278 | if (ret) | |
279 | break; | |
280 | ||
281 | mpcore_wdt_keepalive(wdt); | |
282 | /* Fall */ | |
283 | case WDIOC_GETTIMEOUT: | |
284 | uarg.i = mpcore_margin; | |
285 | ret = 0; | |
286 | break; | |
287 | ||
288 | default: | |
795b89d2 | 289 | return -ENOTTY; |
b9d36b85 RK |
290 | } |
291 | ||
292 | if (ret == 0 && _IOC_DIR(cmd) & _IOC_READ) { | |
293 | ret = copy_to_user((void __user *)arg, &uarg, _IOC_SIZE(cmd)); | |
294 | if (ret) | |
295 | ret = -EFAULT; | |
296 | } | |
297 | return ret; | |
298 | } | |
299 | ||
300 | /* | |
301 | * System shutdown handler. Turn off the watchdog if we're | |
302 | * restarting or halting the system. | |
303 | */ | |
3ae5eaec | 304 | static void mpcore_wdt_shutdown(struct platform_device *dev) |
b9d36b85 | 305 | { |
3ae5eaec | 306 | struct mpcore_wdt *wdt = platform_get_drvdata(dev); |
b9d36b85 RK |
307 | |
308 | if (system_state == SYSTEM_RESTART || system_state == SYSTEM_HALT) | |
309 | mpcore_wdt_stop(wdt); | |
310 | } | |
311 | ||
312 | /* | |
313 | * Kernel Interfaces | |
314 | */ | |
62322d25 | 315 | static const struct file_operations mpcore_wdt_fops = { |
b9d36b85 RK |
316 | .owner = THIS_MODULE, |
317 | .llseek = no_llseek, | |
318 | .write = mpcore_wdt_write, | |
83ab1a53 | 319 | .unlocked_ioctl = mpcore_wdt_ioctl, |
b9d36b85 RK |
320 | .open = mpcore_wdt_open, |
321 | .release = mpcore_wdt_release, | |
322 | }; | |
323 | ||
324 | static struct miscdevice mpcore_wdt_miscdev = { | |
325 | .minor = WATCHDOG_MINOR, | |
326 | .name = "watchdog", | |
327 | .fops = &mpcore_wdt_fops, | |
328 | }; | |
329 | ||
3ae5eaec | 330 | static int __devinit mpcore_wdt_probe(struct platform_device *dev) |
b9d36b85 | 331 | { |
b9d36b85 RK |
332 | struct mpcore_wdt *wdt; |
333 | struct resource *res; | |
334 | int ret; | |
335 | ||
336 | /* We only accept one device, and it must have an id of -1 */ | |
337 | if (dev->id != -1) | |
338 | return -ENODEV; | |
339 | ||
340 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
341 | if (!res) { | |
342 | ret = -ENODEV; | |
343 | goto err_out; | |
344 | } | |
345 | ||
dd00cc48 | 346 | wdt = kzalloc(sizeof(struct mpcore_wdt), GFP_KERNEL); |
b9d36b85 RK |
347 | if (!wdt) { |
348 | ret = -ENOMEM; | |
349 | goto err_out; | |
350 | } | |
b9d36b85 RK |
351 | |
352 | wdt->dev = &dev->dev; | |
353 | wdt->irq = platform_get_irq(dev, 0); | |
48944738 DV |
354 | if (wdt->irq < 0) { |
355 | ret = -ENXIO; | |
356 | goto err_free; | |
357 | } | |
b782a563 | 358 | wdt->base = ioremap(res->start, resource_size(res)); |
b9d36b85 RK |
359 | if (!wdt->base) { |
360 | ret = -ENOMEM; | |
361 | goto err_free; | |
362 | } | |
363 | ||
e0b79e0b | 364 | mpcore_wdt_miscdev.parent = &dev->dev; |
b9d36b85 RK |
365 | ret = misc_register(&mpcore_wdt_miscdev); |
366 | if (ret) { | |
98af0570 | 367 | dev_printk(KERN_ERR, wdt->dev, |
83ab1a53 AC |
368 | "cannot register miscdev on minor=%d (err=%d)\n", |
369 | WATCHDOG_MINOR, ret); | |
b9d36b85 RK |
370 | goto err_misc; |
371 | } | |
372 | ||
86b59128 | 373 | ret = request_irq(wdt->irq, mpcore_wdt_fire, 0, "mpcore_wdt", wdt); |
b9d36b85 | 374 | if (ret) { |
98af0570 | 375 | dev_printk(KERN_ERR, wdt->dev, |
83ab1a53 | 376 | "cannot register IRQ%d for watchdog\n", wdt->irq); |
b9d36b85 RK |
377 | goto err_irq; |
378 | } | |
379 | ||
380 | mpcore_wdt_stop(wdt); | |
98af0570 | 381 | platform_set_drvdata(dev, wdt); |
b9d36b85 RK |
382 | mpcore_wdt_dev = dev; |
383 | ||
384 | return 0; | |
385 | ||
7944d3a5 | 386 | err_irq: |
b9d36b85 | 387 | misc_deregister(&mpcore_wdt_miscdev); |
7944d3a5 | 388 | err_misc: |
b9d36b85 | 389 | iounmap(wdt->base); |
7944d3a5 | 390 | err_free: |
b9d36b85 | 391 | kfree(wdt); |
7944d3a5 | 392 | err_out: |
b9d36b85 RK |
393 | return ret; |
394 | } | |
395 | ||
3ae5eaec | 396 | static int __devexit mpcore_wdt_remove(struct platform_device *dev) |
b9d36b85 | 397 | { |
3ae5eaec | 398 | struct mpcore_wdt *wdt = platform_get_drvdata(dev); |
b9d36b85 | 399 | |
3ae5eaec | 400 | platform_set_drvdata(dev, NULL); |
b9d36b85 RK |
401 | |
402 | misc_deregister(&mpcore_wdt_miscdev); | |
403 | ||
404 | mpcore_wdt_dev = NULL; | |
405 | ||
406 | free_irq(wdt->irq, wdt); | |
407 | iounmap(wdt->base); | |
408 | kfree(wdt); | |
409 | return 0; | |
410 | } | |
411 | ||
641e4f44 PF |
412 | #ifdef CONFIG_PM |
413 | static int mpcore_wdt_suspend(struct platform_device *dev, pm_message_t msg) | |
414 | { | |
415 | struct mpcore_wdt *wdt = platform_get_drvdata(dev); | |
416 | mpcore_wdt_stop(wdt); /* Turn the WDT off */ | |
417 | return 0; | |
418 | } | |
419 | ||
420 | static int mpcore_wdt_resume(struct platform_device *dev) | |
421 | { | |
422 | struct mpcore_wdt *wdt = platform_get_drvdata(dev); | |
423 | /* re-activate timer */ | |
424 | if (test_bit(0, &wdt->timer_alive)) | |
425 | mpcore_wdt_start(wdt); | |
426 | return 0; | |
427 | } | |
428 | #else | |
429 | #define mpcore_wdt_suspend NULL | |
430 | #define mpcore_wdt_resume NULL | |
431 | #endif | |
432 | ||
f37d193c KS |
433 | /* work with hotplug and coldplug */ |
434 | MODULE_ALIAS("platform:mpcore_wdt"); | |
435 | ||
3ae5eaec | 436 | static struct platform_driver mpcore_wdt_driver = { |
b9d36b85 RK |
437 | .probe = mpcore_wdt_probe, |
438 | .remove = __devexit_p(mpcore_wdt_remove), | |
641e4f44 PF |
439 | .suspend = mpcore_wdt_suspend, |
440 | .resume = mpcore_wdt_resume, | |
b9d36b85 | 441 | .shutdown = mpcore_wdt_shutdown, |
3ae5eaec RK |
442 | .driver = { |
443 | .owner = THIS_MODULE, | |
444 | .name = "mpcore_wdt", | |
445 | }, | |
b9d36b85 RK |
446 | }; |
447 | ||
b9d36b85 RK |
448 | static int __init mpcore_wdt_init(void) |
449 | { | |
450 | /* | |
451 | * Check that the margin value is within it's range; | |
452 | * if not reset to the default | |
453 | */ | |
454 | if (mpcore_wdt_set_heartbeat(mpcore_margin)) { | |
455 | mpcore_wdt_set_heartbeat(TIMER_MARGIN); | |
27c766aa | 456 | pr_info("mpcore_margin value must be 0 < mpcore_margin < 65536, using %d\n", |
b9d36b85 RK |
457 | TIMER_MARGIN); |
458 | } | |
459 | ||
27c766aa JP |
460 | pr_info("MPcore Watchdog Timer: 0.1. mpcore_noboot=%d mpcore_margin=%d sec (nowayout= %d)\n", |
461 | mpcore_noboot, mpcore_margin, nowayout); | |
b9d36b85 | 462 | |
3ae5eaec | 463 | return platform_driver_register(&mpcore_wdt_driver); |
b9d36b85 RK |
464 | } |
465 | ||
466 | static void __exit mpcore_wdt_exit(void) | |
467 | { | |
3ae5eaec | 468 | platform_driver_unregister(&mpcore_wdt_driver); |
b9d36b85 RK |
469 | } |
470 | ||
471 | module_init(mpcore_wdt_init); | |
472 | module_exit(mpcore_wdt_exit); | |
473 | ||
474 | MODULE_AUTHOR("ARM Limited"); | |
475 | MODULE_DESCRIPTION("MPcore Watchdog Device Driver"); | |
476 | MODULE_LICENSE("GPL"); | |
477 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |