Commit | Line | Data |
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fabbfb9e | 1 | /* |
0d7b1014 | 2 | * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface |
fabbfb9e KG |
3 | * |
4 | * Authors: Dave Updegraff <dave@cray.org> | |
5f3b2756 WVS |
5 | * Kumar Gala <galak@kernel.crashing.org> |
6 | * Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org> | |
7 | * ..and from sc520_wdt | |
500c919e AV |
8 | * Copyright (c) 2008 MontaVista Software, Inc. |
9 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
fabbfb9e KG |
10 | * |
11 | * Note: it appears that you can only actually ENABLE or DISABLE the thing | |
12 | * once after POR. Once enabled, you cannot disable, and vice versa. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify it | |
15 | * under the terms of the GNU General Public License as published by the | |
16 | * Free Software Foundation; either version 2 of the License, or (at your | |
17 | * option) any later version. | |
18 | */ | |
19 | ||
27c766aa JP |
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
21 | ||
fabbfb9e KG |
22 | #include <linux/fs.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
500c919e | 25 | #include <linux/timer.h> |
5af50730 | 26 | #include <linux/of_address.h> |
ef8ab12e | 27 | #include <linux/of_platform.h> |
fabbfb9e KG |
28 | #include <linux/module.h> |
29 | #include <linux/watchdog.h> | |
f26ef3dc AC |
30 | #include <linux/io.h> |
31 | #include <linux/uaccess.h> | |
ef8ab12e | 32 | #include <sysdev/fsl_soc.h> |
fabbfb9e | 33 | |
59ca1b0d | 34 | struct mpc8xxx_wdt { |
fabbfb9e KG |
35 | __be32 res0; |
36 | __be32 swcrr; /* System watchdog control register */ | |
37 | #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ | |
38 | #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ | |
39 | #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/ | |
40 | #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ | |
41 | __be32 swcnr; /* System watchdog count register */ | |
42 | u8 res1[2]; | |
43 | __be16 swsrr; /* System watchdog service register */ | |
44 | u8 res2[0xF0]; | |
45 | }; | |
46 | ||
59ca1b0d | 47 | struct mpc8xxx_wdt_type { |
500c919e AV |
48 | int prescaler; |
49 | bool hw_enabled; | |
50 | }; | |
51 | ||
7997ebad UKK |
52 | struct mpc8xxx_wdt_ddata { |
53 | struct mpc8xxx_wdt __iomem *base; | |
54 | struct watchdog_device wdd; | |
55 | struct timer_list timer; | |
56 | spinlock_t lock; | |
57 | }; | |
fabbfb9e KG |
58 | |
59 | static u16 timeout = 0xffff; | |
60 | module_param(timeout, ushort, 0); | |
f26ef3dc | 61 | MODULE_PARM_DESC(timeout, |
76550d32 | 62 | "Watchdog timeout in ticks. (0<timeout<65536, default=65535)"); |
fabbfb9e | 63 | |
90ab5ee9 | 64 | static bool reset = 1; |
fabbfb9e | 65 | module_param(reset, bool, 0); |
f26ef3dc AC |
66 | MODULE_PARM_DESC(reset, |
67 | "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset"); | |
fabbfb9e | 68 | |
86a1e189 WVS |
69 | static bool nowayout = WATCHDOG_NOWAYOUT; |
70 | module_param(nowayout, bool, 0); | |
500c919e AV |
71 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " |
72 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
73 | ||
7997ebad | 74 | static void mpc8xxx_wdt_keepalive(struct mpc8xxx_wdt_ddata *ddata) |
fabbfb9e KG |
75 | { |
76 | /* Ping the WDT */ | |
7997ebad UKK |
77 | spin_lock(&ddata->lock); |
78 | out_be16(&ddata->base->swsrr, 0x556c); | |
79 | out_be16(&ddata->base->swsrr, 0xaa39); | |
80 | spin_unlock(&ddata->lock); | |
fabbfb9e KG |
81 | } |
82 | ||
59ca1b0d | 83 | static void mpc8xxx_wdt_timer_ping(unsigned long arg) |
500c919e | 84 | { |
7997ebad | 85 | struct mpc8xxx_wdt_ddata *ddata = (void *)arg; |
d5cfaf0a | 86 | |
7997ebad | 87 | mpc8xxx_wdt_keepalive(ddata); |
500c919e | 88 | /* We're pinging it twice faster than needed, just to be sure. */ |
7997ebad | 89 | mod_timer(&ddata->timer, jiffies + HZ * ddata->wdd.timeout / 2); |
500c919e AV |
90 | } |
91 | ||
d5cfaf0a | 92 | static int mpc8xxx_wdt_start(struct watchdog_device *w) |
fabbfb9e | 93 | { |
7997ebad UKK |
94 | struct mpc8xxx_wdt_ddata *ddata = |
95 | container_of(w, struct mpc8xxx_wdt_ddata, wdd); | |
96 | ||
a57e06f7 | 97 | u32 tmp = SWCRR_SWEN | SWCRR_SWPR; |
fabbfb9e KG |
98 | |
99 | /* Good, fire up the show */ | |
fabbfb9e KG |
100 | if (reset) |
101 | tmp |= SWCRR_SWRI; | |
102 | ||
103 | tmp |= timeout << 16; | |
104 | ||
7997ebad | 105 | out_be32(&ddata->base->swcrr, tmp); |
fabbfb9e | 106 | |
7997ebad | 107 | del_timer_sync(&ddata->timer); |
500c919e | 108 | |
d5cfaf0a | 109 | return 0; |
fabbfb9e KG |
110 | } |
111 | ||
d5cfaf0a | 112 | static int mpc8xxx_wdt_ping(struct watchdog_device *w) |
fabbfb9e | 113 | { |
7997ebad UKK |
114 | struct mpc8xxx_wdt_ddata *ddata = |
115 | container_of(w, struct mpc8xxx_wdt_ddata, wdd); | |
116 | ||
117 | mpc8xxx_wdt_keepalive(ddata); | |
fabbfb9e KG |
118 | return 0; |
119 | } | |
120 | ||
d5cfaf0a | 121 | static int mpc8xxx_wdt_stop(struct watchdog_device *w) |
fabbfb9e | 122 | { |
7997ebad UKK |
123 | struct mpc8xxx_wdt_ddata *ddata = |
124 | container_of(w, struct mpc8xxx_wdt_ddata, wdd); | |
125 | ||
126 | mod_timer(&ddata->timer, jiffies); | |
d5cfaf0a | 127 | return 0; |
fabbfb9e KG |
128 | } |
129 | ||
d5cfaf0a CL |
130 | static struct watchdog_info mpc8xxx_wdt_info = { |
131 | .options = WDIOF_KEEPALIVEPING, | |
132 | .firmware_version = 1, | |
133 | .identity = "MPC8xxx", | |
fabbfb9e KG |
134 | }; |
135 | ||
d5cfaf0a CL |
136 | static struct watchdog_ops mpc8xxx_wdt_ops = { |
137 | .owner = THIS_MODULE, | |
138 | .start = mpc8xxx_wdt_start, | |
139 | .ping = mpc8xxx_wdt_ping, | |
140 | .stop = mpc8xxx_wdt_stop, | |
141 | }; | |
142 | ||
2d991a16 | 143 | static int mpc8xxx_wdt_probe(struct platform_device *ofdev) |
fabbfb9e | 144 | { |
fabbfb9e | 145 | int ret; |
de5f7122 | 146 | struct resource *res; |
639397e4 | 147 | const struct mpc8xxx_wdt_type *wdt_type; |
7997ebad | 148 | struct mpc8xxx_wdt_ddata *ddata; |
ef8ab12e | 149 | u32 freq = fsl_get_sys_freq(); |
500c919e | 150 | bool enabled; |
d5cfaf0a | 151 | unsigned int timeout_sec; |
fabbfb9e | 152 | |
f0ded83b UKK |
153 | wdt_type = of_device_get_match_data(&ofdev->dev); |
154 | if (!wdt_type) | |
1c48a5c9 | 155 | return -EINVAL; |
1c48a5c9 | 156 | |
ef8ab12e AV |
157 | if (!freq || freq == -1) |
158 | return -EINVAL; | |
fabbfb9e | 159 | |
7997ebad UKK |
160 | ddata = devm_kzalloc(&ofdev->dev, sizeof(*ddata), GFP_KERNEL); |
161 | if (!ddata) | |
162 | return -ENOMEM; | |
163 | ||
de5f7122 | 164 | res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); |
7997ebad UKK |
165 | ddata->base = devm_ioremap_resource(&ofdev->dev, res); |
166 | if (IS_ERR(ddata->base)) | |
167 | return PTR_ERR(ddata->base); | |
fabbfb9e | 168 | |
7997ebad | 169 | enabled = in_be32(&ddata->base->swcrr) & SWCRR_SWEN; |
500c919e | 170 | if (!enabled && wdt_type->hw_enabled) { |
27c766aa | 171 | pr_info("could not be enabled in software\n"); |
72cd501e | 172 | return -ENODEV; |
500c919e AV |
173 | } |
174 | ||
7997ebad UKK |
175 | spin_lock_init(&ddata->lock); |
176 | setup_timer(&ddata->timer, mpc8xxx_wdt_timer_ping, | |
177 | (unsigned long)ddata); | |
178 | ||
179 | ddata->wdd.info = &mpc8xxx_wdt_info, | |
180 | ddata->wdd.ops = &mpc8xxx_wdt_ops, | |
181 | ||
fabbfb9e | 182 | /* Calculate the timeout in seconds */ |
a57e06f7 | 183 | timeout_sec = (timeout * wdt_type->prescaler) / freq; |
fabbfb9e | 184 | |
7997ebad | 185 | ddata->wdd.timeout = timeout_sec; |
50ffb53e | 186 | |
7997ebad | 187 | watchdog_set_nowayout(&ddata->wdd, nowayout); |
50ffb53e | 188 | |
7997ebad | 189 | ret = watchdog_register_device(&ddata->wdd); |
50ffb53e UKK |
190 | if (ret) { |
191 | pr_err("cannot register watchdog device (err=%d)\n", ret); | |
de5f7122 | 192 | return ret; |
50ffb53e | 193 | } |
593fc178 | 194 | |
27c766aa JP |
195 | pr_info("WDT driver for MPC8xxx initialized. mode:%s timeout=%d (%d seconds)\n", |
196 | reset ? "reset" : "interrupt", timeout, timeout_sec); | |
500c919e AV |
197 | |
198 | /* | |
199 | * If the watchdog was previously enabled or we're running on | |
59ca1b0d | 200 | * MPC8xxx, we should ping the wdt from the kernel until the |
500c919e AV |
201 | * userspace handles it. |
202 | */ | |
203 | if (enabled) | |
7997ebad UKK |
204 | mod_timer(&ddata->timer, jiffies); |
205 | ||
206 | platform_set_drvdata(ofdev, ddata); | |
fabbfb9e | 207 | return 0; |
fabbfb9e KG |
208 | } |
209 | ||
4b12b896 | 210 | static int mpc8xxx_wdt_remove(struct platform_device *ofdev) |
fabbfb9e | 211 | { |
7997ebad UKK |
212 | struct mpc8xxx_wdt_ddata *ddata = platform_get_drvdata(ofdev); |
213 | ||
d5cfaf0a CL |
214 | pr_crit("Watchdog removed, expect the %s soon!\n", |
215 | reset ? "reset" : "machine check exception"); | |
7997ebad UKK |
216 | del_timer_sync(&ddata->timer); |
217 | watchdog_unregister_device(&ddata->wdd); | |
fabbfb9e KG |
218 | |
219 | return 0; | |
220 | } | |
221 | ||
59ca1b0d | 222 | static const struct of_device_id mpc8xxx_wdt_match[] = { |
ef8ab12e AV |
223 | { |
224 | .compatible = "mpc83xx_wdt", | |
59ca1b0d | 225 | .data = &(struct mpc8xxx_wdt_type) { |
500c919e AV |
226 | .prescaler = 0x10000, |
227 | }, | |
228 | }, | |
229 | { | |
230 | .compatible = "fsl,mpc8610-wdt", | |
59ca1b0d | 231 | .data = &(struct mpc8xxx_wdt_type) { |
500c919e AV |
232 | .prescaler = 0x10000, |
233 | .hw_enabled = true, | |
234 | }, | |
ef8ab12e | 235 | }, |
0d7b1014 AV |
236 | { |
237 | .compatible = "fsl,mpc823-wdt", | |
238 | .data = &(struct mpc8xxx_wdt_type) { | |
239 | .prescaler = 0x800, | |
4af897fa | 240 | .hw_enabled = true, |
0d7b1014 AV |
241 | }, |
242 | }, | |
ef8ab12e AV |
243 | {}, |
244 | }; | |
59ca1b0d | 245 | MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match); |
ef8ab12e | 246 | |
1c48a5c9 | 247 | static struct platform_driver mpc8xxx_wdt_driver = { |
59ca1b0d | 248 | .probe = mpc8xxx_wdt_probe, |
82268714 | 249 | .remove = mpc8xxx_wdt_remove, |
4018294b GL |
250 | .driver = { |
251 | .name = "mpc8xxx_wdt", | |
4018294b | 252 | .of_match_table = mpc8xxx_wdt_match, |
fabbfb9e KG |
253 | }, |
254 | }; | |
255 | ||
59ca1b0d | 256 | static int __init mpc8xxx_wdt_init(void) |
fabbfb9e | 257 | { |
1c48a5c9 | 258 | return platform_driver_register(&mpc8xxx_wdt_driver); |
fabbfb9e | 259 | } |
0d7b1014 | 260 | arch_initcall(mpc8xxx_wdt_init); |
fabbfb9e | 261 | |
59ca1b0d | 262 | static void __exit mpc8xxx_wdt_exit(void) |
fabbfb9e | 263 | { |
1c48a5c9 | 264 | platform_driver_unregister(&mpc8xxx_wdt_driver); |
fabbfb9e | 265 | } |
59ca1b0d | 266 | module_exit(mpc8xxx_wdt_exit); |
fabbfb9e KG |
267 | |
268 | MODULE_AUTHOR("Dave Updegraff, Kumar Gala"); | |
0d7b1014 AV |
269 | MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx " |
270 | "uProcessors"); | |
fabbfb9e | 271 | MODULE_LICENSE("GPL"); |