[linux-2.6-block.git] / drivers / watchdog / max63xx_wdt.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * drivers/char/watchdog/max63xx_wdt.c
 *
 * Driver for max63{69,70,71,72,73,74} watchdog timers
 *
 * Copyright (C) 2009 Marc Zyngier <maz@misterjones.org>
 *
 * This driver assumes the watchdog pins are memory mapped (as it is
 * the case for the Arcom Zeus). Should it be connected over GPIOs or
 * another interface, some abstraction will have to be introduced.
 */

#include <linux/err.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mod_devicetable.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/bitops.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/property.h>

#define DEFAULT_HEARTBEAT 60
#define MAX_HEARTBEAT     60

static unsigned int heartbeat = DEFAULT_HEARTBEAT;
static bool nowayout  = WATCHDOG_NOWAYOUT;

/*
 * Memory mapping: a single byte, 3 first lower bits to select bit 3
 * to ping the watchdog.
 */
#define MAX6369_WDSET	(7 << 0)
#define MAX6369_WDI	(1 << 3)

#define MAX6369_WDSET_DISABLED	3

static int nodelay;

struct max63xx_wdt {
	struct watchdog_device wdd;
	const struct max63xx_timeout *timeout;

	/* memory mapping */
	void __iomem *base;
	spinlock_t lock;

	/* WDI and WSET bits write access routines */
	void (*ping)(struct max63xx_wdt *wdt);
	void (*set)(struct max63xx_wdt *wdt, u8 set);
};

/*
 * The timeout values used are actually the absolute minimum the chip
 * offers. Typical values on my board are slightly over twice as long
 * (10s setting ends up with a 25s timeout), and can be up to 3 times
 * the nominal setting (according to the datasheet). So please take
 * these values with a grain of salt. Same goes for the initial delay
 * "feature". Only max6373/74 have a few settings without this initial
 * delay (selected with the "nodelay" parameter).
 *
 * I also decided to remove from the tables any timeout smaller than a
 * second, as it looked completly overkill...
 */

/* Timeouts in second */
struct max63xx_timeout {
	const u8 wdset;
	const u8 tdelay;
	const u8 twd;
};

static const struct max63xx_timeout max6369_table[] = {
	{ 5,  1,  1 },
	{ 6, 10, 10 },
	{ 7, 60, 60 },
	{ },
};

static const struct max63xx_timeout max6371_table[] = {
	{ 6, 60,  3 },
	{ 7, 60, 60 },
	{ },
};

static const struct max63xx_timeout max6373_table[] = {
	{ 2, 60,  1 },
	{ 5,  0,  1 },
	{ 1,  3,  3 },
	{ 7, 60, 10 },
	{ 6,  0, 10 },
	{ },
};

static const struct max63xx_timeout *
max63xx_select_timeout(const struct max63xx_timeout *table, int value)
{
	while (table->twd) {
		if (value <= table->twd) {
			if (nodelay && table->tdelay == 0)
				return table;

			if (!nodelay)
				return table;
		}

		table++;
	}

	return NULL;
}

static int max63xx_wdt_ping(struct watchdog_device *wdd)
{
	struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd);

	wdt->ping(wdt);
	return 0;
}

static int max63xx_wdt_start(struct watchdog_device *wdd)
{
	struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd);

	wdt->set(wdt, wdt->timeout->wdset);

	/* check for a edge triggered startup */
	if (wdt->timeout->tdelay == 0)
		wdt->ping(wdt);
	return 0;
}

static int max63xx_wdt_stop(struct watchdog_device *wdd)
{
	struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd);

	wdt->set(wdt, MAX6369_WDSET_DISABLED);
	return 0;
}

static const struct watchdog_ops max63xx_wdt_ops = {
	.owner = THIS_MODULE,
	.start = max63xx_wdt_start,
	.stop = max63xx_wdt_stop,
	.ping = max63xx_wdt_ping,
};

static const struct watchdog_info max63xx_wdt_info = {
	.options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
	.identity = "max63xx Watchdog",
};

static void max63xx_mmap_ping(struct max63xx_wdt *wdt)
{
	u8 val;

	spin_lock(&wdt->lock);

	val = __raw_readb(wdt->base);

	__raw_writeb(val | MAX6369_WDI, wdt->base);
	__raw_writeb(val & ~MAX6369_WDI, wdt->base);

	spin_unlock(&wdt->lock);
}

static void max63xx_mmap_set(struct max63xx_wdt *wdt, u8 set)
{
	u8 val;

	spin_lock(&wdt->lock);

	val = __raw_readb(wdt->base);
	val &= ~MAX6369_WDSET;
	val |= set & MAX6369_WDSET;
	__raw_writeb(val, wdt->base);

	spin_unlock(&wdt->lock);
}

static int max63xx_mmap_init(struct platform_device *p, struct max63xx_wdt *wdt)
{
	wdt->base = devm_platform_ioremap_resource(p, 0);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	spin_lock_init(&wdt->lock);

	wdt->ping = max63xx_mmap_ping;
	wdt->set = max63xx_mmap_set;
	return 0;
}

static int max63xx_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct max63xx_wdt *wdt;
	const struct max63xx_timeout *table;
	int err;

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	/* Attempt to use fwnode first */
	table = device_get_match_data(dev);
	if (!table)
		table = (struct max63xx_timeout *)pdev->id_entry->driver_data;

	if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
		heartbeat = DEFAULT_HEARTBEAT;

	wdt->timeout = max63xx_select_timeout(table, heartbeat);
	if (!wdt->timeout) {
		dev_err(dev, "unable to satisfy %ds heartbeat request\n",
			heartbeat);
		return -EINVAL;
	}

	err = max63xx_mmap_init(pdev, wdt);
	if (err)
		return err;

	platform_set_drvdata(pdev, &wdt->wdd);
	watchdog_set_drvdata(&wdt->wdd, wdt);

	wdt->wdd.parent = dev;
	wdt->wdd.timeout = wdt->timeout->twd;
	wdt->wdd.info = &max63xx_wdt_info;
	wdt->wdd.ops = &max63xx_wdt_ops;

	watchdog_set_nowayout(&wdt->wdd, nowayout);

	err = devm_watchdog_register_device(dev, &wdt->wdd);
	if (err)
		return err;

	dev_info(dev, "using %ds heartbeat with %ds initial delay\n",
		 wdt->timeout->twd, wdt->timeout->tdelay);
	return 0;
}

static const struct platform_device_id max63xx_id_table[] = {
	{ "max6369_wdt", (kernel_ulong_t)max6369_table, },
	{ "max6370_wdt", (kernel_ulong_t)max6369_table, },
	{ "max6371_wdt", (kernel_ulong_t)max6371_table, },
	{ "max6372_wdt", (kernel_ulong_t)max6371_table, },
	{ "max6373_wdt", (kernel_ulong_t)max6373_table, },
	{ "max6374_wdt", (kernel_ulong_t)max6373_table, },
	{ },
};
MODULE_DEVICE_TABLE(platform, max63xx_id_table);

static const struct of_device_id max63xx_dt_id_table[] = {
	{ .compatible = "maxim,max6369", .data = max6369_table, },
	{ .compatible = "maxim,max6370", .data = max6369_table, },
	{ .compatible = "maxim,max6371", .data = max6371_table, },
	{ .compatible = "maxim,max6372", .data = max6371_table, },
	{ .compatible = "maxim,max6373", .data = max6373_table, },
	{ .compatible = "maxim,max6374", .data = max6373_table, },
	{ }
};
MODULE_DEVICE_TABLE(of, max63xx_dt_id_table);

static struct platform_driver max63xx_wdt_driver = {
	.probe		= max63xx_wdt_probe,
	.id_table	= max63xx_id_table,
	.driver		= {
		.name	= "max63xx_wdt",
		.of_match_table = max63xx_dt_id_table,
	},
};

module_platform_driver(max63xx_wdt_driver);

MODULE_AUTHOR("Marc Zyngier <maz@misterjones.org>");
MODULE_DESCRIPTION("max63xx Watchdog Driver");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
		 "Watchdog heartbeat period in seconds from 1 to "
		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
		 __MODULE_STRING(DEFAULT_HEARTBEAT));

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

module_param(nodelay, int, 0);
MODULE_PARM_DESC(nodelay,
		 "Force selection of a timeout setting without initial delay "
		 "(max6373/74 only, default=0)");

MODULE_LICENSE("GPL v2");
Commit	Line	Data
a0d261cc	1	// SPDX-License-Identifier: GPL-2.0-only
66aaa7a5 MZ	2	/*
	3	* drivers/char/watchdog/max63xx_wdt.c
	4	*
	5	* Driver for max63{69,70,71,72,73,74} watchdog timers
	6	*
	7	* Copyright (C) 2009 Marc Zyngier <maz@misterjones.org>
	8	*
66aaa7a5 MZ	9	* This driver assumes the watchdog pins are memory mapped (as it is
	10	* the case for the Arcom Zeus). Should it be connected over GPIOs or
	11	* another interface, some abstraction will have to be introduced.
	12	*/
	13
4c271bb6	14	#include <linux/err.h>
66aaa7a5 MZ	15	#include <linux/module.h>
66aaa7a5 MZ	16	#include <linux/moduleparam.h>
ac316725	17	#include <linux/mod_devicetable.h>
66aaa7a5 MZ	18	#include <linux/types.h>
66aaa7a5 MZ	19	#include <linux/kernel.h>
66aaa7a5	20	#include <linux/watchdog.h>
66aaa7a5 MZ	21	#include <linux/bitops.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/spinlock.h>
66aaa7a5	24	#include <linux/io.h>
5a0e3ad6	25	#include <linux/slab.h>
585ba602	26	#include <linux/property.h>
66aaa7a5 MZ	27
	28	#define DEFAULT_HEARTBEAT 60
	29	#define MAX_HEARTBEAT 60
	30
a0f36833	31	static unsigned int heartbeat = DEFAULT_HEARTBEAT;
86a1e189	32	static bool nowayout = WATCHDOG_NOWAYOUT;
66aaa7a5 MZ	33
	34	/*
	35	* Memory mapping: a single byte, 3 first lower bits to select bit 3
	36	* to ping the watchdog.
	37	*/
	38	#define MAX6369_WDSET (7 << 0)
5f3b2756	39	#define MAX6369_WDI (1 << 3)
66aaa7a5	40
b9be9660	41	#define MAX6369_WDSET_DISABLED 3
66aaa7a5	42
66aaa7a5	43	static int nodelay;
b9be9660 VD	44
	45	struct max63xx_wdt {
	46	struct watchdog_device wdd;
	47	const struct max63xx_timeout *timeout;
	48
	49	/* memory mapping */
	50	void __iomem *base;
	51	spinlock_t lock;
	52
	53	/* WDI and WSET bits write access routines */
	54	void (ping)(struct max63xx_wdt wdt);
	55	void (set)(struct max63xx_wdt wdt, u8 set);
	56	};
66aaa7a5 MZ	57
	58	/*
	59	* The timeout values used are actually the absolute minimum the chip
	60	* offers. Typical values on my board are slightly over twice as long
	61	* (10s setting ends up with a 25s timeout), and can be up to 3 times
	62	* the nominal setting (according to the datasheet). So please take
	63	* these values with a grain of salt. Same goes for the initial delay
	64	* "feature". Only max6373/74 have a few settings without this initial
	65	* delay (selected with the "nodelay" parameter).
	66	*
	67	* I also decided to remove from the tables any timeout smaller than a
	68	* second, as it looked completly overkill...
	69	*/
	70
	71	/* Timeouts in second */
	72	struct max63xx_timeout {
b9be9660 VD	73	const u8 wdset;
	74	const u8 tdelay;
	75	const u8 twd;
66aaa7a5 MZ	76	};
66aaa7a5 MZ	77
b9be9660	78	static const struct max63xx_timeout max6369_table[] = {
66aaa7a5 MZ	79	{ 5, 1, 1 },
	80	{ 6, 10, 10 },
	81	{ 7, 60, 60 },
	82	{ },
	83	};
	84
b9be9660	85	static const struct max63xx_timeout max6371_table[] = {
66aaa7a5 MZ	86	{ 6, 60, 3 },
	87	{ 7, 60, 60 },
	88	{ },
	89	};
	90
b9be9660	91	static const struct max63xx_timeout max6373_table[] = {
66aaa7a5 MZ	92	{ 2, 60, 1 },
	93	{ 5, 0, 1 },
	94	{ 1, 3, 3 },
	95	{ 7, 60, 10 },
	96	{ 6, 0, 10 },
	97	{ },
	98	};
	99
585ba602 LW	100	static const struct max63xx_timeout *
585ba602 LW	101	max63xx_select_timeout(const struct max63xx_timeout *table, int value)
66aaa7a5 MZ	102	{
	103	while (table->twd) {
	104	if (value <= table->twd) {
	105	if (nodelay && table->tdelay == 0)
	106	return table;
	107
	108	if (!nodelay)
	109	return table;
	110	}
	111
	112	table++;
	113	}
	114
	115	return NULL;
	116	}
	117
a0f36833	118	static int max63xx_wdt_ping(struct watchdog_device *wdd)
66aaa7a5	119	{
b9be9660	120	struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd);
66aaa7a5	121
b9be9660	122	wdt->ping(wdt);
a0f36833	123	return 0;
66aaa7a5 MZ	124	}
66aaa7a5 MZ	125
a0f36833	126	static int max63xx_wdt_start(struct watchdog_device *wdd)
66aaa7a5	127	{
b9be9660	128	struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd);
66aaa7a5	129
b9be9660	130	wdt->set(wdt, wdt->timeout->wdset);
66aaa7a5 MZ	131
66aaa7a5 MZ	132	/* check for a edge triggered startup */
b9be9660 VD	133	if (wdt->timeout->tdelay == 0)
b9be9660 VD	134	wdt->ping(wdt);
a0f36833	135	return 0;
66aaa7a5 MZ	136	}
66aaa7a5 MZ	137
a0f36833	138	static int max63xx_wdt_stop(struct watchdog_device *wdd)
66aaa7a5	139	{
b9be9660	140	struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd);
b1183e06	141
b9be9660	142	wdt->set(wdt, MAX6369_WDSET_DISABLED);
a0f36833	143	return 0;
66aaa7a5 MZ	144	}
66aaa7a5 MZ	145
a0f36833 AL	146	static const struct watchdog_ops max63xx_wdt_ops = {
	147	.owner = THIS_MODULE,
	148	.start = max63xx_wdt_start,
	149	.stop = max63xx_wdt_stop,
	150	.ping = max63xx_wdt_ping,
66aaa7a5 MZ	151	};
66aaa7a5 MZ	152
b9be9660 VD	153	static const struct watchdog_info max63xx_wdt_info = {
	154	.options = WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE,
	155	.identity = "max63xx Watchdog",
66aaa7a5 MZ	156	};
66aaa7a5 MZ	157
b9be9660 VD	158	static void max63xx_mmap_ping(struct max63xx_wdt *wdt)
	159	{
	160	u8 val;
	161
	162	spin_lock(&wdt->lock);
	163
	164	val = __raw_readb(wdt->base);
	165
	166	__raw_writeb(val \| MAX6369_WDI, wdt->base);
	167	__raw_writeb(val & ~MAX6369_WDI, wdt->base);
	168
	169	spin_unlock(&wdt->lock);
	170	}
	171
	172	static void max63xx_mmap_set(struct max63xx_wdt *wdt, u8 set)
	173	{
	174	u8 val;
	175
	176	spin_lock(&wdt->lock);
	177
	178	val = __raw_readb(wdt->base);
	179	val &= ~MAX6369_WDSET;
	180	val \|= set & MAX6369_WDSET;
	181	__raw_writeb(val, wdt->base);
	182
	183	spin_unlock(&wdt->lock);
	184	}
	185
	186	static int max63xx_mmap_init(struct platform_device p, struct max63xx_wdt wdt)
	187	{
0f0a6a28	188	wdt->base = devm_platform_ioremap_resource(p, 0);
b9be9660 VD	189	if (IS_ERR(wdt->base))
	190	return PTR_ERR(wdt->base);
	191
	192	spin_lock_init(&wdt->lock);
	193
	194	wdt->ping = max63xx_mmap_ping;
	195	wdt->set = max63xx_mmap_set;
	196	return 0;
	197	}
	198
2d991a16	199	static int max63xx_wdt_probe(struct platform_device *pdev)
66aaa7a5	200	{
80cb6bdd	201	struct device *dev = &pdev->dev;
b9be9660	202	struct max63xx_wdt *wdt;
585ba602	203	const struct max63xx_timeout *table;
b9be9660 VD	204	int err;
b9be9660 VD	205
80cb6bdd	206	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
b9be9660 VD	207	if (!wdt)
b9be9660 VD	208	return -ENOMEM;
66aaa7a5	209
585ba602 LW	210	/* Attempt to use fwnode first */
	211	table = device_get_match_data(dev);
	212	if (!table)
	213	table = (struct max63xx_timeout *)pdev->id_entry->driver_data;
66aaa7a5 MZ	214
	215	if (heartbeat < 1 \|\| heartbeat > MAX_HEARTBEAT)
	216	heartbeat = DEFAULT_HEARTBEAT;
	217
b9be9660 VD	218	wdt->timeout = max63xx_select_timeout(table, heartbeat);
b9be9660 VD	219	if (!wdt->timeout) {
80cb6bdd	220	dev_err(dev, "unable to satisfy %ds heartbeat request\n",
b9be9660	221	heartbeat);
66aaa7a5 MZ	222	return -EINVAL;
	223	}
	224
b9be9660 VD	225	err = max63xx_mmap_init(pdev, wdt);
	226	if (err)
	227	return err;
	228
	229	platform_set_drvdata(pdev, &wdt->wdd);
	230	watchdog_set_drvdata(&wdt->wdd, wdt);
66aaa7a5	231
80cb6bdd	232	wdt->wdd.parent = dev;
b9be9660 VD	233	wdt->wdd.timeout = wdt->timeout->twd;
	234	wdt->wdd.info = &max63xx_wdt_info;
	235	wdt->wdd.ops = &max63xx_wdt_ops;
66aaa7a5	236
b9be9660	237	watchdog_set_nowayout(&wdt->wdd, nowayout);
66aaa7a5	238
80cb6bdd	239	err = devm_watchdog_register_device(dev, &wdt->wdd);
b9be9660 VD	240	if (err)
b9be9660 VD	241	return err;
66aaa7a5	242
80cb6bdd	243	dev_info(dev, "using %ds heartbeat with %ds initial delay\n",
b9be9660 VD	244	wdt->timeout->twd, wdt->timeout->tdelay);
b9be9660 VD	245	return 0;
66aaa7a5 MZ	246	}
66aaa7a5 MZ	247
8c7c72c9	248	static const struct platform_device_id max63xx_id_table[] = {
66aaa7a5 MZ	249	{ "max6369_wdt", (kernel_ulong_t)max6369_table, },
	250	{ "max6370_wdt", (kernel_ulong_t)max6369_table, },
	251	{ "max6371_wdt", (kernel_ulong_t)max6371_table, },
	252	{ "max6372_wdt", (kernel_ulong_t)max6371_table, },
	253	{ "max6373_wdt", (kernel_ulong_t)max6373_table, },
	254	{ "max6374_wdt", (kernel_ulong_t)max6373_table, },
	255	{ },
	256	};
	257	MODULE_DEVICE_TABLE(platform, max63xx_id_table);
	258
585ba602 LW	259	static const struct of_device_id max63xx_dt_id_table[] = {
	260	{ .compatible = "maxim,max6369", .data = max6369_table, },
	261	{ .compatible = "maxim,max6370", .data = max6369_table, },
	262	{ .compatible = "maxim,max6371", .data = max6371_table, },
	263	{ .compatible = "maxim,max6372", .data = max6371_table, },
	264	{ .compatible = "maxim,max6373", .data = max6373_table, },
	265	{ .compatible = "maxim,max6374", .data = max6373_table, },
	266	{ }
	267	};
	268	MODULE_DEVICE_TABLE(of, max63xx_dt_id_table);
	269
66aaa7a5 MZ	270	static struct platform_driver max63xx_wdt_driver = {
66aaa7a5 MZ	271	.probe = max63xx_wdt_probe,
66aaa7a5 MZ	272	.id_table = max63xx_id_table,
	273	.driver = {
	274	.name = "max63xx_wdt",
585ba602	275	.of_match_table = max63xx_dt_id_table,
66aaa7a5 MZ	276	},
	277	};
	278
b8ec6118	279	module_platform_driver(max63xx_wdt_driver);
66aaa7a5 MZ	280
	281	MODULE_AUTHOR("Marc Zyngier <maz@misterjones.org>");
	282	MODULE_DESCRIPTION("max63xx Watchdog Driver");
	283
	284	module_param(heartbeat, int, 0);
	285	MODULE_PARM_DESC(heartbeat,
	286	"Watchdog heartbeat period in seconds from 1 to "
	287	__MODULE_STRING(MAX_HEARTBEAT) ", default "
	288	__MODULE_STRING(DEFAULT_HEARTBEAT));
	289
86a1e189	290	module_param(nowayout, bool, 0);
66aaa7a5 MZ	291	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	292	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	293
	294	module_param(nodelay, int, 0);
	295	MODULE_PARM_DESC(nodelay,
	296	"Force selection of a timeout setting without initial delay "
	297	"(max6373/74 only, default=0)");
	298
29efefb9	299	MODULE_LICENSE("GPL v2");