[linux-2.6-block.git] / drivers / watchdog / lantiq_wdt.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 *  Copyright (C) 2010 John Crispin <john@phrozen.org>
 *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
 *  Based on EP93xx wdt driver
 */

#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/watchdog.h>
#include <linux/of_platform.h>
#include <linux/uaccess.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#include <lantiq_soc.h>

#define LTQ_XRX_RCU_RST_STAT		0x0014
#define LTQ_XRX_RCU_RST_STAT_WDT	BIT(31)

/* CPU0 Reset Source Register */
#define LTQ_FALCON_SYS1_CPU0RS		0x0060
/* reset cause mask */
#define LTQ_FALCON_SYS1_CPU0RS_MASK	0x0007
#define LTQ_FALCON_SYS1_CPU0RS_WDT	0x02

/*
 * Section 3.4 of the datasheet
 * The password sequence protects the WDT control register from unintended
 * write actions, which might cause malfunction of the WDT.
 *
 * essentially the following two magic passwords need to be written to allow
 * IO access to the WDT core
 */
#define LTQ_WDT_CR_PW1		0x00BE0000
#define LTQ_WDT_CR_PW2		0x00DC0000

#define LTQ_WDT_CR		0x0		/* watchdog control register */
#define  LTQ_WDT_CR_GEN		BIT(31)		/* enable bit */
/* Pre-warning limit set to 1/16 of max WDT period */
#define  LTQ_WDT_CR_PWL		(0x3 << 26)
/* set clock divider to 0x40000 */
#define  LTQ_WDT_CR_CLKDIV	(0x3 << 24)
#define  LTQ_WDT_CR_PW_MASK	GENMASK(23, 16)	/* Password field */
#define  LTQ_WDT_CR_MAX_TIMEOUT	((1 << 16) - 1)	/* The reload field is 16 bit */
#define LTQ_WDT_SR		0x8		/* watchdog status register */
#define  LTQ_WDT_SR_EN		BIT(31)		/* Enable */
#define  LTQ_WDT_SR_VALUE_MASK	GENMASK(15, 0)	/* Timer value */

#define LTQ_WDT_DIVIDER		0x40000

static bool nowayout = WATCHDOG_NOWAYOUT;

struct ltq_wdt_hw {
	int (*bootstatus_get)(struct device *dev);
};

struct ltq_wdt_priv {
	struct watchdog_device wdt;
	void __iomem *membase;
	unsigned long clk_rate;
};

static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
{
	return __raw_readl(priv->membase + offset);
}

static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
{
	__raw_writel(val, priv->membase + offset);
}

static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
			 u32 offset)
{
	u32 val = ltq_wdt_r32(priv, offset);

	val &= ~(clear);
	val |= set;
	ltq_wdt_w32(priv, val, offset);
}

static struct ltq_wdt_priv *ltq_wdt_get_priv(struct watchdog_device *wdt)
{
	return container_of(wdt, struct ltq_wdt_priv, wdt);
}

static struct watchdog_info ltq_wdt_info = {
	.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
		   WDIOF_CARDRESET,
	.identity = "ltq_wdt",
};

static int ltq_wdt_start(struct watchdog_device *wdt)
{
	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	u32 timeout;

	timeout = wdt->timeout * priv->clk_rate;

	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	/* write the second magic plus the configuration and new timeout */
	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
		     LTQ_WDT_CR_GEN | LTQ_WDT_CR_PWL | LTQ_WDT_CR_CLKDIV |
		     LTQ_WDT_CR_PW2 | timeout,
		     LTQ_WDT_CR);

	return 0;
}

static int ltq_wdt_stop(struct watchdog_device *wdt)
{
	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);

	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	ltq_wdt_mask(priv, LTQ_WDT_CR_GEN | LTQ_WDT_CR_PW_MASK,
		     LTQ_WDT_CR_PW2, LTQ_WDT_CR);

	return 0;
}

static int ltq_wdt_ping(struct watchdog_device *wdt)
{
	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	u32 timeout;

	timeout = wdt->timeout * priv->clk_rate;

	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	/* write the second magic plus the configuration and new timeout */
	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
		     LTQ_WDT_CR_PW2 | timeout, LTQ_WDT_CR);

	return 0;
}

static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
{
	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	u64 timeout;

	timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
	return do_div(timeout, priv->clk_rate);
}

static const struct watchdog_ops ltq_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= ltq_wdt_start,
	.stop		= ltq_wdt_stop,
	.ping		= ltq_wdt_ping,
	.get_timeleft	= ltq_wdt_get_timeleft,
};

static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
{
	struct regmap *rcu_regmap;
	u32 val;
	int err;

	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
	if (IS_ERR(rcu_regmap))
		return PTR_ERR(rcu_regmap);

	err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
	if (err)
		return err;

	if (val & LTQ_XRX_RCU_RST_STAT_WDT)
		return WDIOF_CARDRESET;

	return 0;
}

static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
{
	struct regmap *rcu_regmap;
	u32 val;
	int err;

	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
						     "lantiq,rcu");
	if (IS_ERR(rcu_regmap))
		return PTR_ERR(rcu_regmap);

	err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
	if (err)
		return err;

	if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
		return WDIOF_CARDRESET;

	return 0;
}

static int ltq_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct ltq_wdt_priv *priv;
	struct watchdog_device *wdt;
	struct resource *res;
	struct clk *clk;
	const struct ltq_wdt_hw *ltq_wdt_hw;
	int ret;
	u32 status;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->membase = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->membase))
		return PTR_ERR(priv->membase);

	/* we do not need to enable the clock as it is always running */
	clk = clk_get_io();
	priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
	if (!priv->clk_rate) {
		dev_err(dev, "clock rate less than divider %i\n",
			LTQ_WDT_DIVIDER);
		return -EINVAL;
	}

	wdt = &priv->wdt;
	wdt->info		= &ltq_wdt_info;
	wdt->ops		= &ltq_wdt_ops;
	wdt->min_timeout	= 1;
	wdt->max_timeout	= LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
	wdt->timeout		= wdt->max_timeout;
	wdt->parent		= dev;

	ltq_wdt_hw = of_device_get_match_data(dev);
	if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
		ret = ltq_wdt_hw->bootstatus_get(dev);
		if (ret >= 0)
			wdt->bootstatus = ret;
	}

	watchdog_set_nowayout(wdt, nowayout);
	watchdog_init_timeout(wdt, 0, dev);

	status = ltq_wdt_r32(priv, LTQ_WDT_SR);
	if (status & LTQ_WDT_SR_EN) {
		/*
		 * If the watchdog is already running overwrite it with our
		 * new settings. Stop is not needed as the start call will
		 * replace all settings anyway.
		 */
		ltq_wdt_start(wdt);
		set_bit(WDOG_HW_RUNNING, &wdt->status);
	}

	return devm_watchdog_register_device(dev, wdt);
}

static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
	.bootstatus_get = ltq_wdt_xrx_bootstatus_get,
};

static const struct ltq_wdt_hw ltq_wdt_falcon = {
	.bootstatus_get = ltq_wdt_falcon_bootstatus_get,
};

static const struct of_device_id ltq_wdt_match[] = {
	{ .compatible = "lantiq,wdt", .data = NULL },
	{ .compatible = "lantiq,xrx100-wdt", .data = &ltq_wdt_xrx100 },
	{ .compatible = "lantiq,falcon-wdt", .data = &ltq_wdt_falcon },
	{},
};
MODULE_DEVICE_TABLE(of, ltq_wdt_match);

static struct platform_driver ltq_wdt_driver = {
	.probe = ltq_wdt_probe,
	.driver = {
		.name = "wdt",
		.of_match_table = ltq_wdt_match,
	},
};

module_platform_driver(ltq_wdt_driver);

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
MODULE_AUTHOR("John Crispin <john@phrozen.org>");
MODULE_DESCRIPTION("Lantiq SoC Watchdog");
MODULE_LICENSE("GPL");
Commit	Line	Data
2f58b8d0 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
f3519a66	6	* Copyright (C) 2010 John Crispin <john@phrozen.org>
710322ba	7	* Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
2f58b8d0 JC	8	* Based on EP93xx wdt driver
	9	*/
	10
	11	#include <linux/module.h>
1f59f8af	12	#include <linux/bitops.h>
2f58b8d0	13	#include <linux/watchdog.h>
cdb86121	14	#include <linux/of_platform.h>
2f58b8d0 JC	15	#include <linux/uaccess.h>
	16	#include <linux/clk.h>
	17	#include <linux/io.h>
710322ba HM	18	#include <linux/regmap.h>
710322ba HM	19	#include <linux/mfd/syscon.h>
2f58b8d0	20
cdb86121	21	#include <lantiq_soc.h>
2f58b8d0	22
710322ba HM	23	#define LTQ_XRX_RCU_RST_STAT 0x0014
	24	#define LTQ_XRX_RCU_RST_STAT_WDT BIT(31)
	25
	26	/* CPU0 Reset Source Register */
	27	#define LTQ_FALCON_SYS1_CPU0RS 0x0060
	28	/* reset cause mask */
	29	#define LTQ_FALCON_SYS1_CPU0RS_MASK 0x0007
	30	#define LTQ_FALCON_SYS1_CPU0RS_WDT 0x02
	31
cdb86121 JC	32	/*
cdb86121 JC	33	* Section 3.4 of the datasheet
2f58b8d0 JC	34	* The password sequence protects the WDT control register from unintended
	35	* write actions, which might cause malfunction of the WDT.
	36	*
	37	* essentially the following two magic passwords need to be written to allow
	38	* IO access to the WDT core
	39	*/
1f59f8af HM	40	#define LTQ_WDT_CR_PW1 0x00BE0000
	41	#define LTQ_WDT_CR_PW2 0x00DC0000
	42
	43	#define LTQ_WDT_CR 0x0 /* watchdog control register */
	44	#define LTQ_WDT_CR_GEN BIT(31) /* enable bit */
	45	/* Pre-warning limit set to 1/16 of max WDT period */
	46	#define LTQ_WDT_CR_PWL (0x3 << 26)
	47	/* set clock divider to 0x40000 */
	48	#define LTQ_WDT_CR_CLKDIV (0x3 << 24)
	49	#define LTQ_WDT_CR_PW_MASK GENMASK(23, 16) /* Password field */
	50	#define LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */
dcd7e04e HM	51	#define LTQ_WDT_SR 0x8 /* watchdog status register */
dcd7e04e HM	52	#define LTQ_WDT_SR_EN BIT(31) /* Enable */
c99d9df1	53	#define LTQ_WDT_SR_VALUE_MASK GENMASK(15, 0) /* Timer value */
2f58b8d0	54
2f58b8d0	55	#define LTQ_WDT_DIVIDER 0x40000
2f58b8d0	56
86a1e189	57	static bool nowayout = WATCHDOG_NOWAYOUT;
2f58b8d0	58
dcd7e04e HM	59	struct ltq_wdt_hw {
	60	int (bootstatus_get)(struct device dev);
	61	};
2f58b8d0	62
dcd7e04e HM	63	struct ltq_wdt_priv {
	64	struct watchdog_device wdt;
	65	void __iomem *membase;
	66	unsigned long clk_rate;
	67	};
2f58b8d0	68
dcd7e04e	69	static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
2f58b8d0	70	{
dcd7e04e	71	return __raw_readl(priv->membase + offset);
2f58b8d0 JC	72	}
2f58b8d0 JC	73
dcd7e04e	74	static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
2f58b8d0	75	{
dcd7e04e	76	__raw_writel(val, priv->membase + offset);
2f58b8d0 JC	77	}
2f58b8d0 JC	78
dcd7e04e HM	79	static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
dcd7e04e HM	80	u32 offset)
2f58b8d0	81	{
dcd7e04e HM	82	u32 val = ltq_wdt_r32(priv, offset);
	83
	84	val &= ~(clear);
	85	val \|= set;
	86	ltq_wdt_w32(priv, val, offset);
	87	}
2f58b8d0	88
dcd7e04e HM	89	static struct ltq_wdt_priv ltq_wdt_get_priv(struct watchdog_device wdt)
	90	{
	91	return container_of(wdt, struct ltq_wdt_priv, wdt);
2f58b8d0 JC	92	}
2f58b8d0 JC	93
dcd7e04e	94	static struct watchdog_info ltq_wdt_info = {
2f58b8d0	95	.options = WDIOF_MAGICCLOSE \| WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \|
dcd7e04e	96	WDIOF_CARDRESET,
2f58b8d0 JC	97	.identity = "ltq_wdt",
	98	};
	99
dcd7e04e	100	static int ltq_wdt_start(struct watchdog_device *wdt)
2f58b8d0	101	{
dcd7e04e HM	102	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	103	u32 timeout;
	104
	105	timeout = wdt->timeout * priv->clk_rate;
	106
	107	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	108	/* write the second magic plus the configuration and new timeout */
	109	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK \| LTQ_WDT_CR_MAX_TIMEOUT,
	110	LTQ_WDT_CR_GEN \| LTQ_WDT_CR_PWL \| LTQ_WDT_CR_CLKDIV \|
	111	LTQ_WDT_CR_PW2 \| timeout,
	112	LTQ_WDT_CR);
	113
	114	return 0;
2f58b8d0 JC	115	}
2f58b8d0 JC	116
dcd7e04e	117	static int ltq_wdt_stop(struct watchdog_device *wdt)
2f58b8d0	118	{
dcd7e04e HM	119	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	120
	121	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	122	ltq_wdt_mask(priv, LTQ_WDT_CR_GEN \| LTQ_WDT_CR_PW_MASK,
	123	LTQ_WDT_CR_PW2, LTQ_WDT_CR);
2f58b8d0	124
dcd7e04e	125	return 0;
2f58b8d0 JC	126	}
2f58b8d0 JC	127
dcd7e04e	128	static int ltq_wdt_ping(struct watchdog_device *wdt)
2f58b8d0	129	{
dcd7e04e HM	130	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	131	u32 timeout;
	132
	133	timeout = wdt->timeout * priv->clk_rate;
	134
	135	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	136	/* write the second magic plus the configuration and new timeout */
	137	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK \| LTQ_WDT_CR_MAX_TIMEOUT,
	138	LTQ_WDT_CR_PW2 \| timeout, LTQ_WDT_CR);
2f58b8d0 JC	139
	140	return 0;
	141	}
	142
c99d9df1 HM	143	static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
	144	{
	145	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	146	u64 timeout;
	147
	148	timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
	149	return do_div(timeout, priv->clk_rate);
	150	}
	151
dcd7e04e	152	static const struct watchdog_ops ltq_wdt_ops = {
2f58b8d0	153	.owner = THIS_MODULE,
dcd7e04e HM	154	.start = ltq_wdt_start,
	155	.stop = ltq_wdt_stop,
	156	.ping = ltq_wdt_ping,
c99d9df1	157	.get_timeleft = ltq_wdt_get_timeleft,
2f58b8d0 JC	158	};
2f58b8d0 JC	159
dcd7e04e	160	static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
710322ba	161	{
710322ba HM	162	struct regmap *rcu_regmap;
	163	u32 val;
	164	int err;
	165
	166	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
	167	if (IS_ERR(rcu_regmap))
	168	return PTR_ERR(rcu_regmap);
	169
	170	err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
	171	if (err)
	172	return err;
	173
	174	if (val & LTQ_XRX_RCU_RST_STAT_WDT)
dcd7e04e	175	return WDIOF_CARDRESET;
710322ba HM	176
	177	return 0;
	178	}
	179
dcd7e04e	180	static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
710322ba	181	{
710322ba HM	182	struct regmap *rcu_regmap;
	183	u32 val;
	184	int err;
	185
	186	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
	187	"lantiq,rcu");
	188	if (IS_ERR(rcu_regmap))
	189	return PTR_ERR(rcu_regmap);
	190
	191	err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
	192	if (err)
	193	return err;
	194
	195	if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
dcd7e04e	196	return WDIOF_CARDRESET;
710322ba HM	197
	198	return 0;
	199	}
	200
dcd7e04e	201	static int ltq_wdt_probe(struct platform_device *pdev)
2f58b8d0	202	{
dcd7e04e HM	203	struct device *dev = &pdev->dev;
	204	struct ltq_wdt_priv *priv;
	205	struct watchdog_device *wdt;
	206	struct resource *res;
2f58b8d0	207	struct clk *clk;
dcd7e04e	208	const struct ltq_wdt_hw *ltq_wdt_hw;
710322ba	209	int ret;
dcd7e04e	210	u32 status;
2f58b8d0	211
dcd7e04e HM	212	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	213	if (!priv)
	214	return -ENOMEM;
2f58b8d0	215
dcd7e04e HM	216	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	217	priv->membase = devm_ioremap_resource(dev, res);
	218	if (IS_ERR(priv->membase))
	219	return PTR_ERR(priv->membase);
710322ba	220
2f58b8d0	221	/* we do not need to enable the clock as it is always running */
cdb86121	222	clk = clk_get_io();
dcd7e04e HM	223	priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
	224	if (!priv->clk_rate) {
	225	dev_err(dev, "clock rate less than divider %i\n",
	226	LTQ_WDT_DIVIDER);
	227	return -EINVAL;
cdb86121	228	}
2f58b8d0	229
dcd7e04e HM	230	wdt = &priv->wdt;
	231	wdt->info = &ltq_wdt_info;
	232	wdt->ops = &ltq_wdt_ops;
	233	wdt->min_timeout = 1;
	234	wdt->max_timeout = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
	235	wdt->timeout = wdt->max_timeout;
	236	wdt->parent = dev;
	237
	238	ltq_wdt_hw = of_device_get_match_data(dev);
	239	if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
	240	ret = ltq_wdt_hw->bootstatus_get(dev);
	241	if (ret >= 0)
	242	wdt->bootstatus = ret;
	243	}
2f58b8d0	244
dcd7e04e HM	245	watchdog_set_nowayout(wdt, nowayout);
	246	watchdog_init_timeout(wdt, 0, dev);
	247
	248	status = ltq_wdt_r32(priv, LTQ_WDT_SR);
	249	if (status & LTQ_WDT_SR_EN) {
	250	/*
	251	* If the watchdog is already running overwrite it with our
	252	* new settings. Stop is not needed as the start call will
	253	* replace all settings anyway.
	254	*/
	255	ltq_wdt_start(wdt);
	256	set_bit(WDOG_HW_RUNNING, &wdt->status);
	257	}
2f58b8d0	258
dcd7e04e	259	return devm_watchdog_register_device(dev, wdt);
2f58b8d0 JC	260	}
2f58b8d0 JC	261
dcd7e04e HM	262	static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
	263	.bootstatus_get = ltq_wdt_xrx_bootstatus_get,
	264	};
	265
	266	static const struct ltq_wdt_hw ltq_wdt_falcon = {
	267	.bootstatus_get = ltq_wdt_falcon_bootstatus_get,
	268	};
	269
cdb86121	270	static const struct of_device_id ltq_wdt_match[] = {
dcd7e04e HM	271	{ .compatible = "lantiq,wdt", .data = NULL },
	272	{ .compatible = "lantiq,xrx100-wdt", .data = &ltq_wdt_xrx100 },
	273	{ .compatible = "lantiq,falcon-wdt", .data = &ltq_wdt_falcon },
cdb86121 JC	274	{},
	275	};
	276	MODULE_DEVICE_TABLE(of, ltq_wdt_match);
2f58b8d0 JC	277
2f58b8d0 JC	278	static struct platform_driver ltq_wdt_driver = {
cdb86121	279	.probe = ltq_wdt_probe,
2f58b8d0	280	.driver = {
cdb86121	281	.name = "wdt",
cdb86121	282	.of_match_table = ltq_wdt_match,
2f58b8d0 JC	283	},
	284	};
	285
cdb86121	286	module_platform_driver(ltq_wdt_driver);
2f58b8d0	287
86a1e189	288	module_param(nowayout, bool, 0);
2f58b8d0	289	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
f3519a66	290	MODULE_AUTHOR("John Crispin <john@phrozen.org>");
2f58b8d0 JC	291	MODULE_DESCRIPTION("Lantiq SoC Watchdog");
2f58b8d0 JC	292	MODULE_LICENSE("GPL");