Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / watchdog / jz4740_wdt.c
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1/*
2 * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
3 * JZ4740 Watchdog driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/types.h>
19#include <linux/kernel.h>
f865c352 20#include <linux/watchdog.h>
f865c352 21#include <linux/platform_device.h>
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22#include <linux/io.h>
23#include <linux/device.h>
24#include <linux/clk.h>
25#include <linux/slab.h>
85f6df14 26#include <linux/err.h>
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27
28#include <asm/mach-jz4740/timer.h>
29
30#define JZ_REG_WDT_TIMER_DATA 0x0
31#define JZ_REG_WDT_COUNTER_ENABLE 0x4
32#define JZ_REG_WDT_TIMER_COUNTER 0x8
33#define JZ_REG_WDT_TIMER_CONTROL 0xC
34
35#define JZ_WDT_CLOCK_PCLK 0x1
36#define JZ_WDT_CLOCK_RTC 0x2
37#define JZ_WDT_CLOCK_EXT 0x4
38
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39#define JZ_WDT_CLOCK_DIV_SHIFT 3
40
41#define JZ_WDT_CLOCK_DIV_1 (0 << JZ_WDT_CLOCK_DIV_SHIFT)
42#define JZ_WDT_CLOCK_DIV_4 (1 << JZ_WDT_CLOCK_DIV_SHIFT)
43#define JZ_WDT_CLOCK_DIV_16 (2 << JZ_WDT_CLOCK_DIV_SHIFT)
44#define JZ_WDT_CLOCK_DIV_64 (3 << JZ_WDT_CLOCK_DIV_SHIFT)
45#define JZ_WDT_CLOCK_DIV_256 (4 << JZ_WDT_CLOCK_DIV_SHIFT)
46#define JZ_WDT_CLOCK_DIV_1024 (5 << JZ_WDT_CLOCK_DIV_SHIFT)
47
48#define DEFAULT_HEARTBEAT 5
49#define MAX_HEARTBEAT 2048
50
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51static bool nowayout = WATCHDOG_NOWAYOUT;
52module_param(nowayout, bool, 0);
53MODULE_PARM_DESC(nowayout,
54 "Watchdog cannot be stopped once started (default="
55 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
f865c352 56
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57static unsigned int heartbeat = DEFAULT_HEARTBEAT;
58module_param(heartbeat, uint, 0);
59MODULE_PARM_DESC(heartbeat,
60 "Watchdog heartbeat period in seconds from 1 to "
61 __MODULE_STRING(MAX_HEARTBEAT) ", default "
62 __MODULE_STRING(DEFAULT_HEARTBEAT));
f865c352 63
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64struct jz4740_wdt_drvdata {
65 struct watchdog_device wdt;
66 void __iomem *base;
67 struct clk *rtc_clk;
68};
f865c352 69
85f6df14 70static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
f865c352 71{
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72 struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
73
74 writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
75 return 0;
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76}
77
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78static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
79 unsigned int new_timeout)
f865c352 80{
85f6df14 81 struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
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82 unsigned int rtc_clk_rate;
83 unsigned int timeout_value;
84 unsigned short clock_div = JZ_WDT_CLOCK_DIV_1;
85
85f6df14 86 rtc_clk_rate = clk_get_rate(drvdata->rtc_clk);
f865c352 87
85f6df14 88 timeout_value = rtc_clk_rate * new_timeout;
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89 while (timeout_value > 0xffff) {
90 if (clock_div == JZ_WDT_CLOCK_DIV_1024) {
91 /* Requested timeout too high;
92 * use highest possible value. */
93 timeout_value = 0xffff;
94 break;
95 }
96 timeout_value >>= 2;
97 clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT);
98 }
99
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100 writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
101 writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
f865c352 102
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103 writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA);
104 writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
f865c352 105 writew(clock_div | JZ_WDT_CLOCK_RTC,
85f6df14 106 drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
f865c352 107
85f6df14 108 writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
f865c352 109
0197c1c4 110 wdt_dev->timeout = new_timeout;
85f6df14 111 return 0;
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112}
113
85f6df14 114static int jz4740_wdt_start(struct watchdog_device *wdt_dev)
f865c352 115{
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116 jz4740_timer_enable_watchdog();
117 jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
f865c352 118
85f6df14 119 return 0;
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120}
121
85f6df14 122static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
f865c352 123{
85f6df14 124 struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
742e4b63 125
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126 jz4740_timer_disable_watchdog();
127 writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
f865c352 128
85f6df14 129 return 0;
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130}
131
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132static const struct watchdog_info jz4740_wdt_info = {
133 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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134 .identity = "jz4740 Watchdog",
135};
136
85f6df14 137static const struct watchdog_ops jz4740_wdt_ops = {
f865c352 138 .owner = THIS_MODULE,
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139 .start = jz4740_wdt_start,
140 .stop = jz4740_wdt_stop,
141 .ping = jz4740_wdt_ping,
142 .set_timeout = jz4740_wdt_set_timeout,
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143};
144
2d991a16 145static int jz4740_wdt_probe(struct platform_device *pdev)
f865c352 146{
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147 struct jz4740_wdt_drvdata *drvdata;
148 struct watchdog_device *jz4740_wdt;
149 struct resource *res;
150 int ret;
151
152 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct jz4740_wdt_drvdata),
153 GFP_KERNEL);
154 if (!drvdata) {
155 dev_err(&pdev->dev, "Unable to alloacate watchdog device\n");
156 return -ENOMEM;
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157 }
158
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159 if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
160 heartbeat = DEFAULT_HEARTBEAT;
f865c352 161
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162 jz4740_wdt = &drvdata->wdt;
163 jz4740_wdt->info = &jz4740_wdt_info;
164 jz4740_wdt->ops = &jz4740_wdt_ops;
165 jz4740_wdt->timeout = heartbeat;
166 jz4740_wdt->min_timeout = 1;
167 jz4740_wdt->max_timeout = MAX_HEARTBEAT;
168 watchdog_set_nowayout(jz4740_wdt, nowayout);
169 watchdog_set_drvdata(jz4740_wdt, drvdata);
170
171 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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172 drvdata->base = devm_ioremap_resource(&pdev->dev, res);
173 if (IS_ERR(drvdata->base)) {
174 ret = PTR_ERR(drvdata->base);
85f6df14 175 goto err_out;
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176 }
177
5f314970 178 drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
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179 if (IS_ERR(drvdata->rtc_clk)) {
180 dev_err(&pdev->dev, "cannot find RTC clock\n");
181 ret = PTR_ERR(drvdata->rtc_clk);
182 goto err_out;
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183 }
184
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185 ret = watchdog_register_device(&drvdata->wdt);
186 if (ret < 0)
f865c352 187 goto err_disable_clk;
f865c352 188
85f6df14 189 platform_set_drvdata(pdev, drvdata);
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190 return 0;
191
192err_disable_clk:
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193 clk_put(drvdata->rtc_clk);
194err_out:
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195 return ret;
196}
197
4b12b896 198static int jz4740_wdt_remove(struct platform_device *pdev)
f865c352 199{
85f6df14 200 struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
f865c352 201
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202 jz4740_wdt_stop(&drvdata->wdt);
203 watchdog_unregister_device(&drvdata->wdt);
204 clk_put(drvdata->rtc_clk);
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205
206 return 0;
207}
208
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209static struct platform_driver jz4740_wdt_driver = {
210 .probe = jz4740_wdt_probe,
82268714 211 .remove = jz4740_wdt_remove,
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212 .driver = {
213 .name = "jz4740-wdt",
214 .owner = THIS_MODULE,
215 },
216};
217
b8ec6118 218module_platform_driver(jz4740_wdt_driver);
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219
220MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
221MODULE_DESCRIPTION("jz4740 Watchdog Driver");
f865c352 222MODULE_LICENSE("GPL");
f865c352 223MODULE_ALIAS("platform:jz4740-wdt");