watchdog: s3c2410_wdt: Simplify using dev_err_probe()
[linux-block.git] / drivers / watchdog / ixp4xx_wdt.c
CommitLineData
21a0a29d 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4 2/*
f30c2269 3 * drivers/char/watchdog/ixp4xx_wdt.c
1da177e4
LT
4 *
5 * Watchdog driver for Intel IXP4xx network processors
6 *
7 * Author: Deepak Saxena <dsaxena@plexity.net>
21a0a29d 8 * Author: Linus Walleij <linus.walleij@linaro.org>
1da177e4
LT
9 *
10 * Copyright 2004 (c) MontaVista, Software, Inc.
11 * Based on sa1100 driver, Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
1da177e4
LT
12 */
13
1da177e4 14#include <linux/module.h>
1da177e4
LT
15#include <linux/types.h>
16#include <linux/kernel.h>
1da177e4 17#include <linux/watchdog.h>
21a0a29d
LW
18#include <linux/bits.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/soc/ixp4xx/cpu.h>
22
23struct ixp4xx_wdt {
24 struct watchdog_device wdd;
25 void __iomem *base;
26 unsigned long rate;
27};
1da177e4 28
21a0a29d
LW
29/* Fallback if we do not have a clock for this */
30#define IXP4XX_TIMER_FREQ 66666000
1da177e4 31
21a0a29d
LW
32/* Registers after the timer registers */
33#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
34#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
35#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
36#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
1da177e4 37
21a0a29d
LW
38#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
39#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
40#define IXP4XX_WDT_KEY 0x0000482E
41#define IXP4XX_WDT_RESET_ENABLE 0x00000001
42#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
43#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
1da177e4 44
21a0a29d
LW
45static inline
46struct ixp4xx_wdt *to_ixp4xx_wdt(struct watchdog_device *wdd)
1da177e4 47{
21a0a29d 48 return container_of(wdd, struct ixp4xx_wdt, wdd);
1da177e4
LT
49}
50
21a0a29d 51static int ixp4xx_wdt_start(struct watchdog_device *wdd)
1da177e4 52{
21a0a29d 53 struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
1da177e4 54
21a0a29d
LW
55 __raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
56 __raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET);
57 __raw_writel(wdd->timeout * iwdt->rate,
58 iwdt->base + IXP4XX_OSWT_OFFSET);
59 __raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE,
60 iwdt->base + IXP4XX_OSWE_OFFSET);
61 __raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET);
1da177e4 62
21a0a29d 63 return 0;
1da177e4
LT
64}
65
21a0a29d 66static int ixp4xx_wdt_stop(struct watchdog_device *wdd)
1da177e4 67{
21a0a29d 68 struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
1da177e4 69
21a0a29d
LW
70 __raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
71 __raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET);
72 __raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET);
1da177e4 73
21a0a29d 74 return 0;
1da177e4
LT
75}
76
21a0a29d
LW
77static int ixp4xx_wdt_set_timeout(struct watchdog_device *wdd,
78 unsigned int timeout)
1da177e4 79{
21a0a29d
LW
80 wdd->timeout = timeout;
81 if (watchdog_active(wdd))
82 ixp4xx_wdt_start(wdd);
1da177e4
LT
83
84 return 0;
85}
86
1aea5228
LW
87static int ixp4xx_wdt_restart(struct watchdog_device *wdd,
88 unsigned long action, void *data)
89{
90 struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
91
92 __raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
93 __raw_writel(0, iwdt->base + IXP4XX_OSWT_OFFSET);
94 __raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE,
95 iwdt->base + IXP4XX_OSWE_OFFSET);
96
97 return 0;
98}
99
21a0a29d
LW
100static const struct watchdog_ops ixp4xx_wdt_ops = {
101 .start = ixp4xx_wdt_start,
102 .stop = ixp4xx_wdt_stop,
103 .set_timeout = ixp4xx_wdt_set_timeout,
1aea5228 104 .restart = ixp4xx_wdt_restart,
21a0a29d 105 .owner = THIS_MODULE,
1da177e4
LT
106};
107
21a0a29d
LW
108static const struct watchdog_info ixp4xx_wdt_info = {
109 .options = WDIOF_KEEPALIVEPING
110 | WDIOF_MAGICCLOSE
111 | WDIOF_SETTIMEOUT,
112 .identity = KBUILD_MODNAME,
1da177e4
LT
113};
114
21a0a29d
LW
115/* Devres-handled clock disablement */
116static void ixp4xx_clock_action(void *d)
117{
118 clk_disable_unprepare(d);
119}
120
121static int ixp4xx_wdt_probe(struct platform_device *pdev)
1da177e4 122{
21a0a29d
LW
123 struct device *dev = &pdev->dev;
124 struct ixp4xx_wdt *iwdt;
125 struct clk *clk;
1da177e4 126 int ret;
1da177e4 127
0ba8b9b2 128 if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) {
21a0a29d 129 dev_err(dev, "Rev. A0 IXP42x CPU detected - watchdog disabled\n");
1da177e4
LT
130 return -ENODEV;
131 }
1da177e4 132
21a0a29d
LW
133 iwdt = devm_kzalloc(dev, sizeof(*iwdt), GFP_KERNEL);
134 if (!iwdt)
135 return -ENOMEM;
abd1c6ad 136 iwdt->base = (void __iomem *)dev->platform_data;
1da177e4 137
21a0a29d
LW
138 /*
139 * Retrieve rate from a fixed clock from the device tree if
140 * the parent has that, else use the default clock rate.
141 */
142 clk = devm_clk_get(dev->parent, NULL);
143 if (!IS_ERR(clk)) {
144 ret = clk_prepare_enable(clk);
145 if (ret)
146 return ret;
147 ret = devm_add_action_or_reset(dev, ixp4xx_clock_action, clk);
148 if (ret)
149 return ret;
150 iwdt->rate = clk_get_rate(clk);
151 }
152 if (!iwdt->rate)
153 iwdt->rate = IXP4XX_TIMER_FREQ;
1da177e4 154
21a0a29d
LW
155 iwdt->wdd.info = &ixp4xx_wdt_info;
156 iwdt->wdd.ops = &ixp4xx_wdt_ops;
157 iwdt->wdd.min_timeout = 1;
158 iwdt->wdd.max_timeout = U32_MAX / iwdt->rate;
159 iwdt->wdd.parent = dev;
160 /* Default to 60 seconds */
161 iwdt->wdd.timeout = 60U;
162 watchdog_init_timeout(&iwdt->wdd, 0, dev);
1da177e4 163
21a0a29d
LW
164 if (__raw_readl(iwdt->base + IXP4XX_OSST_OFFSET) &
165 IXP4XX_OSST_TIMER_WARM_RESET)
166 iwdt->wdd.bootstatus = WDIOF_CARDRESET;
167
168 ret = devm_watchdog_register_device(dev, &iwdt->wdd);
169 if (ret)
170 return ret;
171
172 dev_info(dev, "IXP4xx watchdog available\n");
1da177e4 173
21a0a29d
LW
174 return 0;
175}
1da177e4 176
21a0a29d
LW
177static struct platform_driver ixp4xx_wdt_driver = {
178 .probe = ixp4xx_wdt_probe,
179 .driver = {
180 .name = "ixp4xx-watchdog",
181 },
182};
183module_platform_driver(ixp4xx_wdt_driver);
1da177e4 184
21a0a29d
LW
185MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net>");
186MODULE_DESCRIPTION("IXP4xx Network Processor Watchdog");
1da177e4 187MODULE_LICENSE("GPL");