Commit | Line | Data |
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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e1fee94f OS |
2 | /* |
3 | * Watchdog Timer Driver | |
4 | * for ITE IT87xx Environment Control - Low Pin Count Input / Output | |
5 | * | |
6 | * (c) Copyright 2007 Oliver Schuster <olivers137@aol.com> | |
7 | * | |
8 | * Based on softdog.c by Alan Cox, | |
9 | * 83977f_wdt.c by Jose Goncalves, | |
10 | * it87.c by Chris Gauthron, Jean Delvare | |
11 | * | |
12 | * Data-sheets: Publicly available at the ITE website | |
13 | * http://www.ite.com.tw/ | |
14 | * | |
15 | * Support of the watchdog timers, which are available on | |
cddda07c GR |
16 | * IT8607, IT8620, IT8622, IT8625, IT8628, IT8655, IT8665, IT8686, |
17 | * IT8702, IT8712, IT8716, IT8718, IT8720, IT8721, IT8726, IT8728, | |
c113739c | 18 | * IT8772, IT8783 and IT8784. |
e1fee94f OS |
19 | */ |
20 | ||
27c766aa JP |
21 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
22 | ||
1123c514 GR |
23 | #include <linux/init.h> |
24 | #include <linux/io.h> | |
25 | #include <linux/kernel.h> | |
e1fee94f OS |
26 | #include <linux/module.h> |
27 | #include <linux/moduleparam.h> | |
28 | #include <linux/types.h> | |
e1fee94f | 29 | #include <linux/watchdog.h> |
e1fee94f | 30 | |
e1fee94f | 31 | #define WATCHDOG_NAME "IT87 WDT" |
e1fee94f OS |
32 | |
33 | /* Defaults for Module Parameter */ | |
5f3b2756 | 34 | #define DEFAULT_TIMEOUT 60 |
e1fee94f OS |
35 | #define DEFAULT_TESTMODE 0 |
36 | #define DEFAULT_NOWAYOUT WATCHDOG_NOWAYOUT | |
37 | ||
38 | /* IO Ports */ | |
39 | #define REG 0x2e | |
40 | #define VAL 0x2f | |
41 | ||
42 | /* Logical device Numbers LDN */ | |
43 | #define GPIO 0x07 | |
e1fee94f OS |
44 | |
45 | /* Configuration Registers and Functions */ | |
46 | #define LDNREG 0x07 | |
47 | #define CHIPID 0x20 | |
5f3b2756 | 48 | #define CHIPREV 0x22 |
e1fee94f OS |
49 | |
50 | /* Chip Id numbers */ | |
51 | #define NO_DEV_ID 0xffff | |
cddda07c | 52 | #define IT8607_ID 0x8607 |
06716128 | 53 | #define IT8620_ID 0x8620 |
cddda07c GR |
54 | #define IT8622_ID 0x8622 |
55 | #define IT8625_ID 0x8625 | |
56 | #define IT8628_ID 0x8628 | |
57 | #define IT8655_ID 0x8655 | |
58 | #define IT8665_ID 0x8665 | |
59 | #define IT8686_ID 0x8686 | |
dfb0b8ea | 60 | #define IT8702_ID 0x8702 |
e1fee94f OS |
61 | #define IT8705_ID 0x8705 |
62 | #define IT8712_ID 0x8712 | |
63 | #define IT8716_ID 0x8716 | |
64 | #define IT8718_ID 0x8718 | |
ee3e9658 | 65 | #define IT8720_ID 0x8720 |
4bc30272 | 66 | #define IT8721_ID 0x8721 |
e1fee94f | 67 | #define IT8726_ID 0x8726 /* the data sheet suggest wrongly 0x8716 */ |
198ca015 | 68 | #define IT8728_ID 0x8728 |
beaabe0e | 69 | #define IT8772_ID 0x8772 |
f83918fb | 70 | #define IT8783_ID 0x8783 |
c113739c | 71 | #define IT8784_ID 0x8784 |
6ae58eec | 72 | #define IT8786_ID 0x8786 |
e1fee94f OS |
73 | |
74 | /* GPIO Configuration Registers LDN=0x07 */ | |
5f3b2756 | 75 | #define WDTCTRL 0x71 |
e1fee94f OS |
76 | #define WDTCFG 0x72 |
77 | #define WDTVALLSB 0x73 | |
78 | #define WDTVALMSB 0x74 | |
79 | ||
e1fee94f OS |
80 | /* GPIO Bits WDTCFG */ |
81 | #define WDT_TOV1 0x80 | |
82 | #define WDT_KRST 0x40 | |
83 | #define WDT_TOVE 0x20 | |
4bc30272 | 84 | #define WDT_PWROK 0x10 /* not in it8721 */ |
e1fee94f OS |
85 | #define WDT_INT_MASK 0x0f |
86 | ||
893dc8b5 | 87 | static unsigned int max_units, chip_type; |
e1fee94f | 88 | |
1d7b8039 | 89 | static unsigned int timeout = DEFAULT_TIMEOUT; |
893dc8b5 GR |
90 | static int testmode = DEFAULT_TESTMODE; |
91 | static bool nowayout = DEFAULT_NOWAYOUT; | |
92 | ||
e1fee94f OS |
93 | module_param(timeout, int, 0); |
94 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, default=" | |
95 | __MODULE_STRING(DEFAULT_TIMEOUT)); | |
96 | module_param(testmode, int, 0); | |
97 | MODULE_PARM_DESC(testmode, "Watchdog test mode (1 = no reboot), default=" | |
98 | __MODULE_STRING(DEFAULT_TESTMODE)); | |
86a1e189 | 99 | module_param(nowayout, bool, 0); |
e1fee94f OS |
100 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started, default=" |
101 | __MODULE_STRING(WATCHDOG_NOWAYOUT)); | |
102 | ||
103 | /* Superio Chip */ | |
104 | ||
a134b825 | 105 | static inline int superio_enter(void) |
e1fee94f | 106 | { |
a134b825 NG |
107 | /* |
108 | * Try to reserve REG and REG + 1 for exclusive access. | |
109 | */ | |
110 | if (!request_muxed_region(REG, 2, WATCHDOG_NAME)) | |
111 | return -EBUSY; | |
112 | ||
e1fee94f OS |
113 | outb(0x87, REG); |
114 | outb(0x01, REG); | |
115 | outb(0x55, REG); | |
116 | outb(0x55, REG); | |
a134b825 | 117 | return 0; |
e1fee94f OS |
118 | } |
119 | ||
120 | static inline void superio_exit(void) | |
121 | { | |
122 | outb(0x02, REG); | |
123 | outb(0x02, VAL); | |
a134b825 | 124 | release_region(REG, 2); |
e1fee94f OS |
125 | } |
126 | ||
127 | static inline void superio_select(int ldn) | |
128 | { | |
129 | outb(LDNREG, REG); | |
130 | outb(ldn, VAL); | |
131 | } | |
132 | ||
133 | static inline int superio_inb(int reg) | |
134 | { | |
135 | outb(reg, REG); | |
136 | return inb(VAL); | |
137 | } | |
138 | ||
139 | static inline void superio_outb(int val, int reg) | |
140 | { | |
143a2e54 WVS |
141 | outb(reg, REG); |
142 | outb(val, VAL); | |
e1fee94f OS |
143 | } |
144 | ||
145 | static inline int superio_inw(int reg) | |
146 | { | |
147 | int val; | |
148 | outb(reg++, REG); | |
149 | val = inb(VAL) << 8; | |
150 | outb(reg, REG); | |
151 | val |= inb(VAL); | |
152 | return val; | |
153 | } | |
154 | ||
dfb0b8ea | 155 | /* Internal function, should be called after superio_select(GPIO) */ |
893dc8b5 | 156 | static void _wdt_update_timeout(unsigned int t) |
dfb0b8ea | 157 | { |
4bc30272 | 158 | unsigned char cfg = WDT_KRST; |
dfb0b8ea OZ |
159 | |
160 | if (testmode) | |
161 | cfg = 0; | |
162 | ||
893dc8b5 | 163 | if (t <= max_units) |
dfb0b8ea OZ |
164 | cfg |= WDT_TOV1; |
165 | else | |
893dc8b5 | 166 | t /= 60; |
dfb0b8ea | 167 | |
4bc30272 HT |
168 | if (chip_type != IT8721_ID) |
169 | cfg |= WDT_PWROK; | |
170 | ||
dfb0b8ea | 171 | superio_outb(cfg, WDTCFG); |
893dc8b5 | 172 | superio_outb(t, WDTVALLSB); |
dfb0b8ea | 173 | if (max_units > 255) |
893dc8b5 | 174 | superio_outb(t >> 8, WDTVALMSB); |
dfb0b8ea OZ |
175 | } |
176 | ||
893dc8b5 | 177 | static int wdt_update_timeout(unsigned int t) |
1d7b8039 GR |
178 | { |
179 | int ret; | |
180 | ||
181 | ret = superio_enter(); | |
182 | if (ret) | |
183 | return ret; | |
184 | ||
185 | superio_select(GPIO); | |
893dc8b5 | 186 | _wdt_update_timeout(t); |
1d7b8039 GR |
187 | superio_exit(); |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
dfb0b8ea OZ |
192 | static int wdt_round_time(int t) |
193 | { | |
194 | t += 59; | |
195 | t -= t % 60; | |
196 | return t; | |
197 | } | |
198 | ||
e1fee94f OS |
199 | /* watchdog timer handling */ |
200 | ||
1d7b8039 | 201 | static int wdt_start(struct watchdog_device *wdd) |
e1fee94f | 202 | { |
893dc8b5 | 203 | return wdt_update_timeout(wdd->timeout); |
e1fee94f OS |
204 | } |
205 | ||
1d7b8039 | 206 | static int wdt_stop(struct watchdog_device *wdd) |
e1fee94f | 207 | { |
893dc8b5 | 208 | return wdt_update_timeout(0); |
e1fee94f OS |
209 | } |
210 | ||
211 | /** | |
212 | * wdt_set_timeout - set a new timeout value with watchdog ioctl | |
213 | * @t: timeout value in seconds | |
214 | * | |
dfb0b8ea OZ |
215 | * The hardware device has a 8 or 16 bit watchdog timer (depends on |
216 | * chip version) that can be configured to count seconds or minutes. | |
e1fee94f OS |
217 | * |
218 | * Used within WDIOC_SETTIMEOUT watchdog device ioctl. | |
219 | */ | |
220 | ||
1d7b8039 | 221 | static int wdt_set_timeout(struct watchdog_device *wdd, unsigned int t) |
e1fee94f | 222 | { |
1d7b8039 | 223 | int ret = 0; |
e1fee94f | 224 | |
dfb0b8ea | 225 | if (t > max_units) |
1d7b8039 | 226 | t = wdt_round_time(t); |
e1fee94f | 227 | |
1d7b8039 | 228 | wdd->timeout = t; |
e1fee94f | 229 | |
1d7b8039 | 230 | if (watchdog_hw_running(wdd)) |
893dc8b5 | 231 | ret = wdt_update_timeout(t); |
e1fee94f | 232 | |
1d7b8039 | 233 | return ret; |
e1fee94f OS |
234 | } |
235 | ||
42747d71 | 236 | static const struct watchdog_info ident = { |
e1fee94f | 237 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, |
1d7b8039 | 238 | .firmware_version = 1, |
e1fee94f OS |
239 | .identity = WATCHDOG_NAME, |
240 | }; | |
241 | ||
2211a8dc | 242 | static const struct watchdog_ops wdt_ops = { |
1d7b8039 GR |
243 | .owner = THIS_MODULE, |
244 | .start = wdt_start, | |
245 | .stop = wdt_stop, | |
1d7b8039 GR |
246 | .set_timeout = wdt_set_timeout, |
247 | }; | |
e1fee94f | 248 | |
1d7b8039 GR |
249 | static struct watchdog_device wdt_dev = { |
250 | .info = &ident, | |
251 | .ops = &wdt_ops, | |
252 | .min_timeout = 1, | |
253 | }; | |
e1fee94f | 254 | |
e1fee94f OS |
255 | static int __init it87_wdt_init(void) |
256 | { | |
e1fee94f | 257 | u8 chip_rev; |
893dc8b5 | 258 | int rc; |
dfb0b8ea | 259 | |
a134b825 NG |
260 | rc = superio_enter(); |
261 | if (rc) | |
262 | return rc; | |
263 | ||
e1fee94f OS |
264 | chip_type = superio_inw(CHIPID); |
265 | chip_rev = superio_inb(CHIPREV) & 0x0f; | |
266 | superio_exit(); | |
e1fee94f OS |
267 | |
268 | switch (chip_type) { | |
dfb0b8ea OZ |
269 | case IT8702_ID: |
270 | max_units = 255; | |
271 | break; | |
272 | case IT8712_ID: | |
273 | max_units = (chip_rev < 8) ? 255 : 65535; | |
274 | break; | |
e1fee94f | 275 | case IT8716_ID: |
e1fee94f | 276 | case IT8726_ID: |
dfb0b8ea | 277 | max_units = 65535; |
e1fee94f | 278 | break; |
cddda07c | 279 | case IT8607_ID: |
06716128 | 280 | case IT8620_ID: |
cddda07c GR |
281 | case IT8622_ID: |
282 | case IT8625_ID: | |
283 | case IT8628_ID: | |
284 | case IT8655_ID: | |
285 | case IT8665_ID: | |
286 | case IT8686_ID: | |
ee3e9658 OZ |
287 | case IT8718_ID: |
288 | case IT8720_ID: | |
4bc30272 | 289 | case IT8721_ID: |
198ca015 | 290 | case IT8728_ID: |
beaabe0e | 291 | case IT8772_ID: |
f83918fb | 292 | case IT8783_ID: |
c113739c | 293 | case IT8784_ID: |
6ae58eec | 294 | case IT8786_ID: |
dfb0b8ea | 295 | max_units = 65535; |
ee3e9658 | 296 | break; |
e1fee94f | 297 | case IT8705_ID: |
27c766aa | 298 | pr_err("Unsupported Chip found, Chip %04x Revision %02x\n", |
e1fee94f OS |
299 | chip_type, chip_rev); |
300 | return -ENODEV; | |
301 | case NO_DEV_ID: | |
27c766aa | 302 | pr_err("no device\n"); |
e1fee94f OS |
303 | return -ENODEV; |
304 | default: | |
27c766aa | 305 | pr_err("Unknown Chip found, Chip %04x Revision %04x\n", |
e1fee94f OS |
306 | chip_type, chip_rev); |
307 | return -ENODEV; | |
308 | } | |
309 | ||
a134b825 NG |
310 | rc = superio_enter(); |
311 | if (rc) | |
312 | return rc; | |
e1fee94f OS |
313 | |
314 | superio_select(GPIO); | |
315 | superio_outb(WDT_TOV1, WDTCFG); | |
316 | superio_outb(0x00, WDTCTRL); | |
893dc8b5 | 317 | superio_exit(); |
e1fee94f | 318 | |
dfb0b8ea | 319 | if (timeout < 1 || timeout > max_units * 60) { |
e1fee94f | 320 | timeout = DEFAULT_TIMEOUT; |
27c766aa JP |
321 | pr_warn("Timeout value out of range, use default %d sec\n", |
322 | DEFAULT_TIMEOUT); | |
e1fee94f OS |
323 | } |
324 | ||
dfb0b8ea OZ |
325 | if (timeout > max_units) |
326 | timeout = wdt_round_time(timeout); | |
327 | ||
1d7b8039 GR |
328 | wdt_dev.timeout = timeout; |
329 | wdt_dev.max_timeout = max_units * 60; | |
330 | ||
1123c514 | 331 | watchdog_stop_on_reboot(&wdt_dev); |
1d7b8039 GR |
332 | rc = watchdog_register_device(&wdt_dev); |
333 | if (rc) { | |
334 | pr_err("Cannot register watchdog device (err=%d)\n", rc); | |
1123c514 | 335 | return rc; |
1d7b8039 GR |
336 | } |
337 | ||
893dc8b5 GR |
338 | pr_info("Chip IT%04x revision %d initialized. timeout=%d sec (nowayout=%d testmode=%d)\n", |
339 | chip_type, chip_rev, timeout, nowayout, testmode); | |
e1fee94f OS |
340 | |
341 | return 0; | |
e1fee94f OS |
342 | } |
343 | ||
344 | static void __exit it87_wdt_exit(void) | |
345 | { | |
1d7b8039 | 346 | watchdog_unregister_device(&wdt_dev); |
e1fee94f OS |
347 | } |
348 | ||
349 | module_init(it87_wdt_init); | |
350 | module_exit(it87_wdt_exit); | |
351 | ||
352 | MODULE_AUTHOR("Oliver Schuster"); | |
353 | MODULE_DESCRIPTION("Hardware Watchdog Device Driver for IT87xx EC-LPC I/O"); | |
354 | MODULE_LICENSE("GPL"); |