Commit | Line | Data |
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bb2fd8a8 WS |
1 | /* |
2 | * Watchdog driver for IMX2 and later processors | |
3 | * | |
4 | * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de> | |
1a9c5efa | 5 | * Copyright (C) 2014 Freescale Semiconductor, Inc. |
bb2fd8a8 WS |
6 | * |
7 | * some parts adapted by similar drivers from Darius Augulis and Vladimir | |
8 | * Zapolskiy, additional improvements by Wim Van Sebroeck. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * NOTE: MX1 has a slightly different Watchdog than MX2 and later: | |
15 | * | |
16 | * MX1: MX2+: | |
17 | * ---- ----- | |
18 | * Registers: 32-bit 16-bit | |
19 | * Stopable timer: Yes No | |
20 | * Need to enable clk: No Yes | |
21 | * Halt on suspend: Manual Can be automatic | |
22 | */ | |
23 | ||
30cb042a | 24 | #include <linux/clk.h> |
bb2fd8a8 | 25 | #include <linux/init.h> |
30cb042a XL |
26 | #include <linux/io.h> |
27 | #include <linux/jiffies.h> | |
bb2fd8a8 | 28 | #include <linux/kernel.h> |
bb2fd8a8 WS |
29 | #include <linux/module.h> |
30 | #include <linux/moduleparam.h> | |
f728f4bf | 31 | #include <linux/of_address.h> |
bb2fd8a8 | 32 | #include <linux/platform_device.h> |
a7977003 | 33 | #include <linux/regmap.h> |
bb2fd8a8 | 34 | #include <linux/timer.h> |
30cb042a | 35 | #include <linux/watchdog.h> |
bb2fd8a8 WS |
36 | |
37 | #define DRIVER_NAME "imx2-wdt" | |
38 | ||
39 | #define IMX2_WDT_WCR 0x00 /* Control Register */ | |
40 | #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */ | |
41 | #define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */ | |
42 | #define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */ | |
1a9c5efa | 43 | #define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */ |
bb2fd8a8 WS |
44 | |
45 | #define IMX2_WDT_WSR 0x02 /* Service Register */ | |
46 | #define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */ | |
47 | #define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */ | |
48 | ||
474ef121 OS |
49 | #define IMX2_WDT_WRSR 0x04 /* Reset Status Register */ |
50 | #define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */ | |
51 | ||
bb2fd8a8 WS |
52 | #define IMX2_WDT_MAX_TIME 128 |
53 | #define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */ | |
54 | ||
55 | #define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8) | |
56 | ||
faad5de0 | 57 | struct imx2_wdt_device { |
bb2fd8a8 | 58 | struct clk *clk; |
a7977003 | 59 | struct regmap *regmap; |
bb2fd8a8 | 60 | struct timer_list timer; /* Pings the watchdog when closed */ |
faad5de0 AG |
61 | struct watchdog_device wdog; |
62 | }; | |
bb2fd8a8 | 63 | |
86a1e189 WVS |
64 | static bool nowayout = WATCHDOG_NOWAYOUT; |
65 | module_param(nowayout, bool, 0); | |
bb2fd8a8 WS |
66 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
67 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
68 | ||
69 | ||
70 | static unsigned timeout = IMX2_WDT_DEFAULT_TIME; | |
71 | module_param(timeout, uint, 0); | |
72 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default=" | |
73 | __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")"); | |
74 | ||
75 | static const struct watchdog_info imx2_wdt_info = { | |
76 | .identity = "imx2+ watchdog", | |
77 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | |
78 | }; | |
79 | ||
faad5de0 | 80 | static inline void imx2_wdt_setup(struct watchdog_device *wdog) |
bb2fd8a8 | 81 | { |
faad5de0 | 82 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); |
a7977003 XL |
83 | u32 val; |
84 | ||
faad5de0 | 85 | regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); |
bb2fd8a8 | 86 | |
1a9c5efa AH |
87 | /* Suspend timer in low power mode, write once-only */ |
88 | val |= IMX2_WDT_WCR_WDZST; | |
bb2fd8a8 WS |
89 | /* Strip the old watchdog Time-Out value */ |
90 | val &= ~IMX2_WDT_WCR_WT; | |
91 | /* Generate reset if WDOG times out */ | |
92 | val &= ~IMX2_WDT_WCR_WRE; | |
93 | /* Keep Watchdog Disabled */ | |
94 | val &= ~IMX2_WDT_WCR_WDE; | |
95 | /* Set the watchdog's Time-Out value */ | |
faad5de0 | 96 | val |= WDOG_SEC_TO_COUNT(wdog->timeout); |
bb2fd8a8 | 97 | |
faad5de0 | 98 | regmap_write(wdev->regmap, IMX2_WDT_WCR, val); |
bb2fd8a8 WS |
99 | |
100 | /* enable the watchdog */ | |
101 | val |= IMX2_WDT_WCR_WDE; | |
faad5de0 | 102 | regmap_write(wdev->regmap, IMX2_WDT_WCR, val); |
bb2fd8a8 WS |
103 | } |
104 | ||
faad5de0 | 105 | static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev) |
bb2fd8a8 | 106 | { |
faad5de0 | 107 | u32 val; |
bb2fd8a8 | 108 | |
faad5de0 AG |
109 | regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); |
110 | ||
111 | return val & IMX2_WDT_WCR_WDE; | |
bb2fd8a8 WS |
112 | } |
113 | ||
faad5de0 | 114 | static int imx2_wdt_ping(struct watchdog_device *wdog) |
bb2fd8a8 | 115 | { |
faad5de0 | 116 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); |
bb2fd8a8 | 117 | |
faad5de0 AG |
118 | regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1); |
119 | regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2); | |
120 | return 0; | |
bb2fd8a8 WS |
121 | } |
122 | ||
faad5de0 | 123 | static void imx2_wdt_timer_ping(unsigned long arg) |
bb2fd8a8 | 124 | { |
faad5de0 AG |
125 | struct watchdog_device *wdog = (struct watchdog_device *)arg; |
126 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); | |
127 | ||
128 | /* ping it every wdog->timeout / 2 seconds to prevent reboot */ | |
129 | imx2_wdt_ping(wdog); | |
130 | mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2); | |
bb2fd8a8 WS |
131 | } |
132 | ||
faad5de0 AG |
133 | static int imx2_wdt_set_timeout(struct watchdog_device *wdog, |
134 | unsigned int new_timeout) | |
bb2fd8a8 | 135 | { |
faad5de0 AG |
136 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); |
137 | ||
138 | regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT, | |
a7977003 | 139 | WDOG_SEC_TO_COUNT(new_timeout)); |
faad5de0 | 140 | return 0; |
bb2fd8a8 WS |
141 | } |
142 | ||
faad5de0 | 143 | static int imx2_wdt_start(struct watchdog_device *wdog) |
bb2fd8a8 | 144 | { |
faad5de0 | 145 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); |
bb2fd8a8 | 146 | |
faad5de0 AG |
147 | if (imx2_wdt_is_running(wdev)) { |
148 | /* delete the timer that pings the watchdog after close */ | |
149 | del_timer_sync(&wdev->timer); | |
150 | imx2_wdt_set_timeout(wdog, wdog->timeout); | |
151 | } else | |
152 | imx2_wdt_setup(wdog); | |
153 | ||
154 | return imx2_wdt_ping(wdog); | |
bb2fd8a8 WS |
155 | } |
156 | ||
faad5de0 | 157 | static int imx2_wdt_stop(struct watchdog_device *wdog) |
bb2fd8a8 | 158 | { |
faad5de0 AG |
159 | /* |
160 | * We don't need a clk_disable, it cannot be disabled once started. | |
161 | * We use a timer to ping the watchdog while /dev/watchdog is closed | |
162 | */ | |
163 | imx2_wdt_timer_ping((unsigned long)wdog); | |
bb2fd8a8 WS |
164 | return 0; |
165 | } | |
166 | ||
faad5de0 | 167 | static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog) |
bb2fd8a8 | 168 | { |
faad5de0 | 169 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); |
bb2fd8a8 | 170 | |
faad5de0 AG |
171 | if (imx2_wdt_is_running(wdev)) { |
172 | imx2_wdt_set_timeout(wdog, wdog->timeout); | |
173 | imx2_wdt_timer_ping((unsigned long)wdog); | |
bb2fd8a8 WS |
174 | } |
175 | } | |
176 | ||
faad5de0 | 177 | static struct watchdog_ops imx2_wdt_ops = { |
bb2fd8a8 | 178 | .owner = THIS_MODULE, |
faad5de0 AG |
179 | .start = imx2_wdt_start, |
180 | .stop = imx2_wdt_stop, | |
181 | .ping = imx2_wdt_ping, | |
182 | .set_timeout = imx2_wdt_set_timeout, | |
bb2fd8a8 WS |
183 | }; |
184 | ||
a7977003 XL |
185 | static struct regmap_config imx2_wdt_regmap_config = { |
186 | .reg_bits = 16, | |
187 | .reg_stride = 2, | |
188 | .val_bits = 16, | |
189 | .max_register = 0x8, | |
190 | }; | |
191 | ||
bb2fd8a8 WS |
192 | static int __init imx2_wdt_probe(struct platform_device *pdev) |
193 | { | |
f728f4bf | 194 | struct device_node *np = pdev->dev.of_node; |
faad5de0 AG |
195 | struct imx2_wdt_device *wdev; |
196 | struct watchdog_device *wdog; | |
bb2fd8a8 | 197 | struct resource *res; |
a7977003 | 198 | void __iomem *base; |
f728f4bf | 199 | bool big_endian; |
a7977003 | 200 | int ret; |
faad5de0 AG |
201 | u32 val; |
202 | ||
203 | wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL); | |
204 | if (!wdev) | |
205 | return -ENOMEM; | |
bb2fd8a8 | 206 | |
f728f4bf XL |
207 | big_endian = of_property_read_bool(np, "big-endian"); |
208 | if (big_endian) | |
209 | imx2_wdt_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG; | |
210 | ||
bb2fd8a8 | 211 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a7977003 XL |
212 | base = devm_ioremap_resource(&pdev->dev, res); |
213 | if (IS_ERR(base)) | |
214 | return PTR_ERR(base); | |
215 | ||
faad5de0 AG |
216 | wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, |
217 | &imx2_wdt_regmap_config); | |
218 | if (IS_ERR(wdev->regmap)) { | |
a7977003 | 219 | dev_err(&pdev->dev, "regmap init failed\n"); |
faad5de0 | 220 | return PTR_ERR(wdev->regmap); |
a7977003 | 221 | } |
bb2fd8a8 | 222 | |
faad5de0 AG |
223 | wdev->clk = devm_clk_get(&pdev->dev, NULL); |
224 | if (IS_ERR(wdev->clk)) { | |
bb2fd8a8 | 225 | dev_err(&pdev->dev, "can't get Watchdog clock\n"); |
faad5de0 | 226 | return PTR_ERR(wdev->clk); |
bb2fd8a8 WS |
227 | } |
228 | ||
faad5de0 AG |
229 | wdog = &wdev->wdog; |
230 | wdog->info = &imx2_wdt_info; | |
231 | wdog->ops = &imx2_wdt_ops; | |
232 | wdog->min_timeout = 1; | |
233 | wdog->max_timeout = IMX2_WDT_MAX_TIME; | |
bb2fd8a8 | 234 | |
faad5de0 | 235 | clk_prepare_enable(wdev->clk); |
bb2fd8a8 | 236 | |
faad5de0 AG |
237 | regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val); |
238 | wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0; | |
bb2fd8a8 | 239 | |
faad5de0 AG |
240 | wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME); |
241 | if (wdog->timeout != timeout) | |
242 | dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n", | |
243 | timeout, wdog->timeout); | |
244 | ||
245 | platform_set_drvdata(pdev, wdog); | |
246 | watchdog_set_drvdata(wdog, wdev); | |
247 | watchdog_set_nowayout(wdog, nowayout); | |
248 | watchdog_init_timeout(wdog, timeout, &pdev->dev); | |
249 | ||
250 | setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog); | |
bb2fd8a8 | 251 | |
faad5de0 AG |
252 | imx2_wdt_ping_if_active(wdog); |
253 | ||
254 | ret = watchdog_register_device(wdog); | |
255 | if (ret) { | |
256 | dev_err(&pdev->dev, "cannot register watchdog device\n"); | |
257 | return ret; | |
258 | } | |
259 | ||
260 | dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n", | |
261 | wdog->timeout, nowayout); | |
262 | ||
263 | return 0; | |
bb2fd8a8 WS |
264 | } |
265 | ||
266 | static int __exit imx2_wdt_remove(struct platform_device *pdev) | |
267 | { | |
faad5de0 AG |
268 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
269 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); | |
bb2fd8a8 | 270 | |
faad5de0 | 271 | watchdog_unregister_device(wdog); |
bb2fd8a8 | 272 | |
faad5de0 AG |
273 | if (imx2_wdt_is_running(wdev)) { |
274 | del_timer_sync(&wdev->timer); | |
275 | imx2_wdt_ping(wdog); | |
276 | dev_crit(&pdev->dev, "Device removed: Expect reboot!\n"); | |
bdf49574 | 277 | } |
bb2fd8a8 WS |
278 | return 0; |
279 | } | |
280 | ||
281 | static void imx2_wdt_shutdown(struct platform_device *pdev) | |
282 | { | |
faad5de0 AG |
283 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
284 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); | |
285 | ||
286 | if (imx2_wdt_is_running(wdev)) { | |
287 | /* | |
288 | * We are running, we need to delete the timer but will | |
289 | * give max timeout before reboot will take place | |
290 | */ | |
291 | del_timer_sync(&wdev->timer); | |
292 | imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME); | |
293 | imx2_wdt_ping(wdog); | |
294 | dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n"); | |
bb2fd8a8 WS |
295 | } |
296 | } | |
297 | ||
f5a427ee SG |
298 | static const struct of_device_id imx2_wdt_dt_ids[] = { |
299 | { .compatible = "fsl,imx21-wdt", }, | |
300 | { /* sentinel */ } | |
301 | }; | |
813296a1 | 302 | MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids); |
f5a427ee | 303 | |
bb2fd8a8 | 304 | static struct platform_driver imx2_wdt_driver = { |
bb2fd8a8 WS |
305 | .remove = __exit_p(imx2_wdt_remove), |
306 | .shutdown = imx2_wdt_shutdown, | |
307 | .driver = { | |
308 | .name = DRIVER_NAME, | |
309 | .owner = THIS_MODULE, | |
f5a427ee | 310 | .of_match_table = imx2_wdt_dt_ids, |
bb2fd8a8 WS |
311 | }, |
312 | }; | |
313 | ||
1cb9204c | 314 | module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe); |
bb2fd8a8 WS |
315 | |
316 | MODULE_AUTHOR("Wolfram Sang"); | |
317 | MODULE_DESCRIPTION("Watchdog driver for IMX2 and later"); | |
318 | MODULE_LICENSE("GPL v2"); | |
bb2fd8a8 | 319 | MODULE_ALIAS("platform:" DRIVER_NAME); |