[linux-2.6-block.git] / drivers / watchdog / imx2_wdt.c

/*
 * Watchdog driver for IMX2 and later processors
 *
 *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
 *  Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * some parts adapted by similar drivers from Darius Augulis and Vladimir
 * Zapolskiy, additional improvements by Wim Van Sebroeck.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
 *
 *			MX1:		MX2+:
 *			----		-----
 * Registers:		32-bit		16-bit
 * Stopable timer:	Yes		No
 * Need to enable clk:	No		Yes
 * Halt on suspend:	Manual		Can be automatic
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>

#define DRIVER_NAME "imx2-wdt"

#define IMX2_WDT_WCR		0x00		/* Control Register */
#define IMX2_WDT_WCR_WT		(0xFF << 8)	/* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WDA	(1 << 5)	/* -> External Reset WDOG_B */
#define IMX2_WDT_WCR_SRS	(1 << 4)	/* -> Software Reset Signal */
#define IMX2_WDT_WCR_WRE	(1 << 3)	/* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE	(1 << 2)	/* -> Watchdog Enable */
#define IMX2_WDT_WCR_WDZST	(1 << 0)	/* -> Watchdog timer Suspend */

#define IMX2_WDT_WSR		0x02		/* Service Register */
#define IMX2_WDT_SEQ1		0x5555		/* -> service sequence 1 */
#define IMX2_WDT_SEQ2		0xAAAA		/* -> service sequence 2 */

#define IMX2_WDT_WRSR		0x04		/* Reset Status Register */
#define IMX2_WDT_WRSR_TOUT	(1 << 1)	/* -> Reset due to Timeout */

#define IMX2_WDT_WMCR		0x08		/* Misc Register */

#define IMX2_WDT_MAX_TIME	128
#define IMX2_WDT_DEFAULT_TIME	60		/* in seconds */

#define WDOG_SEC_TO_COUNT(s)	((s * 2 - 1) << 8)

struct imx2_wdt_device {
	struct clk *clk;
	struct regmap *regmap;
	struct watchdog_device wdog;
	bool ext_reset;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");


static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
				__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");

static const struct watchdog_info imx2_wdt_info = {
	.identity = "imx2+ watchdog",
	.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};

static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
			    void *data)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;

	/* Use internal reset or external - not both */
	if (wdev->ext_reset)
		wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
	else
		wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */

	/* Assert SRS signal */
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
	/*
	 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	 * written twice), we add another two writes to ensure there must be at
	 * least two writes happen in the same one 32kHz clock period.  We save
	 * the target check here, since the writes shouldn't be a huge burden
	 * for other platforms.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);

	/* wait for reset to assert... */
	mdelay(500);

	return 0;
}

static inline void imx2_wdt_setup(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	/* Suspend timer in low power mode, write once-only */
	val |= IMX2_WDT_WCR_WDZST;
	/* Strip the old watchdog Time-Out value */
	val &= ~IMX2_WDT_WCR_WT;
	/* Generate internal chip-level reset if WDOG times out */
	if (!wdev->ext_reset)
		val &= ~IMX2_WDT_WCR_WRE;
	/* Or if external-reset assert WDOG_B reset only on time-out */
	else
		val |= IMX2_WDT_WCR_WRE;
	/* Keep Watchdog Disabled */
	val &= ~IMX2_WDT_WCR_WDE;
	/* Set the watchdog's Time-Out value */
	val |= WDOG_SEC_TO_COUNT(wdog->timeout);

	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);

	/* enable the watchdog */
	val |= IMX2_WDT_WCR_WDE;
	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
}

static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
{
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	return val & IMX2_WDT_WCR_WDE;
}

static int imx2_wdt_ping(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	return 0;
}

static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int new_timeout)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	wdog->timeout = new_timeout;

	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
			   WDOG_SEC_TO_COUNT(new_timeout));
	return 0;
}

static int imx2_wdt_start(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev))
		imx2_wdt_set_timeout(wdog, wdog->timeout);
	else
		imx2_wdt_setup(wdog);

	set_bit(WDOG_HW_RUNNING, &wdog->status);

	return imx2_wdt_ping(wdog);
}

static const struct watchdog_ops imx2_wdt_ops = {
	.owner = THIS_MODULE,
	.start = imx2_wdt_start,
	.ping = imx2_wdt_ping,
	.set_timeout = imx2_wdt_set_timeout,
	.restart = imx2_wdt_restart,
};

static const struct regmap_config imx2_wdt_regmap_config = {
	.reg_bits = 16,
	.reg_stride = 2,
	.val_bits = 16,
	.max_register = 0x8,
};

static int __init imx2_wdt_probe(struct platform_device *pdev)
{
	struct imx2_wdt_device *wdev;
	struct watchdog_device *wdog;
	struct resource *res;
	void __iomem *base;
	int ret;
	u32 val;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
						 &imx2_wdt_regmap_config);
	if (IS_ERR(wdev->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(wdev->regmap);
	}

	wdev->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdev->clk)) {
		dev_err(&pdev->dev, "can't get Watchdog clock\n");
		return PTR_ERR(wdev->clk);
	}

	wdog			= &wdev->wdog;
	wdog->info		= &imx2_wdt_info;
	wdog->ops		= &imx2_wdt_ops;
	wdog->min_timeout	= 1;
	wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
	wdog->parent		= &pdev->dev;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;

	wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
						"fsl,ext-reset-output");
	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	if (wdog->timeout != timeout)
		dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
			 timeout, wdog->timeout);

	platform_set_drvdata(pdev, wdog);
	watchdog_set_drvdata(wdog, wdev);
	watchdog_set_nowayout(wdog, nowayout);
	watchdog_set_restart_priority(wdog, 128);
	watchdog_init_timeout(wdog, timeout, &pdev->dev);

	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		set_bit(WDOG_HW_RUNNING, &wdog->status);
	}

	/*
	 * Disable the watchdog power down counter at boot. Otherwise the power
	 * down counter will pull down the #WDOG interrupt line for one clock
	 * cycle.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);

	ret = watchdog_register_device(wdog);
	if (ret) {
		dev_err(&pdev->dev, "cannot register watchdog device\n");
		goto disable_clk;
	}

	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
		 wdog->timeout, nowayout);

	return 0;

disable_clk:
	clk_disable_unprepare(wdev->clk);
	return ret;
}

static int __exit imx2_wdt_remove(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	watchdog_unregister_device(wdog);

	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
	}
	return 0;
}

static void imx2_wdt_shutdown(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/*
		 * We are running, configure max timeout before reboot
		 * will take place.
		 */
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
	}
}

#ifdef CONFIG_PM_SLEEP
/* Disable watchdog if it is active or non-active but still running */
static int imx2_wdt_suspend(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* The watchdog IP block is running */
	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
	}

	clk_disable_unprepare(wdev->clk);

	return 0;
}

/* Enable watchdog and configure it if necessary */
static int imx2_wdt_resume(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	int ret;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
		/*
		 * If the watchdog is still active and resumes
		 * from deep sleep state, need to restart the
		 * watchdog again.
		 */
		imx2_wdt_setup(wdog);
	}
	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
			 imx2_wdt_resume);

static const struct of_device_id imx2_wdt_dt_ids[] = {
	{ .compatible = "fsl,imx21-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);

static struct platform_driver imx2_wdt_driver = {
	.remove		= __exit_p(imx2_wdt_remove),
	.shutdown	= imx2_wdt_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.pm     = &imx2_wdt_pm_ops,
		.of_match_table = imx2_wdt_dt_ids,
	},
};

module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);

MODULE_AUTHOR("Wolfram Sang");
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
bb2fd8a8 WS	1	/*
	2	* Watchdog driver for IMX2 and later processors
	3	*
	4	* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
1a9c5efa	5	* Copyright (C) 2014 Freescale Semiconductor, Inc.
bb2fd8a8 WS	6	*
	7	* some parts adapted by similar drivers from Darius Augulis and Vladimir
	8	* Zapolskiy, additional improvements by Wim Van Sebroeck.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
	15	*
	16	* MX1: MX2+:
	17	* ---- -----
	18	* Registers: 32-bit 16-bit
	19	* Stopable timer: Yes No
	20	* Need to enable clk: No Yes
	21	* Halt on suspend: Manual Can be automatic
	22	*/
	23
30cb042a	24	#include <linux/clk.h>
334a9d81	25	#include <linux/delay.h>
bb2fd8a8	26	#include <linux/init.h>
30cb042a	27	#include <linux/io.h>
bb2fd8a8	28	#include <linux/kernel.h>
bb2fd8a8 WS	29	#include <linux/module.h>
bb2fd8a8 WS	30	#include <linux/moduleparam.h>
f728f4bf	31	#include <linux/of_address.h>
bb2fd8a8	32	#include <linux/platform_device.h>
a7977003	33	#include <linux/regmap.h>
30cb042a	34	#include <linux/watchdog.h>
bb2fd8a8 WS	35
	36	#define DRIVER_NAME "imx2-wdt"
	37
	38	#define IMX2_WDT_WCR 0x00 /* Control Register */
	39	#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
bc677ff4 TH	40	#define IMX2_WDT_WCR_WDA (1 << 5) /* -> External Reset WDOG_B */
bc677ff4 TH	41	#define IMX2_WDT_WCR_SRS (1 << 4) /* -> Software Reset Signal */
bb2fd8a8 WS	42	#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
bb2fd8a8 WS	43	#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
1a9c5efa	44	#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
bb2fd8a8 WS	45
	46	#define IMX2_WDT_WSR 0x02 /* Service Register */
	47	#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
	48	#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
	49
474ef121 OS	50	#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
	51	#define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
	52
5fe65ce7 MP	53	#define IMX2_WDT_WMCR 0x08 /* Misc Register */
5fe65ce7 MP	54
bb2fd8a8 WS	55	#define IMX2_WDT_MAX_TIME 128
	56	#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
	57
	58	#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
	59
faad5de0	60	struct imx2_wdt_device {
bb2fd8a8	61	struct clk *clk;
a7977003	62	struct regmap *regmap;
faad5de0	63	struct watchdog_device wdog;
bc677ff4	64	bool ext_reset;
faad5de0	65	};
bb2fd8a8	66
86a1e189 WVS	67	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	68	module_param(nowayout, bool, 0);
bb2fd8a8 WS	69	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	70	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	71
	72
	73	static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
	74	module_param(timeout, uint, 0);
	75	MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
	76	__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
	77
	78	static const struct watchdog_info imx2_wdt_info = {
	79	.identity = "imx2+ watchdog",
	80	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE,
	81	};
	82
4d8b229d GR	83	static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
4d8b229d GR	84	void *data)
334a9d81	85	{
2d9d2475	86	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
334a9d81	87	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
2d9d2475	88
bc677ff4 TH	89	/* Use internal reset or external - not both */
	90	if (wdev->ext_reset)
	91	wcr_enable \|= IMX2_WDT_WCR_SRS; /* do not assert int reset */
	92	else
	93	wcr_enable \|= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
	94
334a9d81	95	/* Assert SRS signal */
9493c0d8	96	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
334a9d81 JL	97	/*
	98	* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	99	* written twice), we add another two writes to ensure there must be at
	100	* least two writes happen in the same one 32kHz clock period. We save
	101	* the target check here, since the writes shouldn't be a huge burden
	102	* for other platforms.
	103	*/
9493c0d8 FE	104	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
9493c0d8 FE	105	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
334a9d81 JL	106
	107	/* wait for reset to assert... */
	108	mdelay(500);
	109
2d9d2475	110	return 0;
334a9d81 JL	111	}
334a9d81 JL	112
faad5de0	113	static inline void imx2_wdt_setup(struct watchdog_device *wdog)
bb2fd8a8	114	{
faad5de0	115	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
a7977003 XL	116	u32 val;
a7977003 XL	117
faad5de0	118	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
bb2fd8a8	119
1a9c5efa AH	120	/* Suspend timer in low power mode, write once-only */
1a9c5efa AH	121	val \|= IMX2_WDT_WCR_WDZST;
bb2fd8a8 WS	122	/* Strip the old watchdog Time-Out value */
bb2fd8a8 WS	123	val &= ~IMX2_WDT_WCR_WT;
bc677ff4 TH	124	/* Generate internal chip-level reset if WDOG times out */
	125	if (!wdev->ext_reset)
	126	val &= ~IMX2_WDT_WCR_WRE;
	127	/* Or if external-reset assert WDOG_B reset only on time-out */
	128	else
	129	val \|= IMX2_WDT_WCR_WRE;
bb2fd8a8 WS	130	/* Keep Watchdog Disabled */
	131	val &= ~IMX2_WDT_WCR_WDE;
	132	/* Set the watchdog's Time-Out value */
faad5de0	133	val \|= WDOG_SEC_TO_COUNT(wdog->timeout);
bb2fd8a8	134
faad5de0	135	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	136
	137	/* enable the watchdog */
	138	val \|= IMX2_WDT_WCR_WDE;
faad5de0	139	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	140	}
bb2fd8a8 WS	141
faad5de0	142	static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
bb2fd8a8	143	{
faad5de0	144	u32 val;
bb2fd8a8	145
faad5de0 AG	146	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
	147
	148	return val & IMX2_WDT_WCR_WDE;
bb2fd8a8 WS	149	}
bb2fd8a8 WS	150
faad5de0	151	static int imx2_wdt_ping(struct watchdog_device *wdog)
bb2fd8a8	152	{
faad5de0	153	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	154
faad5de0 AG	155	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	156	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	157	return 0;
bb2fd8a8 WS	158	}
bb2fd8a8 WS	159
faad5de0 AG	160	static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
faad5de0 AG	161	unsigned int new_timeout)
bb2fd8a8	162	{
faad5de0 AG	163	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
faad5de0 AG	164
30dd4a8f MG	165	wdog->timeout = new_timeout;
30dd4a8f MG	166
faad5de0	167	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
a7977003	168	WDOG_SEC_TO_COUNT(new_timeout));
faad5de0	169	return 0;
bb2fd8a8 WS	170	}
bb2fd8a8 WS	171
faad5de0	172	static int imx2_wdt_start(struct watchdog_device *wdog)
bb2fd8a8	173	{
faad5de0	174	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	175
11d7aba9	176	if (imx2_wdt_is_running(wdev))
faad5de0	177	imx2_wdt_set_timeout(wdog, wdog->timeout);
11d7aba9	178	else
faad5de0 AG	179	imx2_wdt_setup(wdog);
faad5de0 AG	180
11d7aba9	181	set_bit(WDOG_HW_RUNNING, &wdog->status);
bb2fd8a8	182
11d7aba9	183	return imx2_wdt_ping(wdog);
bb2fd8a8 WS	184	}
bb2fd8a8 WS	185
4bd8ce33	186	static const struct watchdog_ops imx2_wdt_ops = {
bb2fd8a8	187	.owner = THIS_MODULE,
faad5de0	188	.start = imx2_wdt_start,
faad5de0 AG	189	.ping = imx2_wdt_ping,
faad5de0 AG	190	.set_timeout = imx2_wdt_set_timeout,
2d9d2475	191	.restart = imx2_wdt_restart,
bb2fd8a8 WS	192	};
bb2fd8a8 WS	193
4bd8ce33	194	static const struct regmap_config imx2_wdt_regmap_config = {
a7977003 XL	195	.reg_bits = 16,
	196	.reg_stride = 2,
	197	.val_bits = 16,
	198	.max_register = 0x8,
	199	};
	200
bb2fd8a8 WS	201	static int __init imx2_wdt_probe(struct platform_device *pdev)
bb2fd8a8 WS	202	{
faad5de0 AG	203	struct imx2_wdt_device *wdev;
faad5de0 AG	204	struct watchdog_device *wdog;
bb2fd8a8	205	struct resource *res;
a7977003 XL	206	void __iomem *base;
a7977003 XL	207	int ret;
faad5de0 AG	208	u32 val;
	209
	210	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	211	if (!wdev)
	212	return -ENOMEM;
bb2fd8a8 WS	213
bb2fd8a8 WS	214	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a7977003 XL	215	base = devm_ioremap_resource(&pdev->dev, res);
	216	if (IS_ERR(base))
	217	return PTR_ERR(base);
	218
faad5de0 AG	219	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
	220	&imx2_wdt_regmap_config);
	221	if (IS_ERR(wdev->regmap)) {
a7977003	222	dev_err(&pdev->dev, "regmap init failed\n");
faad5de0	223	return PTR_ERR(wdev->regmap);
a7977003	224	}
bb2fd8a8	225
faad5de0 AG	226	wdev->clk = devm_clk_get(&pdev->dev, NULL);
faad5de0 AG	227	if (IS_ERR(wdev->clk)) {
bb2fd8a8	228	dev_err(&pdev->dev, "can't get Watchdog clock\n");
faad5de0	229	return PTR_ERR(wdev->clk);
bb2fd8a8 WS	230	}
bb2fd8a8 WS	231
faad5de0 AG	232	wdog = &wdev->wdog;
	233	wdog->info = &imx2_wdt_info;
	234	wdog->ops = &imx2_wdt_ops;
	235	wdog->min_timeout = 1;
11d7aba9	236	wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
8135193c	237	wdog->parent = &pdev->dev;
bb2fd8a8	238
aefb163c FE	239	ret = clk_prepare_enable(wdev->clk);
	240	if (ret)
	241	return ret;
bb2fd8a8	242
faad5de0 AG	243	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
faad5de0 AG	244	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
bb2fd8a8	245
bc677ff4 TH	246	wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
bc677ff4 TH	247	"fsl,ext-reset-output");
faad5de0 AG	248	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	249	if (wdog->timeout != timeout)
	250	dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
	251	timeout, wdog->timeout);
	252
	253	platform_set_drvdata(pdev, wdog);
	254	watchdog_set_drvdata(wdog, wdev);
	255	watchdog_set_nowayout(wdog, nowayout);
2d9d2475	256	watchdog_set_restart_priority(wdog, 128);
faad5de0 AG	257	watchdog_init_timeout(wdog, timeout, &pdev->dev);
faad5de0 AG	258
11d7aba9 GR	259	if (imx2_wdt_is_running(wdev)) {
	260	imx2_wdt_set_timeout(wdog, wdog->timeout);
	261	set_bit(WDOG_HW_RUNNING, &wdog->status);
	262	}
faad5de0	263
5fe65ce7 MP	264	/*
	265	* Disable the watchdog power down counter at boot. Otherwise the power
	266	* down counter will pull down the #WDOG interrupt line for one clock
	267	* cycle.
	268	*/
	269	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
	270
faad5de0 AG	271	ret = watchdog_register_device(wdog);
	272	if (ret) {
	273	dev_err(&pdev->dev, "cannot register watchdog device\n");
db11cba2	274	goto disable_clk;
faad5de0 AG	275	}
	276
	277	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
	278	wdog->timeout, nowayout);
	279
	280	return 0;
db11cba2 FE	281
	282	disable_clk:
	283	clk_disable_unprepare(wdev->clk);
	284	return ret;
bb2fd8a8 WS	285	}
	286
	287	static int __exit imx2_wdt_remove(struct platform_device *pdev)
	288	{
faad5de0 AG	289	struct watchdog_device *wdog = platform_get_drvdata(pdev);
faad5de0 AG	290	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	291
faad5de0	292	watchdog_unregister_device(wdog);
bb2fd8a8	293
faad5de0	294	if (imx2_wdt_is_running(wdev)) {
faad5de0 AG	295	imx2_wdt_ping(wdog);
faad5de0 AG	296	dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
bdf49574	297	}
bb2fd8a8 WS	298	return 0;
	299	}
	300
	301	static void imx2_wdt_shutdown(struct platform_device *pdev)
	302	{
faad5de0 AG	303	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	304	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	305
	306	if (imx2_wdt_is_running(wdev)) {
	307	/*
11d7aba9 GR	308	* We are running, configure max timeout before reboot
11d7aba9 GR	309	* will take place.
faad5de0	310	*/
faad5de0 AG	311	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	312	imx2_wdt_ping(wdog);
	313	dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
bb2fd8a8 WS	314	}
	315	}
	316
aefbaf3a	317	#ifdef CONFIG_PM_SLEEP
bbd59009	318	/* Disable watchdog if it is active or non-active but still running */
aefbaf3a XL	319	static int imx2_wdt_suspend(struct device *dev)
	320	{
	321	struct watchdog_device *wdog = dev_get_drvdata(dev);
	322	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	323
bbd59009 XL	324	/* The watchdog IP block is running */
	325	if (imx2_wdt_is_running(wdev)) {
	326	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	327	imx2_wdt_ping(wdog);
bbd59009	328	}
aefbaf3a XL	329
	330	clk_disable_unprepare(wdev->clk);
	331
	332	return 0;
	333	}
	334
	335	/* Enable watchdog and configure it if necessary */
	336	static int imx2_wdt_resume(struct device *dev)
	337	{
	338	struct watchdog_device *wdog = dev_get_drvdata(dev);
	339	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
aefb163c	340	int ret;
aefbaf3a	341
aefb163c FE	342	ret = clk_prepare_enable(wdev->clk);
	343	if (ret)
	344	return ret;
aefbaf3a XL	345
aefbaf3a XL	346	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
bbd59009 XL	347	/*
	348	* If the watchdog is still active and resumes
	349	* from deep sleep state, need to restart the
	350	* watchdog again.
aefbaf3a XL	351	*/
aefbaf3a XL	352	imx2_wdt_setup(wdog);
11d7aba9 GR	353	}
11d7aba9 GR	354	if (imx2_wdt_is_running(wdev)) {
aefbaf3a XL	355	imx2_wdt_set_timeout(wdog, wdog->timeout);
aefbaf3a XL	356	imx2_wdt_ping(wdog);
aefbaf3a XL	357	}
	358
	359	return 0;
	360	}
	361	#endif
	362
	363	static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
	364	imx2_wdt_resume);
	365
f5a427ee SG	366	static const struct of_device_id imx2_wdt_dt_ids[] = {
	367	{ .compatible = "fsl,imx21-wdt", },
	368	{ /* sentinel */ }
	369	};
813296a1	370	MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
f5a427ee	371
bb2fd8a8	372	static struct platform_driver imx2_wdt_driver = {
bb2fd8a8 WS	373	.remove = __exit_p(imx2_wdt_remove),
	374	.shutdown = imx2_wdt_shutdown,
	375	.driver = {
	376	.name = DRIVER_NAME,
aefbaf3a	377	.pm = &imx2_wdt_pm_ops,
f5a427ee	378	.of_match_table = imx2_wdt_dt_ids,
bb2fd8a8 WS	379	},
	380	};
	381
1cb9204c	382	module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
bb2fd8a8 WS	383
	384	MODULE_AUTHOR("Wolfram Sang");
	385	MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
	386	MODULE_LICENSE("GPL v2");
bb2fd8a8	387	MODULE_ALIAS("platform:" DRIVER_NAME);