[linux-2.6-block.git] / drivers / watchdog / imx2_wdt.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Watchdog driver for IMX2 and later processors
 *
 *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <kernel@pengutronix.de>
 *  Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * some parts adapted by similar drivers from Darius Augulis and Vladimir
 * Zapolskiy, additional improvements by Wim Van Sebroeck.
 *
 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
 *
 *			MX1:		MX2+:
 *			----		-----
 * Registers:		32-bit		16-bit
 * Stopable timer:	Yes		No
 * Need to enable clk:	No		Yes
 * Halt on suspend:	Manual		Can be automatic
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>

#define DRIVER_NAME "imx2-wdt"

#define IMX2_WDT_WCR		0x00		/* Control Register */
#define IMX2_WDT_WCR_WT		(0xFF << 8)	/* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WDA	BIT(5)		/* -> External Reset WDOG_B */
#define IMX2_WDT_WCR_SRS	BIT(4)		/* -> Software Reset Signal */
#define IMX2_WDT_WCR_WRE	BIT(3)		/* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE	BIT(2)		/* -> Watchdog Enable */
#define IMX2_WDT_WCR_WDZST	BIT(0)		/* -> Watchdog timer Suspend */

#define IMX2_WDT_WSR		0x02		/* Service Register */
#define IMX2_WDT_SEQ1		0x5555		/* -> service sequence 1 */
#define IMX2_WDT_SEQ2		0xAAAA		/* -> service sequence 2 */

#define IMX2_WDT_WRSR		0x04		/* Reset Status Register */
#define IMX2_WDT_WRSR_TOUT	BIT(1)		/* -> Reset due to Timeout */

#define IMX2_WDT_WICR		0x06		/* Interrupt Control Register */
#define IMX2_WDT_WICR_WIE	BIT(15)		/* -> Interrupt Enable */
#define IMX2_WDT_WICR_WTIS	BIT(14)		/* -> Interrupt Status */
#define IMX2_WDT_WICR_WICT	0xFF		/* -> Interrupt Count Timeout */

#define IMX2_WDT_WMCR		0x08		/* Misc Register */

#define IMX2_WDT_MAX_TIME	128U
#define IMX2_WDT_DEFAULT_TIME	60		/* in seconds */

#define WDOG_SEC_TO_COUNT(s)	((s * 2 - 1) << 8)

struct imx2_wdt_device {
	struct clk *clk;
	struct regmap *regmap;
	struct watchdog_device wdog;
	bool ext_reset;
	bool clk_is_on;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static unsigned timeout;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
				__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");

static const struct watchdog_info imx2_wdt_info = {
	.identity = "imx2+ watchdog",
	.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};

static const struct watchdog_info imx2_wdt_pretimeout_info = {
	.identity = "imx2+ watchdog",
	.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
		   WDIOF_PRETIMEOUT,
};

static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
			    void *data)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;

	/* Use internal reset or external - not both */
	if (wdev->ext_reset)
		wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
	else
		wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */

	/* Assert SRS signal */
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
	/*
	 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	 * written twice), we add another two writes to ensure there must be at
	 * least two writes happen in the same one 32kHz clock period.  We save
	 * the target check here, since the writes shouldn't be a huge burden
	 * for other platforms.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);

	/* wait for reset to assert... */
	mdelay(500);

	return 0;
}

static inline void imx2_wdt_setup(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	/* Suspend timer in low power mode, write once-only */
	val |= IMX2_WDT_WCR_WDZST;
	/* Strip the old watchdog Time-Out value */
	val &= ~IMX2_WDT_WCR_WT;
	/* Generate internal chip-level reset if WDOG times out */
	if (!wdev->ext_reset)
		val &= ~IMX2_WDT_WCR_WRE;
	/* Or if external-reset assert WDOG_B reset only on time-out */
	else
		val |= IMX2_WDT_WCR_WRE;
	/* Keep Watchdog Disabled */
	val &= ~IMX2_WDT_WCR_WDE;
	/* Set the watchdog's Time-Out value */
	val |= WDOG_SEC_TO_COUNT(wdog->timeout);

	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);

	/* enable the watchdog */
	val |= IMX2_WDT_WCR_WDE;
	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
}

static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
{
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	return val & IMX2_WDT_WCR_WDE;
}

static int imx2_wdt_ping(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (!wdev->clk_is_on)
		return 0;

	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	return 0;
}

static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
				   unsigned int new_timeout)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
			   WDOG_SEC_TO_COUNT(new_timeout));
}

static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int new_timeout)
{
	unsigned int actual;

	actual = min(new_timeout, IMX2_WDT_MAX_TIME);
	__imx2_wdt_set_timeout(wdog, actual);
	wdog->timeout = new_timeout;
	return 0;
}

static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
				   unsigned int new_pretimeout)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (new_pretimeout >= IMX2_WDT_MAX_TIME)
		return -EINVAL;

	wdog->pretimeout = new_pretimeout;

	regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
			   IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
			   IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
	return 0;
}

static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
{
	struct watchdog_device *wdog = wdog_arg;
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
			  IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);

	watchdog_notify_pretimeout(wdog);

	return IRQ_HANDLED;
}

static int imx2_wdt_start(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev))
		imx2_wdt_set_timeout(wdog, wdog->timeout);
	else
		imx2_wdt_setup(wdog);

	set_bit(WDOG_HW_RUNNING, &wdog->status);

	return imx2_wdt_ping(wdog);
}

static const struct watchdog_ops imx2_wdt_ops = {
	.owner = THIS_MODULE,
	.start = imx2_wdt_start,
	.ping = imx2_wdt_ping,
	.set_timeout = imx2_wdt_set_timeout,
	.set_pretimeout = imx2_wdt_set_pretimeout,
	.restart = imx2_wdt_restart,
};

static const struct regmap_config imx2_wdt_regmap_config = {
	.reg_bits = 16,
	.reg_stride = 2,
	.val_bits = 16,
	.max_register = 0x8,
};

static void imx2_wdt_action(void *data)
{
	clk_disable_unprepare(data);
}

static int __init imx2_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct imx2_wdt_device *wdev;
	struct watchdog_device *wdog;
	void __iomem *base;
	int ret;
	u32 val;

	wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
						 &imx2_wdt_regmap_config);
	if (IS_ERR(wdev->regmap)) {
		dev_err(dev, "regmap init failed\n");
		return PTR_ERR(wdev->regmap);
	}

	wdev->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(wdev->clk)) {
		dev_err(dev, "can't get Watchdog clock\n");
		return PTR_ERR(wdev->clk);
	}

	wdog			= &wdev->wdog;
	wdog->info		= &imx2_wdt_info;
	wdog->ops		= &imx2_wdt_ops;
	wdog->min_timeout	= 1;
	wdog->timeout		= IMX2_WDT_DEFAULT_TIME;
	wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
	wdog->parent		= dev;

	ret = platform_get_irq(pdev, 0);
	if (ret > 0)
		if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0,
				      dev_name(dev), wdog))
			wdog->info = &imx2_wdt_pretimeout_info;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);
	if (ret)
		return ret;

	wdev->clk_is_on = true;

	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;

	wdev->ext_reset = of_property_read_bool(dev->of_node,
						"fsl,ext-reset-output");
	platform_set_drvdata(pdev, wdog);
	watchdog_set_drvdata(wdog, wdev);
	watchdog_set_nowayout(wdog, nowayout);
	watchdog_set_restart_priority(wdog, 128);
	watchdog_init_timeout(wdog, timeout, dev);
	watchdog_stop_ping_on_suspend(wdog);

	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		set_bit(WDOG_HW_RUNNING, &wdog->status);
	}

	/*
	 * Disable the watchdog power down counter at boot. Otherwise the power
	 * down counter will pull down the #WDOG interrupt line for one clock
	 * cycle.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);

	return devm_watchdog_register_device(dev, wdog);
}

static void imx2_wdt_shutdown(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/*
		 * We are running, configure max timeout before reboot
		 * will take place.
		 */
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
	}
}

/* Disable watchdog if it is active or non-active but still running */
static int __maybe_unused imx2_wdt_suspend(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* The watchdog IP block is running */
	if (imx2_wdt_is_running(wdev)) {
		/*
		 * Don't update wdog->timeout, we'll restore the current value
		 * during resume.
		 */
		__imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
	}

	clk_disable_unprepare(wdev->clk);

	wdev->clk_is_on = false;

	return 0;
}

/* Enable watchdog and configure it if necessary */
static int __maybe_unused imx2_wdt_resume(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	int ret;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	wdev->clk_is_on = true;

	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
		/*
		 * If the watchdog is still active and resumes
		 * from deep sleep state, need to restart the
		 * watchdog again.
		 */
		imx2_wdt_setup(wdog);
	}
	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
	}

	return 0;
}

static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
			 imx2_wdt_resume);

static const struct of_device_id imx2_wdt_dt_ids[] = {
	{ .compatible = "fsl,imx21-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);

static struct platform_driver imx2_wdt_driver = {
	.shutdown	= imx2_wdt_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.pm     = &imx2_wdt_pm_ops,
		.of_match_table = imx2_wdt_dt_ids,
	},
};

module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);

MODULE_AUTHOR("Wolfram Sang");
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
cd6100fc	1	// SPDX-License-Identifier: GPL-2.0
bb2fd8a8 WS	2	/*
	3	* Watchdog driver for IMX2 and later processors
	4	*
62c35b44	5	* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <kernel@pengutronix.de>
1a9c5efa	6	* Copyright (C) 2014 Freescale Semiconductor, Inc.
bb2fd8a8 WS	7	*
	8	* some parts adapted by similar drivers from Darius Augulis and Vladimir
	9	* Zapolskiy, additional improvements by Wim Van Sebroeck.
	10	*
bb2fd8a8 WS	11	* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
	12	*
	13	* MX1: MX2+:
	14	* ---- -----
	15	* Registers: 32-bit 16-bit
	16	* Stopable timer: Yes No
	17	* Need to enable clk: No Yes
	18	* Halt on suspend: Manual Can be automatic
	19	*/
	20
30cb042a	21	#include <linux/clk.h>
334a9d81	22	#include <linux/delay.h>
bb2fd8a8	23	#include <linux/init.h>
39487f66	24	#include <linux/interrupt.h>
30cb042a	25	#include <linux/io.h>
bb2fd8a8	26	#include <linux/kernel.h>
bb2fd8a8 WS	27	#include <linux/module.h>
bb2fd8a8 WS	28	#include <linux/moduleparam.h>
f728f4bf	29	#include <linux/of_address.h>
bb2fd8a8	30	#include <linux/platform_device.h>
a7977003	31	#include <linux/regmap.h>
30cb042a	32	#include <linux/watchdog.h>
bb2fd8a8 WS	33
	34	#define DRIVER_NAME "imx2-wdt"
	35
	36	#define IMX2_WDT_WCR 0x00 /* Control Register */
	37	#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
68d4cb80 VZ	38	#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
	39	#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
	40	#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
	41	#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
	42	#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
bb2fd8a8 WS	43
	44	#define IMX2_WDT_WSR 0x02 /* Service Register */
	45	#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
	46	#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
	47
474ef121	48	#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
68d4cb80	49	#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
474ef121	50
39487f66 VZ	51	#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
	52	#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
	53	#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
	54	#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
	55
5fe65ce7 MP	56	#define IMX2_WDT_WMCR 0x08 /* Misc Register */
5fe65ce7 MP	57
144783a8	58	#define IMX2_WDT_MAX_TIME 128U
bb2fd8a8 WS	59	#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
	60
	61	#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
	62
faad5de0	63	struct imx2_wdt_device {
bb2fd8a8	64	struct clk *clk;
a7977003	65	struct regmap *regmap;
faad5de0	66	struct watchdog_device wdog;
bc677ff4	67	bool ext_reset;
e0b101ab	68	bool clk_is_on;
faad5de0	69	};
bb2fd8a8	70
86a1e189 WVS	71	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	72	module_param(nowayout, bool, 0);
bb2fd8a8 WS	73	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	74	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	75
2b77f008	76	static unsigned timeout;
bb2fd8a8 WS	77	module_param(timeout, uint, 0);
	78	MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
	79	__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
	80
	81	static const struct watchdog_info imx2_wdt_info = {
	82	.identity = "imx2+ watchdog",
	83	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE,
	84	};
	85
39487f66 VZ	86	static const struct watchdog_info imx2_wdt_pretimeout_info = {
	87	.identity = "imx2+ watchdog",
	88	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE \|
	89	WDIOF_PRETIMEOUT,
	90	};
	91
4d8b229d GR	92	static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
4d8b229d GR	93	void *data)
334a9d81	94	{
2d9d2475	95	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
334a9d81	96	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
2d9d2475	97
bc677ff4 TH	98	/* Use internal reset or external - not both */
	99	if (wdev->ext_reset)
	100	wcr_enable \|= IMX2_WDT_WCR_SRS; /* do not assert int reset */
	101	else
	102	wcr_enable \|= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
	103
334a9d81	104	/* Assert SRS signal */
9493c0d8	105	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
334a9d81 JL	106	/*
	107	* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	108	* written twice), we add another two writes to ensure there must be at
	109	* least two writes happen in the same one 32kHz clock period. We save
	110	* the target check here, since the writes shouldn't be a huge burden
	111	* for other platforms.
	112	*/
9493c0d8 FE	113	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
9493c0d8 FE	114	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
334a9d81 JL	115
	116	/* wait for reset to assert... */
	117	mdelay(500);
	118
2d9d2475	119	return 0;
334a9d81 JL	120	}
334a9d81 JL	121
faad5de0	122	static inline void imx2_wdt_setup(struct watchdog_device *wdog)
bb2fd8a8	123	{
faad5de0	124	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
a7977003 XL	125	u32 val;
a7977003 XL	126
faad5de0	127	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
bb2fd8a8	128
1a9c5efa AH	129	/* Suspend timer in low power mode, write once-only */
1a9c5efa AH	130	val \|= IMX2_WDT_WCR_WDZST;
bb2fd8a8 WS	131	/* Strip the old watchdog Time-Out value */
bb2fd8a8 WS	132	val &= ~IMX2_WDT_WCR_WT;
bc677ff4 TH	133	/* Generate internal chip-level reset if WDOG times out */
	134	if (!wdev->ext_reset)
	135	val &= ~IMX2_WDT_WCR_WRE;
	136	/* Or if external-reset assert WDOG_B reset only on time-out */
	137	else
	138	val \|= IMX2_WDT_WCR_WRE;
bb2fd8a8 WS	139	/* Keep Watchdog Disabled */
	140	val &= ~IMX2_WDT_WCR_WDE;
	141	/* Set the watchdog's Time-Out value */
faad5de0	142	val \|= WDOG_SEC_TO_COUNT(wdog->timeout);
bb2fd8a8	143
faad5de0	144	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	145
	146	/* enable the watchdog */
	147	val \|= IMX2_WDT_WCR_WDE;
faad5de0	148	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	149	}
bb2fd8a8 WS	150
faad5de0	151	static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
bb2fd8a8	152	{
faad5de0	153	u32 val;
bb2fd8a8	154
faad5de0 AG	155	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
	156
	157	return val & IMX2_WDT_WCR_WDE;
bb2fd8a8 WS	158	}
bb2fd8a8 WS	159
faad5de0	160	static int imx2_wdt_ping(struct watchdog_device *wdog)
bb2fd8a8	161	{
faad5de0	162	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	163
e0b101ab RG	164	if (!wdev->clk_is_on)
	165	return 0;
	166
faad5de0 AG	167	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	168	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	169	return 0;
bb2fd8a8 WS	170	}
bb2fd8a8 WS	171
0be26725 MK	172	static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
0be26725 MK	173	unsigned int new_timeout)
bb2fd8a8	174	{
faad5de0 AG	175	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	176
	177	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
a7977003	178	WDOG_SEC_TO_COUNT(new_timeout));
0be26725 MK	179	}
	180
	181	static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
	182	unsigned int new_timeout)
	183	{
b07e228e	184	unsigned int actual;
0be26725	185
144783a8	186	actual = min(new_timeout, IMX2_WDT_MAX_TIME);
b07e228e	187	__imx2_wdt_set_timeout(wdog, actual);
0be26725	188	wdog->timeout = new_timeout;
faad5de0	189	return 0;
bb2fd8a8 WS	190	}
bb2fd8a8 WS	191
39487f66 VZ	192	static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
	193	unsigned int new_pretimeout)
	194	{
	195	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	196
	197	if (new_pretimeout >= IMX2_WDT_MAX_TIME)
	198	return -EINVAL;
	199
	200	wdog->pretimeout = new_pretimeout;
	201
	202	regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
	203	IMX2_WDT_WICR_WIE \| IMX2_WDT_WICR_WICT,
	204	IMX2_WDT_WICR_WIE \| (new_pretimeout << 1));
	205	return 0;
	206	}
	207
	208	static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
	209	{
	210	struct watchdog_device *wdog = wdog_arg;
	211	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	212
	213	regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
	214	IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
	215
	216	watchdog_notify_pretimeout(wdog);
	217
	218	return IRQ_HANDLED;
	219	}
	220
faad5de0	221	static int imx2_wdt_start(struct watchdog_device *wdog)
bb2fd8a8	222	{
faad5de0	223	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	224
11d7aba9	225	if (imx2_wdt_is_running(wdev))
faad5de0	226	imx2_wdt_set_timeout(wdog, wdog->timeout);
11d7aba9	227	else
faad5de0 AG	228	imx2_wdt_setup(wdog);
faad5de0 AG	229
11d7aba9	230	set_bit(WDOG_HW_RUNNING, &wdog->status);
bb2fd8a8	231
11d7aba9	232	return imx2_wdt_ping(wdog);
bb2fd8a8 WS	233	}
bb2fd8a8 WS	234
4bd8ce33	235	static const struct watchdog_ops imx2_wdt_ops = {
bb2fd8a8	236	.owner = THIS_MODULE,
faad5de0	237	.start = imx2_wdt_start,
faad5de0 AG	238	.ping = imx2_wdt_ping,
faad5de0 AG	239	.set_timeout = imx2_wdt_set_timeout,
39487f66	240	.set_pretimeout = imx2_wdt_set_pretimeout,
2d9d2475	241	.restart = imx2_wdt_restart,
bb2fd8a8 WS	242	};
bb2fd8a8 WS	243
4bd8ce33	244	static const struct regmap_config imx2_wdt_regmap_config = {
a7977003 XL	245	.reg_bits = 16,
	246	.reg_stride = 2,
	247	.val_bits = 16,
	248	.max_register = 0x8,
	249	};
	250
436867b6 AH	251	static void imx2_wdt_action(void *data)
	252	{
	253	clk_disable_unprepare(data);
	254	}
	255
bb2fd8a8 WS	256	static int __init imx2_wdt_probe(struct platform_device *pdev)
bb2fd8a8 WS	257	{
86865322	258	struct device *dev = &pdev->dev;
faad5de0 AG	259	struct imx2_wdt_device *wdev;
faad5de0 AG	260	struct watchdog_device *wdog;
a7977003 XL	261	void __iomem *base;
a7977003 XL	262	int ret;
faad5de0 AG	263	u32 val;
faad5de0 AG	264
86865322	265	wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
faad5de0 AG	266	if (!wdev)
faad5de0 AG	267	return -ENOMEM;
bb2fd8a8	268
24b82256	269	base = devm_platform_ioremap_resource(pdev, 0);
a7977003 XL	270	if (IS_ERR(base))
	271	return PTR_ERR(base);
	272
86865322	273	wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
faad5de0 AG	274	&imx2_wdt_regmap_config);
faad5de0 AG	275	if (IS_ERR(wdev->regmap)) {
86865322	276	dev_err(dev, "regmap init failed\n");
faad5de0	277	return PTR_ERR(wdev->regmap);
a7977003	278	}
bb2fd8a8	279
86865322	280	wdev->clk = devm_clk_get(dev, NULL);
faad5de0	281	if (IS_ERR(wdev->clk)) {
86865322	282	dev_err(dev, "can't get Watchdog clock\n");
faad5de0	283	return PTR_ERR(wdev->clk);
bb2fd8a8 WS	284	}
bb2fd8a8 WS	285
faad5de0 AG	286	wdog = &wdev->wdog;
	287	wdog->info = &imx2_wdt_info;
	288	wdog->ops = &imx2_wdt_ops;
	289	wdog->min_timeout = 1;
2b77f008	290	wdog->timeout = IMX2_WDT_DEFAULT_TIME;
11d7aba9	291	wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
86865322	292	wdog->parent = dev;
bb2fd8a8	293
39487f66 VZ	294	ret = platform_get_irq(pdev, 0);
39487f66 VZ	295	if (ret > 0)
86865322 AH	296	if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0,
86865322 AH	297	dev_name(dev), wdog))
39487f66 VZ	298	wdog->info = &imx2_wdt_pretimeout_info;
39487f66 VZ	299
aefb163c FE	300	ret = clk_prepare_enable(wdev->clk);
	301	if (ret)
	302	return ret;
bb2fd8a8	303
436867b6 AH	304	ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);
	305	if (ret)
	306	return ret;
	307
e0b101ab RG	308	wdev->clk_is_on = true;
e0b101ab RG	309
faad5de0 AG	310	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
faad5de0 AG	311	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
bb2fd8a8	312
86865322	313	wdev->ext_reset = of_property_read_bool(dev->of_node,
bc677ff4	314	"fsl,ext-reset-output");
faad5de0 AG	315	platform_set_drvdata(pdev, wdog);
	316	watchdog_set_drvdata(wdog, wdev);
	317	watchdog_set_nowayout(wdog, nowayout);
2d9d2475	318	watchdog_set_restart_priority(wdog, 128);
86865322	319	watchdog_init_timeout(wdog, timeout, dev);
14244b7c	320	watchdog_stop_ping_on_suspend(wdog);
faad5de0	321
11d7aba9 GR	322	if (imx2_wdt_is_running(wdev)) {
	323	imx2_wdt_set_timeout(wdog, wdog->timeout);
	324	set_bit(WDOG_HW_RUNNING, &wdog->status);
	325	}
faad5de0	326
5fe65ce7 MP	327	/*
	328	* Disable the watchdog power down counter at boot. Otherwise the power
	329	* down counter will pull down the #WDOG interrupt line for one clock
	330	* cycle.
	331	*/
	332	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
	333
436867b6	334	return devm_watchdog_register_device(dev, wdog);
bb2fd8a8 WS	335	}
	336
	337	static void imx2_wdt_shutdown(struct platform_device *pdev)
	338	{
faad5de0 AG	339	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	340	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	341
	342	if (imx2_wdt_is_running(wdev)) {
	343	/*
11d7aba9 GR	344	* We are running, configure max timeout before reboot
11d7aba9 GR	345	* will take place.
faad5de0	346	*/
faad5de0 AG	347	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	348	imx2_wdt_ping(wdog);
	349	dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
bb2fd8a8 WS	350	}
	351	}
	352
bbd59009	353	/* Disable watchdog if it is active or non-active but still running */
ebe66ded	354	static int __maybe_unused imx2_wdt_suspend(struct device *dev)
aefbaf3a XL	355	{
	356	struct watchdog_device *wdog = dev_get_drvdata(dev);
	357	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	358
bbd59009 XL	359	/* The watchdog IP block is running */
bbd59009 XL	360	if (imx2_wdt_is_running(wdev)) {
0be26725 MK	361	/*
	362	* Don't update wdog->timeout, we'll restore the current value
	363	* during resume.
	364	*/
	365	__imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
bbd59009	366	imx2_wdt_ping(wdog);
bbd59009	367	}
aefbaf3a XL	368
	369	clk_disable_unprepare(wdev->clk);
	370
e0b101ab RG	371	wdev->clk_is_on = false;
e0b101ab RG	372
aefbaf3a XL	373	return 0;
	374	}
	375
	376	/* Enable watchdog and configure it if necessary */
ebe66ded	377	static int __maybe_unused imx2_wdt_resume(struct device *dev)
aefbaf3a XL	378	{
	379	struct watchdog_device *wdog = dev_get_drvdata(dev);
	380	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
aefb163c	381	int ret;
aefbaf3a	382
aefb163c FE	383	ret = clk_prepare_enable(wdev->clk);
	384	if (ret)
	385	return ret;
aefbaf3a	386
e0b101ab RG	387	wdev->clk_is_on = true;
e0b101ab RG	388
aefbaf3a	389	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
bbd59009 XL	390	/*
	391	* If the watchdog is still active and resumes
	392	* from deep sleep state, need to restart the
	393	* watchdog again.
aefbaf3a XL	394	*/
aefbaf3a XL	395	imx2_wdt_setup(wdog);
11d7aba9 GR	396	}
11d7aba9 GR	397	if (imx2_wdt_is_running(wdev)) {
aefbaf3a XL	398	imx2_wdt_set_timeout(wdog, wdog->timeout);
aefbaf3a XL	399	imx2_wdt_ping(wdog);
aefbaf3a XL	400	}
	401
	402	return 0;
	403	}
aefbaf3a XL	404
	405	static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
	406	imx2_wdt_resume);
	407
f5a427ee SG	408	static const struct of_device_id imx2_wdt_dt_ids[] = {
	409	{ .compatible = "fsl,imx21-wdt", },
	410	{ /* sentinel */ }
	411	};
813296a1	412	MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
f5a427ee	413
bb2fd8a8	414	static struct platform_driver imx2_wdt_driver = {
bb2fd8a8 WS	415	.shutdown = imx2_wdt_shutdown,
	416	.driver = {
	417	.name = DRIVER_NAME,
aefbaf3a	418	.pm = &imx2_wdt_pm_ops,
f5a427ee	419	.of_match_table = imx2_wdt_dt_ids,
bb2fd8a8 WS	420	},
	421	};
	422
1cb9204c	423	module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
bb2fd8a8 WS	424
	425	MODULE_AUTHOR("Wolfram Sang");
	426	MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
	427	MODULE_LICENSE("GPL v2");
bb2fd8a8	428	MODULE_ALIAS("platform:" DRIVER_NAME);