Commit | Line | Data |
---|---|---|
d0173278 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
9e0ea345 | 2 | /* |
cb711a19 | 3 | * intel TCO Watchdog Driver |
9e0ea345 | 4 | * |
deb9197b | 5 | * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>. |
9e0ea345 | 6 | * |
9e0ea345 WVS |
7 | * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor |
8 | * provide warranty for any of this software. This material is | |
9 | * provided "AS-IS" and at no charge. | |
10 | * | |
11 | * The TCO watchdog is implemented in the following I/O controller hubs: | |
12 | * (See the intel documentation on http://developer.intel.com.) | |
cb711a19 WVS |
13 | * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) |
14 | * document number 290687-002, 298242-027: 82801BA (ICH2) | |
15 | * document number 290733-003, 290739-013: 82801CA (ICH3-S) | |
16 | * document number 290716-001, 290718-007: 82801CAM (ICH3-M) | |
17 | * document number 290744-001, 290745-025: 82801DB (ICH4) | |
18 | * document number 252337-001, 252663-008: 82801DBM (ICH4-M) | |
19 | * document number 273599-001, 273645-002: 82801E (C-ICH) | |
20 | * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) | |
21 | * document number 300641-004, 300884-013: 6300ESB | |
22 | * document number 301473-002, 301474-026: 82801F (ICH6) | |
23 | * document number 313082-001, 313075-006: 631xESB, 632xESB | |
24 | * document number 307013-003, 307014-024: 82801G (ICH7) | |
d38bd479 | 25 | * document number 322896-001, 322897-001: NM10 |
cb711a19 WVS |
26 | * document number 313056-003, 313057-017: 82801H (ICH8) |
27 | * document number 316972-004, 316973-012: 82801I (ICH9) | |
28 | * document number 319973-002, 319974-002: 82801J (ICH10) | |
3c9d8ecc | 29 | * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) |
4946f835 | 30 | * document number 320066-003, 320257-008: EP80597 (IICH) |
203f8d89 | 31 | * document number 324645-001, 324646-001: Cougar Point (CPT) |
c54fb811 | 32 | * document number TBD : Patsburg (PBG) |
203f8d89 | 33 | * document number TBD : DH89xxCC |
aa1f4652 | 34 | * document number TBD : Panther Point |
84e83c28 | 35 | * document number TBD : Lynx Point |
7fb9c1a4 | 36 | * document number TBD : Lynx Point-LP |
9e0ea345 WVS |
37 | */ |
38 | ||
39 | /* | |
40 | * Includes, defines, variables, module parameters, ... | |
41 | */ | |
42 | ||
27c766aa JP |
43 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
44 | ||
9e0ea345 | 45 | /* Module and version information */ |
7944d3a5 | 46 | #define DRV_NAME "iTCO_wdt" |
24b3a167 | 47 | #define DRV_VERSION "1.11" |
9e0ea345 WVS |
48 | |
49 | /* Includes */ | |
f321c9cb | 50 | #include <linux/acpi.h> /* For ACPI support */ |
da23b6fa | 51 | #include <linux/bits.h> /* For BIT() */ |
3836cc0f WVS |
52 | #include <linux/module.h> /* For module specific items */ |
53 | #include <linux/moduleparam.h> /* For new moduleparam's */ | |
54 | #include <linux/types.h> /* For standard types (like size_t) */ | |
55 | #include <linux/errno.h> /* For the -ENODEV/... values */ | |
56 | #include <linux/kernel.h> /* For printk/panic/... */ | |
3836cc0f | 57 | #include <linux/watchdog.h> /* For the watchdog specific items */ |
3836cc0f WVS |
58 | #include <linux/init.h> /* For __init/__exit/... */ |
59 | #include <linux/fs.h> /* For file operations */ | |
60 | #include <linux/platform_device.h> /* For platform_driver framework */ | |
61 | #include <linux/pci.h> /* For pci functions */ | |
62 | #include <linux/ioport.h> /* For io-port access */ | |
63 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ | |
0e6fa3fb AC |
64 | #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ |
65 | #include <linux/io.h> /* For inb/outb/... */ | |
420b54de | 66 | #include <linux/platform_data/itco_wdt.h> |
25f1ca31 | 67 | #include <linux/mfd/intel_pmc_bxt.h> |
3836cc0f | 68 | |
0e6fa3fb | 69 | #include "iTCO_vendor.h" |
9e0ea345 | 70 | |
9e0ea345 | 71 | /* Address definitions for the TCO */ |
0e6fa3fb | 72 | /* TCO base address */ |
ce1b95ca | 73 | #define TCOBASE(p) ((p)->tco_res->start) |
0e6fa3fb | 74 | /* SMI Control and Enable Register */ |
ce1b95ca GR |
75 | #define SMI_EN(p) ((p)->smi_res->start) |
76 | ||
77 | #define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */ | |
78 | #define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/ | |
79 | #define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */ | |
80 | #define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */ | |
81 | #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */ | |
82 | #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */ | |
83 | #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */ | |
84 | #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */ | |
85 | #define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/ | |
9e0ea345 WVS |
86 | |
87 | /* internal variables */ | |
ce1b95ca GR |
88 | struct iTCO_wdt_private { |
89 | struct watchdog_device wddev; | |
90 | ||
0e6fa3fb AC |
91 | /* TCO version/generation */ |
92 | unsigned int iTCO_version; | |
887c8ec7 AS |
93 | struct resource *tco_res; |
94 | struct resource *smi_res; | |
24b3a167 PT |
95 | /* |
96 | * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2), | |
97 | * or memory-mapped PMC register bit 4 (TCO version 3). | |
98 | */ | |
99 | struct resource *gcs_pmc_res; | |
100 | unsigned long __iomem *gcs_pmc; | |
0e6fa3fb AC |
101 | /* the lock for io operations */ |
102 | spinlock_t io_lock; | |
103 | /* the PCI-device */ | |
78e45696 | 104 | struct pci_dev *pci_dev; |
f321c9cb RW |
105 | /* whether or not the watchdog has been suspended */ |
106 | bool suspended; | |
140c91b2 KS |
107 | /* no reboot API private data */ |
108 | void *no_reboot_priv; | |
f583a884 KS |
109 | /* no reboot update function pointer */ |
110 | int (*update_no_reboot_bit)(void *p, bool set); | |
ce1b95ca | 111 | }; |
9e0ea345 WVS |
112 | |
113 | /* module parameters */ | |
bff23431 WVS |
114 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */ |
115 | static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */ | |
9e0ea345 | 116 | module_param(heartbeat, int, 0); |
7e6811da PB |
117 | MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. " |
118 | "5..76 (TCO v1) or 3..614 (TCO v2), default=" | |
bff23431 | 119 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); |
9e0ea345 | 120 | |
86a1e189 WVS |
121 | static bool nowayout = WATCHDOG_NOWAYOUT; |
122 | module_param(nowayout, bool, 0); | |
0e6fa3fb AC |
123 | MODULE_PARM_DESC(nowayout, |
124 | "Watchdog cannot be stopped once started (default=" | |
125 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
e033351d | 126 | |
0d098587 | 127 | static int turn_SMI_watchdog_clear_off = 1; |
deb9197b WVS |
128 | module_param(turn_SMI_watchdog_clear_off, int, 0); |
129 | MODULE_PARM_DESC(turn_SMI_watchdog_clear_off, | |
0d098587 | 130 | "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)"); |
deb9197b | 131 | |
9e0ea345 WVS |
132 | /* |
133 | * Some TCO specific functions | |
134 | */ | |
135 | ||
24b3a167 PT |
136 | /* |
137 | * The iTCO v1 and v2's internal timer is stored as ticks which decrement | |
138 | * every 0.6 seconds. v3's internal timer is stored as seconds (some | |
139 | * datasheets incorrectly state 0.6 seconds). | |
140 | */ | |
ce1b95ca GR |
141 | static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p, |
142 | int secs) | |
9e0ea345 | 143 | { |
ce1b95ca | 144 | return p->iTCO_version == 3 ? secs : (secs * 10) / 6; |
24b3a167 PT |
145 | } |
146 | ||
ce1b95ca GR |
147 | static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p, |
148 | int ticks) | |
24b3a167 | 149 | { |
ce1b95ca | 150 | return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10; |
9e0ea345 WVS |
151 | } |
152 | ||
ce1b95ca | 153 | static inline u32 no_reboot_bit(struct iTCO_wdt_private *p) |
2a7a0e9b MF |
154 | { |
155 | u32 enable_bit; | |
156 | ||
ce1b95ca | 157 | switch (p->iTCO_version) { |
3b3a1c8f | 158 | case 5: |
2a7a0e9b MF |
159 | case 3: |
160 | enable_bit = 0x00000010; | |
161 | break; | |
162 | case 2: | |
163 | enable_bit = 0x00000020; | |
164 | break; | |
165 | case 4: | |
166 | case 1: | |
167 | default: | |
168 | enable_bit = 0x00000002; | |
169 | break; | |
170 | } | |
171 | ||
172 | return enable_bit; | |
173 | } | |
174 | ||
f583a884 | 175 | static int update_no_reboot_bit_def(void *priv, bool set) |
9e0ea345 | 176 | { |
f583a884 | 177 | return 0; |
9e0ea345 WVS |
178 | } |
179 | ||
f583a884 | 180 | static int update_no_reboot_bit_pci(void *priv, bool set) |
9e0ea345 | 181 | { |
f583a884 KS |
182 | struct iTCO_wdt_private *p = priv; |
183 | u32 val32 = 0, newval32 = 0; | |
9e0ea345 | 184 | |
f583a884 KS |
185 | pci_read_config_dword(p->pci_dev, 0xd4, &val32); |
186 | if (set) | |
187 | val32 |= no_reboot_bit(p); | |
188 | else | |
189 | val32 &= ~no_reboot_bit(p); | |
190 | pci_write_config_dword(p->pci_dev, 0xd4, val32); | |
191 | pci_read_config_dword(p->pci_dev, 0xd4, &newval32); | |
9e0ea345 | 192 | |
f583a884 KS |
193 | /* make sure the update is successful */ |
194 | if (val32 != newval32) | |
195 | return -EIO; | |
9e0ea345 | 196 | |
f583a884 KS |
197 | return 0; |
198 | } | |
199 | ||
200 | static int update_no_reboot_bit_mem(void *priv, bool set) | |
201 | { | |
202 | struct iTCO_wdt_private *p = priv; | |
203 | u32 val32 = 0, newval32 = 0; | |
204 | ||
205 | val32 = readl(p->gcs_pmc); | |
206 | if (set) | |
207 | val32 |= no_reboot_bit(p); | |
208 | else | |
209 | val32 &= ~no_reboot_bit(p); | |
210 | writel(val32, p->gcs_pmc); | |
211 | newval32 = readl(p->gcs_pmc); | |
9e0ea345 | 212 | |
f583a884 KS |
213 | /* make sure the update is successful */ |
214 | if (val32 != newval32) | |
2a7a0e9b MF |
215 | return -EIO; |
216 | ||
217 | return 0; | |
9e0ea345 WVS |
218 | } |
219 | ||
da23b6fa MW |
220 | static int update_no_reboot_bit_cnt(void *priv, bool set) |
221 | { | |
222 | struct iTCO_wdt_private *p = priv; | |
223 | u16 val, newval; | |
224 | ||
225 | val = inw(TCO1_CNT(p)); | |
226 | if (set) | |
227 | val |= BIT(0); | |
228 | else | |
229 | val &= ~BIT(0); | |
230 | outw(val, TCO1_CNT(p)); | |
231 | newval = inw(TCO1_CNT(p)); | |
232 | ||
233 | /* make sure the update is successful */ | |
234 | return val != newval ? -EIO : 0; | |
235 | } | |
236 | ||
25f1ca31 MW |
237 | static int update_no_reboot_bit_pmc(void *priv, bool set) |
238 | { | |
239 | struct intel_pmc_dev *pmc = priv; | |
240 | u32 bits = PMC_CFG_NO_REBOOT_EN; | |
241 | u32 value = set ? bits : 0; | |
242 | ||
243 | return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value); | |
244 | } | |
245 | ||
140c91b2 | 246 | static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p, |
25f1ca31 MW |
247 | struct platform_device *pdev, |
248 | struct itco_wdt_platform_data *pdata) | |
f583a884 | 249 | { |
25f1ca31 MW |
250 | if (pdata->no_reboot_use_pmc) { |
251 | struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent); | |
252 | ||
253 | p->update_no_reboot_bit = update_no_reboot_bit_pmc; | |
254 | p->no_reboot_priv = pmc; | |
140c91b2 KS |
255 | return; |
256 | } | |
257 | ||
da23b6fa MW |
258 | if (p->iTCO_version >= 6) |
259 | p->update_no_reboot_bit = update_no_reboot_bit_cnt; | |
260 | else if (p->iTCO_version >= 2) | |
f583a884 KS |
261 | p->update_no_reboot_bit = update_no_reboot_bit_mem; |
262 | else if (p->iTCO_version == 1) | |
263 | p->update_no_reboot_bit = update_no_reboot_bit_pci; | |
264 | else | |
265 | p->update_no_reboot_bit = update_no_reboot_bit_def; | |
140c91b2 KS |
266 | |
267 | p->no_reboot_priv = p; | |
f583a884 KS |
268 | } |
269 | ||
bff23431 | 270 | static int iTCO_wdt_start(struct watchdog_device *wd_dev) |
9e0ea345 | 271 | { |
ce1b95ca | 272 | struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
9e0ea345 WVS |
273 | unsigned int val; |
274 | ||
ce1b95ca | 275 | spin_lock(&p->io_lock); |
9e0ea345 | 276 | |
ce1b95ca | 277 | iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout); |
e033351d | 278 | |
9e0ea345 | 279 | /* disable chipset's NO_REBOOT bit */ |
140c91b2 | 280 | if (p->update_no_reboot_bit(p->no_reboot_priv, false)) { |
ce1b95ca | 281 | spin_unlock(&p->io_lock); |
27c766aa | 282 | pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n"); |
9e0ea345 WVS |
283 | return -EIO; |
284 | } | |
285 | ||
7cd5b08b WVS |
286 | /* Force the timer to its reload value by writing to the TCO_RLD |
287 | register */ | |
ce1b95ca GR |
288 | if (p->iTCO_version >= 2) |
289 | outw(0x01, TCO_RLD(p)); | |
290 | else if (p->iTCO_version == 1) | |
291 | outb(0x01, TCO_RLD(p)); | |
7cd5b08b | 292 | |
9e0ea345 | 293 | /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ |
ce1b95ca | 294 | val = inw(TCO1_CNT(p)); |
9e0ea345 | 295 | val &= 0xf7ff; |
ce1b95ca GR |
296 | outw(val, TCO1_CNT(p)); |
297 | val = inw(TCO1_CNT(p)); | |
298 | spin_unlock(&p->io_lock); | |
9e0ea345 WVS |
299 | |
300 | if (val & 0x0800) | |
301 | return -1; | |
302 | return 0; | |
303 | } | |
304 | ||
bff23431 | 305 | static int iTCO_wdt_stop(struct watchdog_device *wd_dev) |
9e0ea345 | 306 | { |
ce1b95ca | 307 | struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
9e0ea345 WVS |
308 | unsigned int val; |
309 | ||
ce1b95ca | 310 | spin_lock(&p->io_lock); |
9e0ea345 | 311 | |
ce1b95ca | 312 | iTCO_vendor_pre_stop(p->smi_res); |
e033351d | 313 | |
9e0ea345 | 314 | /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ |
ce1b95ca | 315 | val = inw(TCO1_CNT(p)); |
9e0ea345 | 316 | val |= 0x0800; |
ce1b95ca GR |
317 | outw(val, TCO1_CNT(p)); |
318 | val = inw(TCO1_CNT(p)); | |
9e0ea345 WVS |
319 | |
320 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ | |
140c91b2 | 321 | p->update_no_reboot_bit(p->no_reboot_priv, true); |
9e0ea345 | 322 | |
ce1b95ca | 323 | spin_unlock(&p->io_lock); |
9e0ea345 WVS |
324 | |
325 | if ((val & 0x0800) == 0) | |
326 | return -1; | |
327 | return 0; | |
328 | } | |
329 | ||
bff23431 | 330 | static int iTCO_wdt_ping(struct watchdog_device *wd_dev) |
9e0ea345 | 331 | { |
ce1b95ca | 332 | struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
9e0ea345 | 333 | |
ce1b95ca GR |
334 | spin_lock(&p->io_lock); |
335 | ||
9e0ea345 | 336 | /* Reload the timer by writing to the TCO Timer Counter register */ |
fc61e83a | 337 | if (p->iTCO_version >= 2) { |
ce1b95ca | 338 | outw(0x01, TCO_RLD(p)); |
fc61e83a WVS |
339 | } else if (p->iTCO_version == 1) { |
340 | /* Reset the timeout status bit so that the timer | |
341 | * needs to count down twice again before rebooting */ | |
342 | outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */ | |
343 | ||
ce1b95ca | 344 | outb(0x01, TCO_RLD(p)); |
fc61e83a | 345 | } |
9e0ea345 | 346 | |
ce1b95ca | 347 | spin_unlock(&p->io_lock); |
9e0ea345 WVS |
348 | return 0; |
349 | } | |
350 | ||
bff23431 | 351 | static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t) |
9e0ea345 | 352 | { |
ce1b95ca | 353 | struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
9e0ea345 WVS |
354 | unsigned int val16; |
355 | unsigned char val8; | |
356 | unsigned int tmrval; | |
357 | ||
fc61e83a WVS |
358 | tmrval = seconds_to_ticks(p, t); |
359 | ||
360 | /* For TCO v1 the timer counts down twice before rebooting */ | |
361 | if (p->iTCO_version == 1) | |
362 | tmrval /= 2; | |
7e6811da | 363 | |
9e0ea345 WVS |
364 | /* from the specs: */ |
365 | /* "Values of 0h-3h are ignored and should not be attempted" */ | |
366 | if (tmrval < 0x04) | |
367 | return -EINVAL; | |
ce1b95ca GR |
368 | if ((p->iTCO_version >= 2 && tmrval > 0x3ff) || |
369 | (p->iTCO_version == 1 && tmrval > 0x03f)) | |
9e0ea345 WVS |
370 | return -EINVAL; |
371 | ||
372 | /* Write new heartbeat to watchdog */ | |
ce1b95ca GR |
373 | if (p->iTCO_version >= 2) { |
374 | spin_lock(&p->io_lock); | |
375 | val16 = inw(TCOv2_TMR(p)); | |
9e0ea345 WVS |
376 | val16 &= 0xfc00; |
377 | val16 |= tmrval; | |
ce1b95ca GR |
378 | outw(val16, TCOv2_TMR(p)); |
379 | val16 = inw(TCOv2_TMR(p)); | |
380 | spin_unlock(&p->io_lock); | |
9e0ea345 WVS |
381 | |
382 | if ((val16 & 0x3ff) != tmrval) | |
383 | return -EINVAL; | |
ce1b95ca GR |
384 | } else if (p->iTCO_version == 1) { |
385 | spin_lock(&p->io_lock); | |
386 | val8 = inb(TCOv1_TMR(p)); | |
9e0ea345 WVS |
387 | val8 &= 0xc0; |
388 | val8 |= (tmrval & 0xff); | |
ce1b95ca GR |
389 | outb(val8, TCOv1_TMR(p)); |
390 | val8 = inb(TCOv1_TMR(p)); | |
391 | spin_unlock(&p->io_lock); | |
9e0ea345 WVS |
392 | |
393 | if ((val8 & 0x3f) != tmrval) | |
394 | return -EINVAL; | |
395 | } | |
396 | ||
bff23431 | 397 | wd_dev->timeout = t; |
9e0ea345 WVS |
398 | return 0; |
399 | } | |
400 | ||
bff23431 | 401 | static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) |
9e0ea345 | 402 | { |
ce1b95ca | 403 | struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
9e0ea345 WVS |
404 | unsigned int val16; |
405 | unsigned char val8; | |
bff23431 | 406 | unsigned int time_left = 0; |
9e0ea345 WVS |
407 | |
408 | /* read the TCO Timer */ | |
ce1b95ca GR |
409 | if (p->iTCO_version >= 2) { |
410 | spin_lock(&p->io_lock); | |
411 | val16 = inw(TCO_RLD(p)); | |
9e0ea345 | 412 | val16 &= 0x3ff; |
ce1b95ca | 413 | spin_unlock(&p->io_lock); |
9e0ea345 | 414 | |
ce1b95ca GR |
415 | time_left = ticks_to_seconds(p, val16); |
416 | } else if (p->iTCO_version == 1) { | |
417 | spin_lock(&p->io_lock); | |
418 | val8 = inb(TCO_RLD(p)); | |
9e0ea345 | 419 | val8 &= 0x3f; |
ce1b95ca GR |
420 | if (!(inw(TCO1_STS(p)) & 0x0008)) |
421 | val8 += (inb(TCOv1_TMR(p)) & 0x3f); | |
422 | spin_unlock(&p->io_lock); | |
9e0ea345 | 423 | |
ce1b95ca | 424 | time_left = ticks_to_seconds(p, val8); |
9e0ea345 | 425 | } |
bff23431 | 426 | return time_left; |
9e0ea345 WVS |
427 | } |
428 | ||
9e0ea345 WVS |
429 | /* |
430 | * Kernel Interfaces | |
431 | */ | |
432 | ||
bff23431 WVS |
433 | static const struct watchdog_info ident = { |
434 | .options = WDIOF_SETTIMEOUT | | |
435 | WDIOF_KEEPALIVEPING | | |
436 | WDIOF_MAGICCLOSE, | |
437 | .firmware_version = 0, | |
438 | .identity = DRV_NAME, | |
439 | }; | |
440 | ||
441 | static const struct watchdog_ops iTCO_wdt_ops = { | |
0e6fa3fb | 442 | .owner = THIS_MODULE, |
bff23431 | 443 | .start = iTCO_wdt_start, |
5f5e1909 JH |
444 | .stop = iTCO_wdt_stop, |
445 | .ping = iTCO_wdt_ping, | |
bff23431 WVS |
446 | .set_timeout = iTCO_wdt_set_timeout, |
447 | .get_timeleft = iTCO_wdt_get_timeleft, | |
9e0ea345 WVS |
448 | }; |
449 | ||
9e0ea345 WVS |
450 | /* |
451 | * Init & exit routines | |
452 | */ | |
453 | ||
78e45696 | 454 | static int iTCO_wdt_probe(struct platform_device *pdev) |
9e0ea345 | 455 | { |
78e45696 GR |
456 | struct device *dev = &pdev->dev; |
457 | struct itco_wdt_platform_data *pdata = dev_get_platdata(dev); | |
ce1b95ca GR |
458 | struct iTCO_wdt_private *p; |
459 | unsigned long val32; | |
460 | int ret; | |
887c8ec7 | 461 | |
420b54de | 462 | if (!pdata) |
ce1b95ca | 463 | return -ENODEV; |
887c8ec7 | 464 | |
78e45696 | 465 | p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); |
ce1b95ca GR |
466 | if (!p) |
467 | return -ENOMEM; | |
887c8ec7 | 468 | |
ce1b95ca | 469 | spin_lock_init(&p->io_lock); |
887c8ec7 | 470 | |
78e45696 | 471 | p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO); |
ce1b95ca GR |
472 | if (!p->tco_res) |
473 | return -ENODEV; | |
887c8ec7 | 474 | |
ce1b95ca | 475 | p->iTCO_version = pdata->version; |
78e45696 | 476 | p->pci_dev = to_pci_dev(dev->parent); |
9e0ea345 | 477 | |
e42b0c24 MW |
478 | p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI); |
479 | if (p->smi_res) { | |
480 | /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ | |
481 | if (!devm_request_region(dev, p->smi_res->start, | |
482 | resource_size(p->smi_res), | |
483 | pdev->name)) { | |
484 | pr_err("I/O address 0x%04llx already in use, device disabled\n", | |
485 | (u64)SMI_EN(p)); | |
486 | return -EBUSY; | |
487 | } | |
488 | } else if (iTCO_vendorsupport || | |
489 | turn_SMI_watchdog_clear_off >= p->iTCO_version) { | |
490 | pr_err("SMI I/O resource is missing\n"); | |
491 | return -ENODEV; | |
492 | } | |
493 | ||
25f1ca31 | 494 | iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata); |
f583a884 | 495 | |
9e0ea345 | 496 | /* |
24b3a167 PT |
497 | * Get the Memory-Mapped GCS or PMC register, we need it for the |
498 | * NO_REBOOT flag (TCO v2 and v3). | |
9e0ea345 | 499 | */ |
da23b6fa | 500 | if (p->iTCO_version >= 2 && p->iTCO_version < 6 && |
25f1ca31 | 501 | !pdata->no_reboot_use_pmc) { |
78e45696 | 502 | p->gcs_pmc_res = platform_get_resource(pdev, |
ce1b95ca GR |
503 | IORESOURCE_MEM, |
504 | ICH_RES_MEM_GCS_PMC); | |
78e45696 | 505 | p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res); |
c7bbcc87 GR |
506 | if (IS_ERR(p->gcs_pmc)) |
507 | return PTR_ERR(p->gcs_pmc); | |
9e0ea345 WVS |
508 | } |
509 | ||
510 | /* Check chipset's NO_REBOOT bit */ | |
140c91b2 | 511 | if (p->update_no_reboot_bit(p->no_reboot_priv, false) && |
ce1b95ca | 512 | iTCO_vendor_check_noreboot_on()) { |
27c766aa | 513 | pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n"); |
c7bbcc87 | 514 | return -ENODEV; /* Cannot reset NO_REBOOT bit */ |
9e0ea345 WVS |
515 | } |
516 | ||
517 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ | |
140c91b2 | 518 | p->update_no_reboot_bit(p->no_reboot_priv, true); |
9e0ea345 | 519 | |
ce1b95ca | 520 | if (turn_SMI_watchdog_clear_off >= p->iTCO_version) { |
887c8ec7 AS |
521 | /* |
522 | * Bit 13: TCO_EN -> 0 | |
523 | * Disables TCO logic generating an SMI# | |
524 | */ | |
ce1b95ca | 525 | val32 = inl(SMI_EN(p)); |
deb9197b | 526 | val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ |
ce1b95ca | 527 | outl(val32, SMI_EN(p)); |
deb9197b | 528 | } |
9e0ea345 | 529 | |
78e45696 | 530 | if (!devm_request_region(dev, p->tco_res->start, |
c7bbcc87 | 531 | resource_size(p->tco_res), |
78e45696 | 532 | pdev->name)) { |
887c8ec7 | 533 | pr_err("I/O address 0x%04llx already in use, device disabled\n", |
ce1b95ca | 534 | (u64)TCOBASE(p)); |
c7bbcc87 | 535 | return -EBUSY; |
9e0ea345 WVS |
536 | } |
537 | ||
887c8ec7 | 538 | pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n", |
ce1b95ca | 539 | pdata->name, pdata->version, (u64)TCOBASE(p)); |
9e0ea345 WVS |
540 | |
541 | /* Clear out the (probably old) status */ | |
ce1b95ca | 542 | switch (p->iTCO_version) { |
da23b6fa | 543 | case 6: |
3b3a1c8f | 544 | case 5: |
2a7a0e9b | 545 | case 4: |
ce1b95ca GR |
546 | outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */ |
547 | outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */ | |
2a7a0e9b MF |
548 | break; |
549 | case 3: | |
ce1b95ca | 550 | outl(0x20008, TCO1_STS(p)); |
2a7a0e9b MF |
551 | break; |
552 | case 2: | |
553 | case 1: | |
554 | default: | |
ce1b95ca GR |
555 | outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */ |
556 | outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */ | |
557 | outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */ | |
2a7a0e9b | 558 | break; |
24b3a167 | 559 | } |
9e0ea345 | 560 | |
ce1b95ca GR |
561 | p->wddev.info = &ident, |
562 | p->wddev.ops = &iTCO_wdt_ops, | |
563 | p->wddev.bootstatus = 0; | |
564 | p->wddev.timeout = WATCHDOG_TIMEOUT; | |
565 | watchdog_set_nowayout(&p->wddev, nowayout); | |
78e45696 | 566 | p->wddev.parent = dev; |
ce1b95ca GR |
567 | |
568 | watchdog_set_drvdata(&p->wddev, p); | |
78e45696 | 569 | platform_set_drvdata(pdev, p); |
bff23431 | 570 | |
9e0ea345 | 571 | /* Make sure the watchdog is not running */ |
ce1b95ca | 572 | iTCO_wdt_stop(&p->wddev); |
9e0ea345 | 573 | |
0e6fa3fb AC |
574 | /* Check that the heartbeat value is within it's range; |
575 | if not reset to the default */ | |
ce1b95ca GR |
576 | if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) { |
577 | iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT); | |
bff23431 WVS |
578 | pr_info("timeout value out of range, using %d\n", |
579 | WATCHDOG_TIMEOUT); | |
9e0ea345 WVS |
580 | } |
581 | ||
d3d77b5a | 582 | watchdog_stop_on_reboot(&p->wddev); |
77d9f766 | 583 | watchdog_stop_on_unregister(&p->wddev); |
78e45696 | 584 | ret = devm_watchdog_register_device(dev, &p->wddev); |
9e0ea345 | 585 | if (ret != 0) { |
bff23431 | 586 | pr_err("cannot register watchdog device (err=%d)\n", ret); |
c7bbcc87 | 587 | return ret; |
9e0ea345 WVS |
588 | } |
589 | ||
27c766aa JP |
590 | pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n", |
591 | heartbeat, nowayout); | |
9e0ea345 WVS |
592 | |
593 | return 0; | |
9e0ea345 WVS |
594 | } |
595 | ||
f321c9cb RW |
596 | #ifdef CONFIG_PM_SLEEP |
597 | /* | |
598 | * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so | |
599 | * the watchdog cannot be pinged while in that state. In ACPI sleep states the | |
600 | * watchdog is stopped by the platform firmware. | |
601 | */ | |
602 | ||
603 | #ifdef CONFIG_ACPI | |
604 | static inline bool need_suspend(void) | |
605 | { | |
606 | return acpi_target_system_state() == ACPI_STATE_S0; | |
607 | } | |
608 | #else | |
609 | static inline bool need_suspend(void) { return true; } | |
610 | #endif | |
611 | ||
612 | static int iTCO_wdt_suspend_noirq(struct device *dev) | |
613 | { | |
ce1b95ca | 614 | struct iTCO_wdt_private *p = dev_get_drvdata(dev); |
f321c9cb RW |
615 | int ret = 0; |
616 | ||
ce1b95ca GR |
617 | p->suspended = false; |
618 | if (watchdog_active(&p->wddev) && need_suspend()) { | |
619 | ret = iTCO_wdt_stop(&p->wddev); | |
f321c9cb | 620 | if (!ret) |
ce1b95ca | 621 | p->suspended = true; |
f321c9cb RW |
622 | } |
623 | return ret; | |
624 | } | |
625 | ||
626 | static int iTCO_wdt_resume_noirq(struct device *dev) | |
627 | { | |
ce1b95ca GR |
628 | struct iTCO_wdt_private *p = dev_get_drvdata(dev); |
629 | ||
630 | if (p->suspended) | |
631 | iTCO_wdt_start(&p->wddev); | |
f321c9cb RW |
632 | |
633 | return 0; | |
634 | } | |
635 | ||
6e938f6e | 636 | static const struct dev_pm_ops iTCO_wdt_pm = { |
f321c9cb RW |
637 | .suspend_noirq = iTCO_wdt_suspend_noirq, |
638 | .resume_noirq = iTCO_wdt_resume_noirq, | |
639 | }; | |
640 | ||
641 | #define ITCO_WDT_PM_OPS (&iTCO_wdt_pm) | |
642 | #else | |
643 | #define ITCO_WDT_PM_OPS NULL | |
644 | #endif /* CONFIG_PM_SLEEP */ | |
645 | ||
3836cc0f WVS |
646 | static struct platform_driver iTCO_wdt_driver = { |
647 | .probe = iTCO_wdt_probe, | |
3836cc0f | 648 | .driver = { |
3836cc0f | 649 | .name = DRV_NAME, |
f321c9cb | 650 | .pm = ITCO_WDT_PM_OPS, |
3836cc0f WVS |
651 | }, |
652 | }; | |
653 | ||
654 | static int __init iTCO_wdt_init_module(void) | |
655 | { | |
27c766aa | 656 | pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION); |
3836cc0f | 657 | |
9616bd2a | 658 | return platform_driver_register(&iTCO_wdt_driver); |
3836cc0f WVS |
659 | } |
660 | ||
661 | static void __exit iTCO_wdt_cleanup_module(void) | |
662 | { | |
3836cc0f | 663 | platform_driver_unregister(&iTCO_wdt_driver); |
27c766aa | 664 | pr_info("Watchdog Module Unloaded\n"); |
9e0ea345 WVS |
665 | } |
666 | ||
667 | module_init(iTCO_wdt_init_module); | |
668 | module_exit(iTCO_wdt_cleanup_module); | |
669 | ||
670 | MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>"); | |
671 | MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver"); | |
3836cc0f | 672 | MODULE_VERSION(DRV_VERSION); |
9e0ea345 | 673 | MODULE_LICENSE("GPL"); |
e5de32e3 | 674 | MODULE_ALIAS("platform:" DRV_NAME); |