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d0173278 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
9e0ea345 | 2 | /* |
cb711a19 | 3 | * intel TCO Watchdog Driver |
9e0ea345 | 4 | * |
deb9197b | 5 | * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>. |
9e0ea345 | 6 | * |
9e0ea345 WVS |
7 | * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor |
8 | * provide warranty for any of this software. This material is | |
9 | * provided "AS-IS" and at no charge. | |
10 | * | |
11 | * The TCO watchdog is implemented in the following I/O controller hubs: | |
12 | * (See the intel documentation on http://developer.intel.com.) | |
cb711a19 WVS |
13 | * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) |
14 | * document number 290687-002, 298242-027: 82801BA (ICH2) | |
15 | * document number 290733-003, 290739-013: 82801CA (ICH3-S) | |
16 | * document number 290716-001, 290718-007: 82801CAM (ICH3-M) | |
17 | * document number 290744-001, 290745-025: 82801DB (ICH4) | |
18 | * document number 252337-001, 252663-008: 82801DBM (ICH4-M) | |
19 | * document number 273599-001, 273645-002: 82801E (C-ICH) | |
20 | * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) | |
21 | * document number 300641-004, 300884-013: 6300ESB | |
22 | * document number 301473-002, 301474-026: 82801F (ICH6) | |
23 | * document number 313082-001, 313075-006: 631xESB, 632xESB | |
24 | * document number 307013-003, 307014-024: 82801G (ICH7) | |
d38bd479 | 25 | * document number 322896-001, 322897-001: NM10 |
cb711a19 WVS |
26 | * document number 313056-003, 313057-017: 82801H (ICH8) |
27 | * document number 316972-004, 316973-012: 82801I (ICH9) | |
28 | * document number 319973-002, 319974-002: 82801J (ICH10) | |
3c9d8ecc | 29 | * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) |
4946f835 | 30 | * document number 320066-003, 320257-008: EP80597 (IICH) |
203f8d89 | 31 | * document number 324645-001, 324646-001: Cougar Point (CPT) |
c54fb811 | 32 | * document number TBD : Patsburg (PBG) |
203f8d89 | 33 | * document number TBD : DH89xxCC |
aa1f4652 | 34 | * document number TBD : Panther Point |
84e83c28 | 35 | * document number TBD : Lynx Point |
7fb9c1a4 | 36 | * document number TBD : Lynx Point-LP |
9e0ea345 WVS |
37 | */ |
38 | ||
39 | /* | |
40 | * Includes, defines, variables, module parameters, ... | |
41 | */ | |
42 | ||
43 | /* Module and version information */ | |
7944d3a5 | 44 | #define DRV_NAME "iTCO_wdt" |
24b3a167 | 45 | #define DRV_VERSION "1.11" |
9e0ea345 WVS |
46 | |
47 | /* Includes */ | |
f321c9cb | 48 | #include <linux/acpi.h> /* For ACPI support */ |
da23b6fa | 49 | #include <linux/bits.h> /* For BIT() */ |
3836cc0f WVS |
50 | #include <linux/module.h> /* For module specific items */ |
51 | #include <linux/moduleparam.h> /* For new moduleparam's */ | |
52 | #include <linux/types.h> /* For standard types (like size_t) */ | |
53 | #include <linux/errno.h> /* For the -ENODEV/... values */ | |
54 | #include <linux/kernel.h> /* For printk/panic/... */ | |
3836cc0f | 55 | #include <linux/watchdog.h> /* For the watchdog specific items */ |
3836cc0f WVS |
56 | #include <linux/init.h> /* For __init/__exit/... */ |
57 | #include <linux/fs.h> /* For file operations */ | |
58 | #include <linux/platform_device.h> /* For platform_driver framework */ | |
59 | #include <linux/pci.h> /* For pci functions */ | |
60 | #include <linux/ioport.h> /* For io-port access */ | |
61 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ | |
0e6fa3fb AC |
62 | #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ |
63 | #include <linux/io.h> /* For inb/outb/... */ | |
420b54de | 64 | #include <linux/platform_data/itco_wdt.h> |
25f1ca31 | 65 | #include <linux/mfd/intel_pmc_bxt.h> |
3836cc0f | 66 | |
0e6fa3fb | 67 | #include "iTCO_vendor.h" |
9e0ea345 | 68 | |
9e0ea345 | 69 | /* Address definitions for the TCO */ |
0e6fa3fb | 70 | /* TCO base address */ |
ce1b95ca | 71 | #define TCOBASE(p) ((p)->tco_res->start) |
0e6fa3fb | 72 | /* SMI Control and Enable Register */ |
ce1b95ca GR |
73 | #define SMI_EN(p) ((p)->smi_res->start) |
74 | ||
75 | #define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */ | |
76 | #define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/ | |
77 | #define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */ | |
78 | #define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */ | |
79 | #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */ | |
80 | #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */ | |
81 | #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */ | |
82 | #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */ | |
83 | #define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/ | |
9e0ea345 WVS |
84 | |
85 | /* internal variables */ | |
ce1b95ca GR |
86 | struct iTCO_wdt_private { |
87 | struct watchdog_device wddev; | |
88 | ||
0e6fa3fb AC |
89 | /* TCO version/generation */ |
90 | unsigned int iTCO_version; | |
887c8ec7 AS |
91 | struct resource *tco_res; |
92 | struct resource *smi_res; | |
24b3a167 PT |
93 | /* |
94 | * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2), | |
95 | * or memory-mapped PMC register bit 4 (TCO version 3). | |
96 | */ | |
24b3a167 | 97 | unsigned long __iomem *gcs_pmc; |
0e6fa3fb AC |
98 | /* the lock for io operations */ |
99 | spinlock_t io_lock; | |
100 | /* the PCI-device */ | |
78e45696 | 101 | struct pci_dev *pci_dev; |
f321c9cb RW |
102 | /* whether or not the watchdog has been suspended */ |
103 | bool suspended; | |
140c91b2 KS |
104 | /* no reboot API private data */ |
105 | void *no_reboot_priv; | |
f583a884 KS |
106 | /* no reboot update function pointer */ |
107 | int (*update_no_reboot_bit)(void *p, bool set); | |
ce1b95ca | 108 | }; |
9e0ea345 WVS |
109 | |
110 | /* module parameters */ | |
bff23431 WVS |
111 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */ |
112 | static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */ | |
9e0ea345 | 113 | module_param(heartbeat, int, 0); |
7e6811da PB |
114 | MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. " |
115 | "5..76 (TCO v1) or 3..614 (TCO v2), default=" | |
bff23431 | 116 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); |
9e0ea345 | 117 | |
86a1e189 WVS |
118 | static bool nowayout = WATCHDOG_NOWAYOUT; |
119 | module_param(nowayout, bool, 0); | |
0e6fa3fb AC |
120 | MODULE_PARM_DESC(nowayout, |
121 | "Watchdog cannot be stopped once started (default=" | |
122 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
e033351d | 123 | |
0d098587 | 124 | static int turn_SMI_watchdog_clear_off = 1; |
deb9197b WVS |
125 | module_param(turn_SMI_watchdog_clear_off, int, 0); |
126 | MODULE_PARM_DESC(turn_SMI_watchdog_clear_off, | |
0d098587 | 127 | "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)"); |
deb9197b | 128 | |
9e0ea345 WVS |
129 | /* |
130 | * Some TCO specific functions | |
131 | */ | |
132 | ||
24b3a167 PT |
133 | /* |
134 | * The iTCO v1 and v2's internal timer is stored as ticks which decrement | |
135 | * every 0.6 seconds. v3's internal timer is stored as seconds (some | |
136 | * datasheets incorrectly state 0.6 seconds). | |
137 | */ | |
ce1b95ca GR |
138 | static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p, |
139 | int secs) | |
9e0ea345 | 140 | { |
ce1b95ca | 141 | return p->iTCO_version == 3 ? secs : (secs * 10) / 6; |
24b3a167 PT |
142 | } |
143 | ||
ce1b95ca GR |
144 | static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p, |
145 | int ticks) | |
24b3a167 | 146 | { |
ce1b95ca | 147 | return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10; |
9e0ea345 WVS |
148 | } |
149 | ||
ce1b95ca | 150 | static inline u32 no_reboot_bit(struct iTCO_wdt_private *p) |
2a7a0e9b MF |
151 | { |
152 | u32 enable_bit; | |
153 | ||
ce1b95ca | 154 | switch (p->iTCO_version) { |
3b3a1c8f | 155 | case 5: |
2a7a0e9b MF |
156 | case 3: |
157 | enable_bit = 0x00000010; | |
158 | break; | |
159 | case 2: | |
160 | enable_bit = 0x00000020; | |
161 | break; | |
162 | case 4: | |
163 | case 1: | |
164 | default: | |
165 | enable_bit = 0x00000002; | |
166 | break; | |
167 | } | |
168 | ||
169 | return enable_bit; | |
170 | } | |
171 | ||
f583a884 | 172 | static int update_no_reboot_bit_def(void *priv, bool set) |
9e0ea345 | 173 | { |
f583a884 | 174 | return 0; |
9e0ea345 WVS |
175 | } |
176 | ||
f583a884 | 177 | static int update_no_reboot_bit_pci(void *priv, bool set) |
9e0ea345 | 178 | { |
f583a884 KS |
179 | struct iTCO_wdt_private *p = priv; |
180 | u32 val32 = 0, newval32 = 0; | |
9e0ea345 | 181 | |
f583a884 KS |
182 | pci_read_config_dword(p->pci_dev, 0xd4, &val32); |
183 | if (set) | |
184 | val32 |= no_reboot_bit(p); | |
185 | else | |
186 | val32 &= ~no_reboot_bit(p); | |
187 | pci_write_config_dword(p->pci_dev, 0xd4, val32); | |
188 | pci_read_config_dword(p->pci_dev, 0xd4, &newval32); | |
9e0ea345 | 189 | |
f583a884 KS |
190 | /* make sure the update is successful */ |
191 | if (val32 != newval32) | |
192 | return -EIO; | |
9e0ea345 | 193 | |
f583a884 KS |
194 | return 0; |
195 | } | |
196 | ||
197 | static int update_no_reboot_bit_mem(void *priv, bool set) | |
198 | { | |
199 | struct iTCO_wdt_private *p = priv; | |
200 | u32 val32 = 0, newval32 = 0; | |
201 | ||
202 | val32 = readl(p->gcs_pmc); | |
203 | if (set) | |
204 | val32 |= no_reboot_bit(p); | |
205 | else | |
206 | val32 &= ~no_reboot_bit(p); | |
207 | writel(val32, p->gcs_pmc); | |
208 | newval32 = readl(p->gcs_pmc); | |
9e0ea345 | 209 | |
f583a884 KS |
210 | /* make sure the update is successful */ |
211 | if (val32 != newval32) | |
2a7a0e9b MF |
212 | return -EIO; |
213 | ||
214 | return 0; | |
9e0ea345 WVS |
215 | } |
216 | ||
da23b6fa MW |
217 | static int update_no_reboot_bit_cnt(void *priv, bool set) |
218 | { | |
219 | struct iTCO_wdt_private *p = priv; | |
220 | u16 val, newval; | |
221 | ||
222 | val = inw(TCO1_CNT(p)); | |
223 | if (set) | |
224 | val |= BIT(0); | |
225 | else | |
226 | val &= ~BIT(0); | |
227 | outw(val, TCO1_CNT(p)); | |
228 | newval = inw(TCO1_CNT(p)); | |
229 | ||
230 | /* make sure the update is successful */ | |
231 | return val != newval ? -EIO : 0; | |
232 | } | |
233 | ||
25f1ca31 MW |
234 | static int update_no_reboot_bit_pmc(void *priv, bool set) |
235 | { | |
236 | struct intel_pmc_dev *pmc = priv; | |
237 | u32 bits = PMC_CFG_NO_REBOOT_EN; | |
238 | u32 value = set ? bits : 0; | |
239 | ||
240 | return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value); | |
241 | } | |
242 | ||
140c91b2 | 243 | static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p, |
25f1ca31 MW |
244 | struct platform_device *pdev, |
245 | struct itco_wdt_platform_data *pdata) | |
f583a884 | 246 | { |
25f1ca31 MW |
247 | if (pdata->no_reboot_use_pmc) { |
248 | struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent); | |
249 | ||
250 | p->update_no_reboot_bit = update_no_reboot_bit_pmc; | |
251 | p->no_reboot_priv = pmc; | |
140c91b2 KS |
252 | return; |
253 | } | |
254 | ||
da23b6fa MW |
255 | if (p->iTCO_version >= 6) |
256 | p->update_no_reboot_bit = update_no_reboot_bit_cnt; | |
257 | else if (p->iTCO_version >= 2) | |
f583a884 KS |
258 | p->update_no_reboot_bit = update_no_reboot_bit_mem; |
259 | else if (p->iTCO_version == 1) | |
260 | p->update_no_reboot_bit = update_no_reboot_bit_pci; | |
261 | else | |
262 | p->update_no_reboot_bit = update_no_reboot_bit_def; | |
140c91b2 KS |
263 | |
264 | p->no_reboot_priv = p; | |
f583a884 KS |
265 | } |
266 | ||
bff23431 | 267 | static int iTCO_wdt_start(struct watchdog_device *wd_dev) |
9e0ea345 | 268 | { |
ce1b95ca | 269 | struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
9e0ea345 WVS |
270 | unsigned int val; |
271 | ||
ce1b95ca | 272 | spin_lock(&p->io_lock); |
9e0ea345 | 273 | |
ce1b95ca | 274 | iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout); |
e033351d | 275 | |
9e0ea345 | 276 | /* disable chipset's NO_REBOOT bit */ |
140c91b2 | 277 | if (p->update_no_reboot_bit(p->no_reboot_priv, false)) { |
ce1b95ca | 278 | spin_unlock(&p->io_lock); |
c21172b3 | 279 | dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n"); |
9e0ea345 WVS |
280 | return -EIO; |
281 | } | |
282 | ||
7cd5b08b WVS |
283 | /* Force the timer to its reload value by writing to the TCO_RLD |
284 | register */ | |
ce1b95ca GR |
285 | if (p->iTCO_version >= 2) |
286 | outw(0x01, TCO_RLD(p)); | |
287 | else if (p->iTCO_version == 1) | |
288 | outb(0x01, TCO_RLD(p)); | |
7cd5b08b | 289 | |
9e0ea345 | 290 | /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ |
ce1b95ca | 291 | val = inw(TCO1_CNT(p)); |
9e0ea345 | 292 | val &= 0xf7ff; |
ce1b95ca GR |
293 | outw(val, TCO1_CNT(p)); |
294 | val = inw(TCO1_CNT(p)); | |
295 | spin_unlock(&p->io_lock); | |
9e0ea345 WVS |
296 | |
297 | if (val & 0x0800) | |
298 | return -1; | |
299 | return 0; | |
300 | } | |
301 | ||
bff23431 | 302 | static int iTCO_wdt_stop(struct watchdog_device *wd_dev) |
9e0ea345 | 303 | { |
ce1b95ca | 304 | struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
9e0ea345 WVS |
305 | unsigned int val; |
306 | ||
ce1b95ca | 307 | spin_lock(&p->io_lock); |
9e0ea345 | 308 | |
ce1b95ca | 309 | iTCO_vendor_pre_stop(p->smi_res); |
e033351d | 310 | |
9e0ea345 | 311 | /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ |
ce1b95ca | 312 | val = inw(TCO1_CNT(p)); |
9e0ea345 | 313 | val |= 0x0800; |
ce1b95ca GR |
314 | outw(val, TCO1_CNT(p)); |
315 | val = inw(TCO1_CNT(p)); | |
9e0ea345 WVS |
316 | |
317 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ | |
140c91b2 | 318 | p->update_no_reboot_bit(p->no_reboot_priv, true); |
9e0ea345 | 319 | |
ce1b95ca | 320 | spin_unlock(&p->io_lock); |
9e0ea345 WVS |
321 | |
322 | if ((val & 0x0800) == 0) | |
323 | return -1; | |
324 | return 0; | |
325 | } | |
326 | ||
bff23431 | 327 | static int iTCO_wdt_ping(struct watchdog_device *wd_dev) |
9e0ea345 | 328 | { |
ce1b95ca | 329 | struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
9e0ea345 | 330 | |
ce1b95ca GR |
331 | spin_lock(&p->io_lock); |
332 | ||
9e0ea345 | 333 | /* Reload the timer by writing to the TCO Timer Counter register */ |
fc61e83a | 334 | if (p->iTCO_version >= 2) { |
ce1b95ca | 335 | outw(0x01, TCO_RLD(p)); |
fc61e83a WVS |
336 | } else if (p->iTCO_version == 1) { |
337 | /* Reset the timeout status bit so that the timer | |
338 | * needs to count down twice again before rebooting */ | |
339 | outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */ | |
340 | ||
ce1b95ca | 341 | outb(0x01, TCO_RLD(p)); |
fc61e83a | 342 | } |
9e0ea345 | 343 | |
ce1b95ca | 344 | spin_unlock(&p->io_lock); |
9e0ea345 WVS |
345 | return 0; |
346 | } | |
347 | ||
bff23431 | 348 | static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t) |
9e0ea345 | 349 | { |
ce1b95ca | 350 | struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
9e0ea345 WVS |
351 | unsigned int val16; |
352 | unsigned char val8; | |
353 | unsigned int tmrval; | |
354 | ||
fc61e83a WVS |
355 | tmrval = seconds_to_ticks(p, t); |
356 | ||
6e7733ef GR |
357 | /* For TCO v1 the timer counts down twice before rebooting */ |
358 | if (p->iTCO_version == 1) | |
fc61e83a | 359 | tmrval /= 2; |
7e6811da | 360 | |
9e0ea345 WVS |
361 | /* from the specs: */ |
362 | /* "Values of 0h-3h are ignored and should not be attempted" */ | |
363 | if (tmrval < 0x04) | |
364 | return -EINVAL; | |
ce1b95ca GR |
365 | if ((p->iTCO_version >= 2 && tmrval > 0x3ff) || |
366 | (p->iTCO_version == 1 && tmrval > 0x03f)) | |
9e0ea345 WVS |
367 | return -EINVAL; |
368 | ||
369 | /* Write new heartbeat to watchdog */ | |
ce1b95ca GR |
370 | if (p->iTCO_version >= 2) { |
371 | spin_lock(&p->io_lock); | |
372 | val16 = inw(TCOv2_TMR(p)); | |
9e0ea345 WVS |
373 | val16 &= 0xfc00; |
374 | val16 |= tmrval; | |
ce1b95ca GR |
375 | outw(val16, TCOv2_TMR(p)); |
376 | val16 = inw(TCOv2_TMR(p)); | |
377 | spin_unlock(&p->io_lock); | |
9e0ea345 WVS |
378 | |
379 | if ((val16 & 0x3ff) != tmrval) | |
380 | return -EINVAL; | |
ce1b95ca GR |
381 | } else if (p->iTCO_version == 1) { |
382 | spin_lock(&p->io_lock); | |
383 | val8 = inb(TCOv1_TMR(p)); | |
9e0ea345 WVS |
384 | val8 &= 0xc0; |
385 | val8 |= (tmrval & 0xff); | |
ce1b95ca GR |
386 | outb(val8, TCOv1_TMR(p)); |
387 | val8 = inb(TCOv1_TMR(p)); | |
388 | spin_unlock(&p->io_lock); | |
9e0ea345 WVS |
389 | |
390 | if ((val8 & 0x3f) != tmrval) | |
391 | return -EINVAL; | |
392 | } | |
393 | ||
bff23431 | 394 | wd_dev->timeout = t; |
9e0ea345 WVS |
395 | return 0; |
396 | } | |
397 | ||
bff23431 | 398 | static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) |
9e0ea345 | 399 | { |
ce1b95ca | 400 | struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
9e0ea345 WVS |
401 | unsigned int val16; |
402 | unsigned char val8; | |
bff23431 | 403 | unsigned int time_left = 0; |
9e0ea345 WVS |
404 | |
405 | /* read the TCO Timer */ | |
ce1b95ca GR |
406 | if (p->iTCO_version >= 2) { |
407 | spin_lock(&p->io_lock); | |
408 | val16 = inw(TCO_RLD(p)); | |
9e0ea345 | 409 | val16 &= 0x3ff; |
ce1b95ca | 410 | spin_unlock(&p->io_lock); |
9e0ea345 | 411 | |
ce1b95ca GR |
412 | time_left = ticks_to_seconds(p, val16); |
413 | } else if (p->iTCO_version == 1) { | |
414 | spin_lock(&p->io_lock); | |
415 | val8 = inb(TCO_RLD(p)); | |
9e0ea345 | 416 | val8 &= 0x3f; |
ce1b95ca GR |
417 | if (!(inw(TCO1_STS(p)) & 0x0008)) |
418 | val8 += (inb(TCOv1_TMR(p)) & 0x3f); | |
419 | spin_unlock(&p->io_lock); | |
9e0ea345 | 420 | |
ce1b95ca | 421 | time_left = ticks_to_seconds(p, val8); |
9e0ea345 | 422 | } |
bff23431 | 423 | return time_left; |
9e0ea345 WVS |
424 | } |
425 | ||
1ae3e78c MW |
426 | static void iTCO_wdt_set_running(struct iTCO_wdt_private *p) |
427 | { | |
428 | u16 val; | |
429 | ||
430 | /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is * enabled */ | |
431 | val = inw(TCO1_CNT(p)); | |
432 | if (!(val & BIT(11))) | |
433 | set_bit(WDOG_HW_RUNNING, &p->wddev.status); | |
434 | } | |
435 | ||
9e0ea345 WVS |
436 | /* |
437 | * Kernel Interfaces | |
438 | */ | |
439 | ||
bff23431 WVS |
440 | static const struct watchdog_info ident = { |
441 | .options = WDIOF_SETTIMEOUT | | |
442 | WDIOF_KEEPALIVEPING | | |
443 | WDIOF_MAGICCLOSE, | |
444 | .firmware_version = 0, | |
445 | .identity = DRV_NAME, | |
446 | }; | |
447 | ||
448 | static const struct watchdog_ops iTCO_wdt_ops = { | |
0e6fa3fb | 449 | .owner = THIS_MODULE, |
bff23431 | 450 | .start = iTCO_wdt_start, |
5f5e1909 JH |
451 | .stop = iTCO_wdt_stop, |
452 | .ping = iTCO_wdt_ping, | |
bff23431 WVS |
453 | .set_timeout = iTCO_wdt_set_timeout, |
454 | .get_timeleft = iTCO_wdt_get_timeleft, | |
9e0ea345 WVS |
455 | }; |
456 | ||
9e0ea345 WVS |
457 | /* |
458 | * Init & exit routines | |
459 | */ | |
460 | ||
78e45696 | 461 | static int iTCO_wdt_probe(struct platform_device *pdev) |
9e0ea345 | 462 | { |
78e45696 GR |
463 | struct device *dev = &pdev->dev; |
464 | struct itco_wdt_platform_data *pdata = dev_get_platdata(dev); | |
ce1b95ca GR |
465 | struct iTCO_wdt_private *p; |
466 | unsigned long val32; | |
467 | int ret; | |
887c8ec7 | 468 | |
420b54de | 469 | if (!pdata) |
ce1b95ca | 470 | return -ENODEV; |
887c8ec7 | 471 | |
78e45696 | 472 | p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); |
ce1b95ca GR |
473 | if (!p) |
474 | return -ENOMEM; | |
887c8ec7 | 475 | |
ce1b95ca | 476 | spin_lock_init(&p->io_lock); |
887c8ec7 | 477 | |
78e45696 | 478 | p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO); |
ce1b95ca GR |
479 | if (!p->tco_res) |
480 | return -ENODEV; | |
887c8ec7 | 481 | |
ce1b95ca | 482 | p->iTCO_version = pdata->version; |
78e45696 | 483 | p->pci_dev = to_pci_dev(dev->parent); |
9e0ea345 | 484 | |
e42b0c24 MW |
485 | p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI); |
486 | if (p->smi_res) { | |
487 | /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ | |
488 | if (!devm_request_region(dev, p->smi_res->start, | |
489 | resource_size(p->smi_res), | |
490 | pdev->name)) { | |
cf813c67 | 491 | dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n", |
e42b0c24 MW |
492 | (u64)SMI_EN(p)); |
493 | return -EBUSY; | |
494 | } | |
495 | } else if (iTCO_vendorsupport || | |
496 | turn_SMI_watchdog_clear_off >= p->iTCO_version) { | |
cf813c67 | 497 | dev_err(dev, "SMI I/O resource is missing\n"); |
e42b0c24 MW |
498 | return -ENODEV; |
499 | } | |
500 | ||
25f1ca31 | 501 | iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata); |
f583a884 | 502 | |
9e0ea345 | 503 | /* |
24b3a167 PT |
504 | * Get the Memory-Mapped GCS or PMC register, we need it for the |
505 | * NO_REBOOT flag (TCO v2 and v3). | |
9e0ea345 | 506 | */ |
da23b6fa | 507 | if (p->iTCO_version >= 2 && p->iTCO_version < 6 && |
25f1ca31 | 508 | !pdata->no_reboot_use_pmc) { |
79cc4d22 | 509 | p->gcs_pmc = devm_platform_ioremap_resource(pdev, ICH_RES_MEM_GCS_PMC); |
c7bbcc87 GR |
510 | if (IS_ERR(p->gcs_pmc)) |
511 | return PTR_ERR(p->gcs_pmc); | |
9e0ea345 WVS |
512 | } |
513 | ||
514 | /* Check chipset's NO_REBOOT bit */ | |
140c91b2 | 515 | if (p->update_no_reboot_bit(p->no_reboot_priv, false) && |
ce1b95ca | 516 | iTCO_vendor_check_noreboot_on()) { |
c21172b3 | 517 | dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n"); |
c7bbcc87 | 518 | return -ENODEV; /* Cannot reset NO_REBOOT bit */ |
9e0ea345 WVS |
519 | } |
520 | ||
521 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ | |
140c91b2 | 522 | p->update_no_reboot_bit(p->no_reboot_priv, true); |
9e0ea345 | 523 | |
ce1b95ca | 524 | if (turn_SMI_watchdog_clear_off >= p->iTCO_version) { |
887c8ec7 AS |
525 | /* |
526 | * Bit 13: TCO_EN -> 0 | |
527 | * Disables TCO logic generating an SMI# | |
528 | */ | |
ce1b95ca | 529 | val32 = inl(SMI_EN(p)); |
6e7733ef | 530 | val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ |
ce1b95ca | 531 | outl(val32, SMI_EN(p)); |
deb9197b | 532 | } |
9e0ea345 | 533 | |
78e45696 | 534 | if (!devm_request_region(dev, p->tco_res->start, |
c7bbcc87 | 535 | resource_size(p->tco_res), |
78e45696 | 536 | pdev->name)) { |
c21172b3 | 537 | dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n", |
ce1b95ca | 538 | (u64)TCOBASE(p)); |
c7bbcc87 | 539 | return -EBUSY; |
9e0ea345 WVS |
540 | } |
541 | ||
c21172b3 | 542 | dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n", |
ce1b95ca | 543 | pdata->name, pdata->version, (u64)TCOBASE(p)); |
9e0ea345 WVS |
544 | |
545 | /* Clear out the (probably old) status */ | |
ce1b95ca | 546 | switch (p->iTCO_version) { |
da23b6fa | 547 | case 6: |
3b3a1c8f | 548 | case 5: |
2a7a0e9b | 549 | case 4: |
ce1b95ca GR |
550 | outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */ |
551 | outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */ | |
2a7a0e9b MF |
552 | break; |
553 | case 3: | |
ce1b95ca | 554 | outl(0x20008, TCO1_STS(p)); |
2a7a0e9b MF |
555 | break; |
556 | case 2: | |
557 | case 1: | |
558 | default: | |
ce1b95ca GR |
559 | outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */ |
560 | outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */ | |
561 | outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */ | |
2a7a0e9b | 562 | break; |
24b3a167 | 563 | } |
9e0ea345 | 564 | |
c21172b3 | 565 | p->wddev.info = &ident, |
ce1b95ca GR |
566 | p->wddev.ops = &iTCO_wdt_ops, |
567 | p->wddev.bootstatus = 0; | |
568 | p->wddev.timeout = WATCHDOG_TIMEOUT; | |
569 | watchdog_set_nowayout(&p->wddev, nowayout); | |
78e45696 | 570 | p->wddev.parent = dev; |
ce1b95ca GR |
571 | |
572 | watchdog_set_drvdata(&p->wddev, p); | |
78e45696 | 573 | platform_set_drvdata(pdev, p); |
bff23431 | 574 | |
1ae3e78c | 575 | iTCO_wdt_set_running(p); |
9e0ea345 | 576 | |
0e6fa3fb AC |
577 | /* Check that the heartbeat value is within it's range; |
578 | if not reset to the default */ | |
ce1b95ca GR |
579 | if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) { |
580 | iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT); | |
c21172b3 | 581 | dev_info(dev, "timeout value out of range, using %d\n", |
bff23431 | 582 | WATCHDOG_TIMEOUT); |
9e0ea345 WVS |
583 | } |
584 | ||
d3d77b5a | 585 | watchdog_stop_on_reboot(&p->wddev); |
77d9f766 | 586 | watchdog_stop_on_unregister(&p->wddev); |
78e45696 | 587 | ret = devm_watchdog_register_device(dev, &p->wddev); |
9e0ea345 | 588 | if (ret != 0) { |
c21172b3 | 589 | dev_err(dev, "cannot register watchdog device (err=%d)\n", ret); |
c7bbcc87 | 590 | return ret; |
9e0ea345 WVS |
591 | } |
592 | ||
c21172b3 | 593 | dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n", |
27c766aa | 594 | heartbeat, nowayout); |
9e0ea345 WVS |
595 | |
596 | return 0; | |
9e0ea345 WVS |
597 | } |
598 | ||
f321c9cb RW |
599 | /* |
600 | * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so | |
601 | * the watchdog cannot be pinged while in that state. In ACPI sleep states the | |
602 | * watchdog is stopped by the platform firmware. | |
603 | */ | |
604 | ||
605 | #ifdef CONFIG_ACPI | |
9ef95892 | 606 | static inline bool __maybe_unused need_suspend(void) |
f321c9cb RW |
607 | { |
608 | return acpi_target_system_state() == ACPI_STATE_S0; | |
609 | } | |
610 | #else | |
9ef95892 | 611 | static inline bool __maybe_unused need_suspend(void) { return true; } |
f321c9cb RW |
612 | #endif |
613 | ||
9ef95892 | 614 | static int __maybe_unused iTCO_wdt_suspend_noirq(struct device *dev) |
f321c9cb | 615 | { |
ce1b95ca | 616 | struct iTCO_wdt_private *p = dev_get_drvdata(dev); |
f321c9cb RW |
617 | int ret = 0; |
618 | ||
ce1b95ca GR |
619 | p->suspended = false; |
620 | if (watchdog_active(&p->wddev) && need_suspend()) { | |
621 | ret = iTCO_wdt_stop(&p->wddev); | |
f321c9cb | 622 | if (!ret) |
ce1b95ca | 623 | p->suspended = true; |
f321c9cb RW |
624 | } |
625 | return ret; | |
626 | } | |
627 | ||
9ef95892 | 628 | static int __maybe_unused iTCO_wdt_resume_noirq(struct device *dev) |
f321c9cb | 629 | { |
ce1b95ca GR |
630 | struct iTCO_wdt_private *p = dev_get_drvdata(dev); |
631 | ||
632 | if (p->suspended) | |
633 | iTCO_wdt_start(&p->wddev); | |
f321c9cb RW |
634 | |
635 | return 0; | |
636 | } | |
637 | ||
6e938f6e | 638 | static const struct dev_pm_ops iTCO_wdt_pm = { |
9ef95892 LX |
639 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(iTCO_wdt_suspend_noirq, |
640 | iTCO_wdt_resume_noirq) | |
f321c9cb RW |
641 | }; |
642 | ||
3836cc0f WVS |
643 | static struct platform_driver iTCO_wdt_driver = { |
644 | .probe = iTCO_wdt_probe, | |
3836cc0f | 645 | .driver = { |
3836cc0f | 646 | .name = DRV_NAME, |
9ef95892 | 647 | .pm = &iTCO_wdt_pm, |
3836cc0f WVS |
648 | }, |
649 | }; | |
650 | ||
89c866f5 | 651 | module_platform_driver(iTCO_wdt_driver); |
9e0ea345 WVS |
652 | |
653 | MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>"); | |
654 | MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver"); | |
3836cc0f | 655 | MODULE_VERSION(DRV_VERSION); |
9e0ea345 | 656 | MODULE_LICENSE("GPL"); |
e5de32e3 | 657 | MODULE_ALIAS("platform:" DRV_NAME); |