[linux-block.git] / drivers / watchdog / iTCO_wdt.c

/*
 *	intel TCO Watchdog Driver
 *
 *	(c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 *
 *	Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
 *	provide warranty for any of this software. This material is
 *	provided "AS-IS" and at no charge.
 *
 *	The TCO watchdog is implemented in the following I/O controller hubs:
 *	(See the intel documentation on http://developer.intel.com.)
 *	document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
 *	document number 290687-002, 298242-027: 82801BA (ICH2)
 *	document number 290733-003, 290739-013: 82801CA (ICH3-S)
 *	document number 290716-001, 290718-007: 82801CAM (ICH3-M)
 *	document number 290744-001, 290745-025: 82801DB (ICH4)
 *	document number 252337-001, 252663-008: 82801DBM (ICH4-M)
 *	document number 273599-001, 273645-002: 82801E (C-ICH)
 *	document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
 *	document number 300641-004, 300884-013: 6300ESB
 *	document number 301473-002, 301474-026: 82801F (ICH6)
 *	document number 313082-001, 313075-006: 631xESB, 632xESB
 *	document number 307013-003, 307014-024: 82801G (ICH7)
 *	document number 322896-001, 322897-001: NM10
 *	document number 313056-003, 313057-017: 82801H (ICH8)
 *	document number 316972-004, 316973-012: 82801I (ICH9)
 *	document number 319973-002, 319974-002: 82801J (ICH10)
 *	document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
 *	document number 320066-003, 320257-008: EP80597 (IICH)
 *	document number 324645-001, 324646-001: Cougar Point (CPT)
 *	document number TBD                   : Patsburg (PBG)
 *	document number TBD                   : DH89xxCC
 *	document number TBD                   : Panther Point
 *	document number TBD                   : Lynx Point
 *	document number TBD                   : Lynx Point-LP
 */

/*
 *	Includes, defines, variables, module parameters, ...
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

/* Module and version information */
#define DRV_NAME	"iTCO_wdt"
#define DRV_VERSION	"1.10"

/* Includes */
#include <linux/module.h>		/* For module specific items */
#include <linux/moduleparam.h>		/* For new moduleparam's */
#include <linux/types.h>		/* For standard types (like size_t) */
#include <linux/errno.h>		/* For the -ENODEV/... values */
#include <linux/kernel.h>		/* For printk/panic/... */
#include <linux/watchdog.h>		/* For the watchdog specific items */
#include <linux/init.h>			/* For __init/__exit/... */
#include <linux/fs.h>			/* For file operations */
#include <linux/platform_device.h>	/* For platform_driver framework */
#include <linux/pci.h>			/* For pci functions */
#include <linux/ioport.h>		/* For io-port access */
#include <linux/spinlock.h>		/* For spin_lock/spin_unlock/... */
#include <linux/uaccess.h>		/* For copy_to_user/put_user/... */
#include <linux/io.h>			/* For inb/outb/... */
#include <linux/mfd/core.h>
#include <linux/mfd/lpc_ich.h>

#include "iTCO_vendor.h"

/* Address definitions for the TCO */
/* TCO base address */
#define TCOBASE		(iTCO_wdt_private.tco_res->start)
/* SMI Control and Enable Register */
#define SMI_EN		(iTCO_wdt_private.smi_res->start)

#define TCO_RLD		(TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
#define TCOv1_TMR	(TCOBASE + 0x01) /* TCOv1 Timer Initial Value	*/
#define TCO_DAT_IN	(TCOBASE + 0x02) /* TCO Data In Register	*/
#define TCO_DAT_OUT	(TCOBASE + 0x03) /* TCO Data Out Register	*/
#define TCO1_STS	(TCOBASE + 0x04) /* TCO1 Status Register	*/
#define TCO2_STS	(TCOBASE + 0x06) /* TCO2 Status Register	*/
#define TCO1_CNT	(TCOBASE + 0x08) /* TCO1 Control Register	*/
#define TCO2_CNT	(TCOBASE + 0x0a) /* TCO2 Control Register	*/
#define TCOv2_TMR	(TCOBASE + 0x12) /* TCOv2 Timer Initial Value	*/

/* internal variables */
static struct {		/* this is private data for the iTCO_wdt device */
	/* TCO version/generation */
	unsigned int iTCO_version;
	struct resource *tco_res;
	struct resource *smi_res;
	struct resource *gcs_res;
	/* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
	unsigned long __iomem *gcs;
	/* the lock for io operations */
	spinlock_t io_lock;
	struct platform_device *dev;
	/* the PCI-device */
	struct pci_dev *pdev;
} iTCO_wdt_private;

/* module parameters */
#define WATCHDOG_TIMEOUT 30	/* 30 sec default heartbeat */
static int heartbeat = WATCHDOG_TIMEOUT;  /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
	"5..76 (TCO v1) or 3..614 (TCO v2), default="
				__MODULE_STRING(WATCHDOG_TIMEOUT) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
	"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static int turn_SMI_watchdog_clear_off = 1;
module_param(turn_SMI_watchdog_clear_off, int, 0);
MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
	"Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");

/*
 * Some TCO specific functions
 */

static inline unsigned int seconds_to_ticks(int seconds)
{
	/* the internal timer is stored as ticks which decrement
	 * every 0.6 seconds */
	return (seconds * 10) / 6;
}

static void iTCO_wdt_set_NO_REBOOT_bit(void)
{
	u32 val32;

	/* Set the NO_REBOOT bit: this disables reboots */
	if (iTCO_wdt_private.iTCO_version == 2) {
		val32 = readl(iTCO_wdt_private.gcs);
		val32 |= 0x00000020;
		writel(val32, iTCO_wdt_private.gcs);
	} else if (iTCO_wdt_private.iTCO_version == 1) {
		pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
		val32 |= 0x00000002;
		pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
	}
}

static int iTCO_wdt_unset_NO_REBOOT_bit(void)
{
	int ret = 0;
	u32 val32;

	/* Unset the NO_REBOOT bit: this enables reboots */
	if (iTCO_wdt_private.iTCO_version == 2) {
		val32 = readl(iTCO_wdt_private.gcs);
		val32 &= 0xffffffdf;
		writel(val32, iTCO_wdt_private.gcs);

		val32 = readl(iTCO_wdt_private.gcs);
		if (val32 & 0x00000020)
			ret = -EIO;
	} else if (iTCO_wdt_private.iTCO_version == 1) {
		pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
		val32 &= 0xfffffffd;
		pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);

		pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
		if (val32 & 0x00000002)
			ret = -EIO;
	}

	return ret; /* returns: 0 = OK, -EIO = Error */
}

static int iTCO_wdt_start(struct watchdog_device *wd_dev)
{
	unsigned int val;

	spin_lock(&iTCO_wdt_private.io_lock);

	iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);

	/* disable chipset's NO_REBOOT bit */
	if (iTCO_wdt_unset_NO_REBOOT_bit()) {
		spin_unlock(&iTCO_wdt_private.io_lock);
		pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
		return -EIO;
	}

	/* Force the timer to its reload value by writing to the TCO_RLD
	   register */
	if (iTCO_wdt_private.iTCO_version == 2)
		outw(0x01, TCO_RLD);
	else if (iTCO_wdt_private.iTCO_version == 1)
		outb(0x01, TCO_RLD);

	/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
	val = inw(TCO1_CNT);
	val &= 0xf7ff;
	outw(val, TCO1_CNT);
	val = inw(TCO1_CNT);
	spin_unlock(&iTCO_wdt_private.io_lock);

	if (val & 0x0800)
		return -1;
	return 0;
}

static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
{
	unsigned int val;

	spin_lock(&iTCO_wdt_private.io_lock);

	iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);

	/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
	val = inw(TCO1_CNT);
	val |= 0x0800;
	outw(val, TCO1_CNT);
	val = inw(TCO1_CNT);

	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
	iTCO_wdt_set_NO_REBOOT_bit();

	spin_unlock(&iTCO_wdt_private.io_lock);

	if ((val & 0x0800) == 0)
		return -1;
	return 0;
}

static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
{
	spin_lock(&iTCO_wdt_private.io_lock);

	iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);

	/* Reload the timer by writing to the TCO Timer Counter register */
	if (iTCO_wdt_private.iTCO_version == 2)
		outw(0x01, TCO_RLD);
	else if (iTCO_wdt_private.iTCO_version == 1) {
		/* Reset the timeout status bit so that the timer
		 * needs to count down twice again before rebooting */
		outw(0x0008, TCO1_STS);	/* write 1 to clear bit */

		outb(0x01, TCO_RLD);
	}

	spin_unlock(&iTCO_wdt_private.io_lock);
	return 0;
}

static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
{
	unsigned int val16;
	unsigned char val8;
	unsigned int tmrval;

	tmrval = seconds_to_ticks(t);

	/* For TCO v1 the timer counts down twice before rebooting */
	if (iTCO_wdt_private.iTCO_version == 1)
		tmrval /= 2;

	/* from the specs: */
	/* "Values of 0h-3h are ignored and should not be attempted" */
	if (tmrval < 0x04)
		return -EINVAL;
	if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
	    ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
		return -EINVAL;

	iTCO_vendor_pre_set_heartbeat(tmrval);

	/* Write new heartbeat to watchdog */
	if (iTCO_wdt_private.iTCO_version == 2) {
		spin_lock(&iTCO_wdt_private.io_lock);
		val16 = inw(TCOv2_TMR);
		val16 &= 0xfc00;
		val16 |= tmrval;
		outw(val16, TCOv2_TMR);
		val16 = inw(TCOv2_TMR);
		spin_unlock(&iTCO_wdt_private.io_lock);

		if ((val16 & 0x3ff) != tmrval)
			return -EINVAL;
	} else if (iTCO_wdt_private.iTCO_version == 1) {
		spin_lock(&iTCO_wdt_private.io_lock);
		val8 = inb(TCOv1_TMR);
		val8 &= 0xc0;
		val8 |= (tmrval & 0xff);
		outb(val8, TCOv1_TMR);
		val8 = inb(TCOv1_TMR);
		spin_unlock(&iTCO_wdt_private.io_lock);

		if ((val8 & 0x3f) != tmrval)
			return -EINVAL;
	}

	wd_dev->timeout = t;
	return 0;
}

static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
{
	unsigned int val16;
	unsigned char val8;
	unsigned int time_left = 0;

	/* read the TCO Timer */
	if (iTCO_wdt_private.iTCO_version == 2) {
		spin_lock(&iTCO_wdt_private.io_lock);
		val16 = inw(TCO_RLD);
		val16 &= 0x3ff;
		spin_unlock(&iTCO_wdt_private.io_lock);

		time_left = (val16 * 6) / 10;
	} else if (iTCO_wdt_private.iTCO_version == 1) {
		spin_lock(&iTCO_wdt_private.io_lock);
		val8 = inb(TCO_RLD);
		val8 &= 0x3f;
		if (!(inw(TCO1_STS) & 0x0008))
			val8 += (inb(TCOv1_TMR) & 0x3f);
		spin_unlock(&iTCO_wdt_private.io_lock);

		time_left = (val8 * 6) / 10;
	}
	return time_left;
}

/*
 *	Kernel Interfaces
 */

static const struct watchdog_info ident = {
	.options =		WDIOF_SETTIMEOUT |
				WDIOF_KEEPALIVEPING |
				WDIOF_MAGICCLOSE,
	.firmware_version =	0,
	.identity =		DRV_NAME,
};

static const struct watchdog_ops iTCO_wdt_ops = {
	.owner =		THIS_MODULE,
	.start =		iTCO_wdt_start,
	.stop = 		iTCO_wdt_stop,
	.ping = 		iTCO_wdt_ping,
	.set_timeout =		iTCO_wdt_set_timeout,
	.get_timeleft =		iTCO_wdt_get_timeleft,
};

static struct watchdog_device iTCO_wdt_watchdog_dev = {
	.info =		&ident,
	.ops = 		&iTCO_wdt_ops,
};

/*
 *	Init & exit routines
 */

static void iTCO_wdt_cleanup(void)
{
	/* Stop the timer before we leave */
	if (!nowayout)
		iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);

	/* Deregister */
	watchdog_unregister_device(&iTCO_wdt_watchdog_dev);

	/* release resources */
	release_region(iTCO_wdt_private.tco_res->start,
			resource_size(iTCO_wdt_private.tco_res));
	release_region(iTCO_wdt_private.smi_res->start,
			resource_size(iTCO_wdt_private.smi_res));
	if (iTCO_wdt_private.iTCO_version == 2) {
		iounmap(iTCO_wdt_private.gcs);
		release_mem_region(iTCO_wdt_private.gcs_res->start,
				resource_size(iTCO_wdt_private.gcs_res));
	}

	iTCO_wdt_private.tco_res = NULL;
	iTCO_wdt_private.smi_res = NULL;
	iTCO_wdt_private.gcs_res = NULL;
	iTCO_wdt_private.gcs = NULL;
}

static int iTCO_wdt_probe(struct platform_device *dev)
{
	int ret = -ENODEV;
	unsigned long val32;
	struct lpc_ich_info *ich_info = dev_get_platdata(&dev->dev);

	if (!ich_info)
		goto out;

	spin_lock_init(&iTCO_wdt_private.io_lock);

	iTCO_wdt_private.tco_res =
		platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
	if (!iTCO_wdt_private.tco_res)
		goto out;

	iTCO_wdt_private.smi_res =
		platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
	if (!iTCO_wdt_private.smi_res)
		goto out;

	iTCO_wdt_private.iTCO_version = ich_info->iTCO_version;
	iTCO_wdt_private.dev = dev;
	iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);

	/*
	 * Get the Memory-Mapped GCS register, we need it for the
	 * NO_REBOOT flag (TCO v2).
	 */
	if (iTCO_wdt_private.iTCO_version == 2) {
		iTCO_wdt_private.gcs_res = platform_get_resource(dev,
							IORESOURCE_MEM,
							ICH_RES_MEM_GCS);

		if (!iTCO_wdt_private.gcs_res)
			goto out;

		if (!request_mem_region(iTCO_wdt_private.gcs_res->start,
			resource_size(iTCO_wdt_private.gcs_res), dev->name)) {
			ret = -EBUSY;
			goto out;
		}
		iTCO_wdt_private.gcs = ioremap(iTCO_wdt_private.gcs_res->start,
			resource_size(iTCO_wdt_private.gcs_res));
		if (!iTCO_wdt_private.gcs) {
			ret = -EIO;
			goto unreg_gcs;
		}
	}

	/* Check chipset's NO_REBOOT bit */
	if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
		pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
		ret = -ENODEV;	/* Cannot reset NO_REBOOT bit */
		goto unmap_gcs;
	}

	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
	iTCO_wdt_set_NO_REBOOT_bit();

	/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
	if (!request_region(iTCO_wdt_private.smi_res->start,
			resource_size(iTCO_wdt_private.smi_res), dev->name)) {
		pr_err("I/O address 0x%04llx already in use, device disabled\n",
		       (u64)SMI_EN);
		ret = -EBUSY;
		goto unmap_gcs;
	}
	if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
		/*
		 * Bit 13: TCO_EN -> 0
		 * Disables TCO logic generating an SMI#
		 */
		val32 = inl(SMI_EN);
		val32 &= 0xffffdfff;	/* Turn off SMI clearing watchdog */
		outl(val32, SMI_EN);
	}

	if (!request_region(iTCO_wdt_private.tco_res->start,
			resource_size(iTCO_wdt_private.tco_res), dev->name)) {
		pr_err("I/O address 0x%04llx already in use, device disabled\n",
		       (u64)TCOBASE);
		ret = -EBUSY;
		goto unreg_smi;
	}

	pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
		ich_info->name, ich_info->iTCO_version, (u64)TCOBASE);

	/* Clear out the (probably old) status */
	outw(0x0008, TCO1_STS);	/* Clear the Time Out Status bit */
	outw(0x0002, TCO2_STS);	/* Clear SECOND_TO_STS bit */
	outw(0x0004, TCO2_STS);	/* Clear BOOT_STS bit */

	iTCO_wdt_watchdog_dev.bootstatus = 0;
	iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
	watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
	iTCO_wdt_watchdog_dev.parent = dev->dev.parent;

	/* Make sure the watchdog is not running */
	iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);

	/* Check that the heartbeat value is within it's range;
	   if not reset to the default */
	if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
		iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
		pr_info("timeout value out of range, using %d\n",
			WATCHDOG_TIMEOUT);
	}

	ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
	if (ret != 0) {
		pr_err("cannot register watchdog device (err=%d)\n", ret);
		goto unreg_tco;
	}

	pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
		heartbeat, nowayout);

	return 0;

unreg_tco:
	release_region(iTCO_wdt_private.tco_res->start,
			resource_size(iTCO_wdt_private.tco_res));
unreg_smi:
	release_region(iTCO_wdt_private.smi_res->start,
			resource_size(iTCO_wdt_private.smi_res));
unmap_gcs:
	if (iTCO_wdt_private.iTCO_version == 2)
		iounmap(iTCO_wdt_private.gcs);
unreg_gcs:
	if (iTCO_wdt_private.iTCO_version == 2)
		release_mem_region(iTCO_wdt_private.gcs_res->start,
				resource_size(iTCO_wdt_private.gcs_res));
out:
	iTCO_wdt_private.tco_res = NULL;
	iTCO_wdt_private.smi_res = NULL;
	iTCO_wdt_private.gcs_res = NULL;
	iTCO_wdt_private.gcs = NULL;

	return ret;
}

static int iTCO_wdt_remove(struct platform_device *dev)
{
	if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res)
		iTCO_wdt_cleanup();

	return 0;
}

static void iTCO_wdt_shutdown(struct platform_device *dev)
{
	iTCO_wdt_stop(NULL);
}

static struct platform_driver iTCO_wdt_driver = {
	.probe          = iTCO_wdt_probe,
	.remove         = iTCO_wdt_remove,
	.shutdown       = iTCO_wdt_shutdown,
	.driver         = {
		.owner  = THIS_MODULE,
		.name   = DRV_NAME,
	},
};

static int __init iTCO_wdt_init_module(void)
{
	int err;

	pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);

	err = platform_driver_register(&iTCO_wdt_driver);
	if (err)
		return err;

	return 0;
}

static void __exit iTCO_wdt_cleanup_module(void)
{
	platform_driver_unregister(&iTCO_wdt_driver);
	pr_info("Watchdog Module Unloaded\n");
}

module_init(iTCO_wdt_init_module);
module_exit(iTCO_wdt_cleanup_module);

MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
MODULE_VERSION(DRV_VERSION);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
9e0ea345	1	/*
cb711a19	2	* intel TCO Watchdog Driver
9e0ea345	3	*
deb9197b	4	* (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
9e0ea345 WVS	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*
	11	* Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
	12	* provide warranty for any of this software. This material is
	13	* provided "AS-IS" and at no charge.
	14	*
	15	* The TCO watchdog is implemented in the following I/O controller hubs:
	16	* (See the intel documentation on http://developer.intel.com.)
cb711a19 WVS	17	* document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
	18	* document number 290687-002, 298242-027: 82801BA (ICH2)
	19	* document number 290733-003, 290739-013: 82801CA (ICH3-S)
	20	* document number 290716-001, 290718-007: 82801CAM (ICH3-M)
	21	* document number 290744-001, 290745-025: 82801DB (ICH4)
	22	* document number 252337-001, 252663-008: 82801DBM (ICH4-M)
	23	* document number 273599-001, 273645-002: 82801E (C-ICH)
	24	* document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
	25	* document number 300641-004, 300884-013: 6300ESB
	26	* document number 301473-002, 301474-026: 82801F (ICH6)
	27	* document number 313082-001, 313075-006: 631xESB, 632xESB
	28	* document number 307013-003, 307014-024: 82801G (ICH7)
d38bd479	29	* document number 322896-001, 322897-001: NM10
cb711a19 WVS	30	* document number 313056-003, 313057-017: 82801H (ICH8)
	31	* document number 316972-004, 316973-012: 82801I (ICH9)
	32	* document number 319973-002, 319974-002: 82801J (ICH10)
3c9d8ecc	33	* document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
4946f835	34	* document number 320066-003, 320257-008: EP80597 (IICH)
203f8d89	35	* document number 324645-001, 324646-001: Cougar Point (CPT)
c54fb811	36	* document number TBD : Patsburg (PBG)
203f8d89	37	* document number TBD : DH89xxCC
aa1f4652	38	* document number TBD : Panther Point
84e83c28	39	* document number TBD : Lynx Point
7fb9c1a4	40	* document number TBD : Lynx Point-LP
9e0ea345 WVS	41	*/
	42
	43	/*
	44	* Includes, defines, variables, module parameters, ...
	45	*/
	46
27c766aa JP	47	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	48
9e0ea345	49	/* Module and version information */
7944d3a5	50	#define DRV_NAME "iTCO_wdt"
bff23431	51	#define DRV_VERSION "1.10"
9e0ea345 WVS	52
9e0ea345 WVS	53	/* Includes */
3836cc0f WVS	54	#include <linux/module.h> /* For module specific items */
	55	#include <linux/moduleparam.h> /* For new moduleparam's */
	56	#include <linux/types.h> /* For standard types (like size_t) */
	57	#include <linux/errno.h> /* For the -ENODEV/... values */
	58	#include <linux/kernel.h> /* For printk/panic/... */
3836cc0f	59	#include <linux/watchdog.h> /* For the watchdog specific items */
3836cc0f WVS	60	#include <linux/init.h> /* For __init/__exit/... */
	61	#include <linux/fs.h> /* For file operations */
	62	#include <linux/platform_device.h> /* For platform_driver framework */
	63	#include <linux/pci.h> /* For pci functions */
	64	#include <linux/ioport.h> /* For io-port access */
	65	#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
0e6fa3fb AC	66	#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
0e6fa3fb AC	67	#include <linux/io.h> /* For inb/outb/... */
887c8ec7 AS	68	#include <linux/mfd/core.h>
887c8ec7 AS	69	#include <linux/mfd/lpc_ich.h>
3836cc0f	70
0e6fa3fb	71	#include "iTCO_vendor.h"
9e0ea345	72
9e0ea345	73	/* Address definitions for the TCO */
0e6fa3fb	74	/* TCO base address */
887c8ec7	75	#define TCOBASE (iTCO_wdt_private.tco_res->start)
0e6fa3fb	76	/* SMI Control and Enable Register */
887c8ec7	77	#define SMI_EN (iTCO_wdt_private.smi_res->start)
9e0ea345	78
0a7e6582 WVS	79	#define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
	80	#define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
	81	#define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
	82	#define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
	83	#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
	84	#define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
	85	#define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
	86	#define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
	87	#define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
9e0ea345 WVS	88
9e0ea345 WVS	89	/* internal variables */
0e6fa3fb AC	90	static struct { /* this is private data for the iTCO_wdt device */
	91	/* TCO version/generation */
	92	unsigned int iTCO_version;
887c8ec7 AS	93	struct resource *tco_res;
	94	struct resource *smi_res;
	95	struct resource *gcs_res;
0e6fa3fb AC	96	/* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
	97	unsigned long __iomem *gcs;
	98	/* the lock for io operations */
	99	spinlock_t io_lock;
887c8ec7	100	struct platform_device *dev;
0e6fa3fb AC	101	/* the PCI-device */
0e6fa3fb AC	102	struct pci_dev *pdev;
9e0ea345 WVS	103	} iTCO_wdt_private;
	104
	105	/* module parameters */
bff23431 WVS	106	#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
bff23431 WVS	107	static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
9e0ea345	108	module_param(heartbeat, int, 0);
7e6811da PB	109	MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
7e6811da PB	110	"5..76 (TCO v1) or 3..614 (TCO v2), default="
bff23431	111	__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
9e0ea345	112
86a1e189 WVS	113	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	114	module_param(nowayout, bool, 0);
0e6fa3fb AC	115	MODULE_PARM_DESC(nowayout,
	116	"Watchdog cannot be stopped once started (default="
	117	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
e033351d	118
0d098587	119	static int turn_SMI_watchdog_clear_off = 1;
deb9197b WVS	120	module_param(turn_SMI_watchdog_clear_off, int, 0);
deb9197b WVS	121	MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
0d098587	122	"Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
deb9197b	123
9e0ea345 WVS	124	/*
	125	* Some TCO specific functions
	126	*/
	127
	128	static inline unsigned int seconds_to_ticks(int seconds)
	129	{
	130	/* the internal timer is stored as ticks which decrement
	131	* every 0.6 seconds */
	132	return (seconds * 10) / 6;
	133	}
	134
	135	static void iTCO_wdt_set_NO_REBOOT_bit(void)
	136	{
	137	u32 val32;
	138
	139	/* Set the NO_REBOOT bit: this disables reboots */
	140	if (iTCO_wdt_private.iTCO_version == 2) {
	141	val32 = readl(iTCO_wdt_private.gcs);
	142	val32 \|= 0x00000020;
	143	writel(val32, iTCO_wdt_private.gcs);
	144	} else if (iTCO_wdt_private.iTCO_version == 1) {
	145	pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
	146	val32 \|= 0x00000002;
	147	pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
	148	}
	149	}
	150
	151	static int iTCO_wdt_unset_NO_REBOOT_bit(void)
	152	{
	153	int ret = 0;
	154	u32 val32;
	155
	156	/* Unset the NO_REBOOT bit: this enables reboots */
	157	if (iTCO_wdt_private.iTCO_version == 2) {
	158	val32 = readl(iTCO_wdt_private.gcs);
	159	val32 &= 0xffffffdf;
	160	writel(val32, iTCO_wdt_private.gcs);
	161
	162	val32 = readl(iTCO_wdt_private.gcs);
	163	if (val32 & 0x00000020)
	164	ret = -EIO;
	165	} else if (iTCO_wdt_private.iTCO_version == 1) {
	166	pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
	167	val32 &= 0xfffffffd;
	168	pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
	169
	170	pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
	171	if (val32 & 0x00000002)
	172	ret = -EIO;
	173	}
	174
	175	return ret; /* returns: 0 = OK, -EIO = Error */
	176	}
	177
bff23431	178	static int iTCO_wdt_start(struct watchdog_device *wd_dev)
9e0ea345 WVS	179	{
	180	unsigned int val;
	181
	182	spin_lock(&iTCO_wdt_private.io_lock);
	183
bff23431	184	iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);
e033351d	185
9e0ea345 WVS	186	/* disable chipset's NO_REBOOT bit */
9e0ea345 WVS	187	if (iTCO_wdt_unset_NO_REBOOT_bit()) {
2ba7d7b3	188	spin_unlock(&iTCO_wdt_private.io_lock);
27c766aa	189	pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
9e0ea345 WVS	190	return -EIO;
	191	}
	192
7cd5b08b WVS	193	/* Force the timer to its reload value by writing to the TCO_RLD
	194	register */
	195	if (iTCO_wdt_private.iTCO_version == 2)
	196	outw(0x01, TCO_RLD);
	197	else if (iTCO_wdt_private.iTCO_version == 1)
	198	outb(0x01, TCO_RLD);
	199
9e0ea345 WVS	200	/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
	201	val = inw(TCO1_CNT);
	202	val &= 0xf7ff;
	203	outw(val, TCO1_CNT);
	204	val = inw(TCO1_CNT);
	205	spin_unlock(&iTCO_wdt_private.io_lock);
	206
	207	if (val & 0x0800)
	208	return -1;
	209	return 0;
	210	}
	211
bff23431	212	static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
9e0ea345 WVS	213	{
	214	unsigned int val;
	215
	216	spin_lock(&iTCO_wdt_private.io_lock);
	217
887c8ec7	218	iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);
e033351d	219
9e0ea345 WVS	220	/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
	221	val = inw(TCO1_CNT);
	222	val \|= 0x0800;
	223	outw(val, TCO1_CNT);
	224	val = inw(TCO1_CNT);
	225
	226	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
	227	iTCO_wdt_set_NO_REBOOT_bit();
	228
	229	spin_unlock(&iTCO_wdt_private.io_lock);
	230
	231	if ((val & 0x0800) == 0)
	232	return -1;
	233	return 0;
	234	}
	235
bff23431	236	static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
9e0ea345 WVS	237	{
	238	spin_lock(&iTCO_wdt_private.io_lock);
	239
bff23431	240	iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);
e033351d	241
9e0ea345	242	/* Reload the timer by writing to the TCO Timer Counter register */
0e6fa3fb	243	if (iTCO_wdt_private.iTCO_version == 2)
9e0ea345	244	outw(0x01, TCO_RLD);
7e6811da PB	245	else if (iTCO_wdt_private.iTCO_version == 1) {
	246	/* Reset the timeout status bit so that the timer
	247	* needs to count down twice again before rebooting */
	248	outw(0x0008, TCO1_STS); /* write 1 to clear bit */
	249
9e0ea345	250	outb(0x01, TCO_RLD);
7e6811da	251	}
9e0ea345 WVS	252
	253	spin_unlock(&iTCO_wdt_private.io_lock);
	254	return 0;
	255	}
	256
bff23431	257	static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
9e0ea345 WVS	258	{
	259	unsigned int val16;
	260	unsigned char val8;
	261	unsigned int tmrval;
	262
	263	tmrval = seconds_to_ticks(t);
7e6811da PB	264
	265	/* For TCO v1 the timer counts down twice before rebooting */
	266	if (iTCO_wdt_private.iTCO_version == 1)
	267	tmrval /= 2;
	268
9e0ea345 WVS	269	/* from the specs: */
	270	/* "Values of 0h-3h are ignored and should not be attempted" */
	271	if (tmrval < 0x04)
	272	return -EINVAL;
	273	if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) \|\|
	274	((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
	275	return -EINVAL;
	276
e033351d WVS	277	iTCO_vendor_pre_set_heartbeat(tmrval);
e033351d WVS	278
9e0ea345 WVS	279	/* Write new heartbeat to watchdog */
	280	if (iTCO_wdt_private.iTCO_version == 2) {
	281	spin_lock(&iTCO_wdt_private.io_lock);
	282	val16 = inw(TCOv2_TMR);
	283	val16 &= 0xfc00;
	284	val16 \|= tmrval;
	285	outw(val16, TCOv2_TMR);
	286	val16 = inw(TCOv2_TMR);
	287	spin_unlock(&iTCO_wdt_private.io_lock);
	288
	289	if ((val16 & 0x3ff) != tmrval)
	290	return -EINVAL;
	291	} else if (iTCO_wdt_private.iTCO_version == 1) {
	292	spin_lock(&iTCO_wdt_private.io_lock);
	293	val8 = inb(TCOv1_TMR);
	294	val8 &= 0xc0;
	295	val8 \|= (tmrval & 0xff);
	296	outb(val8, TCOv1_TMR);
	297	val8 = inb(TCOv1_TMR);
	298	spin_unlock(&iTCO_wdt_private.io_lock);
	299
	300	if ((val8 & 0x3f) != tmrval)
	301	return -EINVAL;
	302	}
	303
bff23431	304	wd_dev->timeout = t;
9e0ea345 WVS	305	return 0;
	306	}
	307
bff23431	308	static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
9e0ea345 WVS	309	{
	310	unsigned int val16;
	311	unsigned char val8;
bff23431	312	unsigned int time_left = 0;
9e0ea345 WVS	313
	314	/* read the TCO Timer */
	315	if (iTCO_wdt_private.iTCO_version == 2) {
	316	spin_lock(&iTCO_wdt_private.io_lock);
	317	val16 = inw(TCO_RLD);
	318	val16 &= 0x3ff;
	319	spin_unlock(&iTCO_wdt_private.io_lock);
	320
bff23431	321	time_left = (val16 * 6) / 10;
9e0ea345 WVS	322	} else if (iTCO_wdt_private.iTCO_version == 1) {
	323	spin_lock(&iTCO_wdt_private.io_lock);
	324	val8 = inb(TCO_RLD);
	325	val8 &= 0x3f;
7e6811da PB	326	if (!(inw(TCO1_STS) & 0x0008))
7e6811da PB	327	val8 += (inb(TCOv1_TMR) & 0x3f);
9e0ea345 WVS	328	spin_unlock(&iTCO_wdt_private.io_lock);
9e0ea345 WVS	329
bff23431	330	time_left = (val8 * 6) / 10;
9e0ea345	331	}
bff23431	332	return time_left;
9e0ea345 WVS	333	}
9e0ea345 WVS	334
9e0ea345 WVS	335	/*
	336	* Kernel Interfaces
	337	*/
	338
bff23431 WVS	339	static const struct watchdog_info ident = {
	340	.options = WDIOF_SETTIMEOUT \|
	341	WDIOF_KEEPALIVEPING \|
	342	WDIOF_MAGICCLOSE,
	343	.firmware_version = 0,
	344	.identity = DRV_NAME,
	345	};
	346
	347	static const struct watchdog_ops iTCO_wdt_ops = {
0e6fa3fb	348	.owner = THIS_MODULE,
bff23431 WVS	349	.start = iTCO_wdt_start,
	350	.stop = iTCO_wdt_stop,
	351	.ping = iTCO_wdt_ping,
	352	.set_timeout = iTCO_wdt_set_timeout,
	353	.get_timeleft = iTCO_wdt_get_timeleft,
9e0ea345 WVS	354	};
9e0ea345 WVS	355
bff23431 WVS	356	static struct watchdog_device iTCO_wdt_watchdog_dev = {
	357	.info = &ident,
	358	.ops = &iTCO_wdt_ops,
9e0ea345 WVS	359	};
9e0ea345 WVS	360
9e0ea345 WVS	361	/*
	362	* Init & exit routines
	363	*/
	364
4b12b896	365	static void iTCO_wdt_cleanup(void)
887c8ec7 AS	366	{
	367	/* Stop the timer before we leave */
	368	if (!nowayout)
bff23431	369	iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
887c8ec7 AS	370
887c8ec7 AS	371	/* Deregister */
bff23431	372	watchdog_unregister_device(&iTCO_wdt_watchdog_dev);
887c8ec7 AS	373
	374	/* release resources */
	375	release_region(iTCO_wdt_private.tco_res->start,
	376	resource_size(iTCO_wdt_private.tco_res));
	377	release_region(iTCO_wdt_private.smi_res->start,
	378	resource_size(iTCO_wdt_private.smi_res));
	379	if (iTCO_wdt_private.iTCO_version == 2) {
	380	iounmap(iTCO_wdt_private.gcs);
	381	release_mem_region(iTCO_wdt_private.gcs_res->start,
	382	resource_size(iTCO_wdt_private.gcs_res));
	383	}
	384
	385	iTCO_wdt_private.tco_res = NULL;
	386	iTCO_wdt_private.smi_res = NULL;
	387	iTCO_wdt_private.gcs_res = NULL;
	388	iTCO_wdt_private.gcs = NULL;
	389	}
	390
2d991a16	391	static int iTCO_wdt_probe(struct platform_device *dev)
9e0ea345	392	{
887c8ec7	393	int ret = -ENODEV;
12d60e28	394	unsigned long val32;
bc8fdfbe	395	struct lpc_ich_info *ich_info = dev_get_platdata(&dev->dev);
887c8ec7 AS	396
	397	if (!ich_info)
	398	goto out;
	399
	400	spin_lock_init(&iTCO_wdt_private.io_lock);
	401
	402	iTCO_wdt_private.tco_res =
	403	platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
	404	if (!iTCO_wdt_private.tco_res)
	405	goto out;
	406
	407	iTCO_wdt_private.smi_res =
	408	platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
	409	if (!iTCO_wdt_private.smi_res)
	410	goto out;
	411
	412	iTCO_wdt_private.iTCO_version = ich_info->iTCO_version;
	413	iTCO_wdt_private.dev = dev;
	414	iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);
9e0ea345 WVS	415
9e0ea345 WVS	416	/*
887c8ec7 AS	417	* Get the Memory-Mapped GCS register, we need it for the
887c8ec7 AS	418	* NO_REBOOT flag (TCO v2).
9e0ea345	419	*/
9e0ea345	420	if (iTCO_wdt_private.iTCO_version == 2) {
887c8ec7 AS	421	iTCO_wdt_private.gcs_res = platform_get_resource(dev,
	422	IORESOURCE_MEM,
	423	ICH_RES_MEM_GCS);
	424
	425	if (!iTCO_wdt_private.gcs_res)
	426	goto out;
	427
	428	if (!request_mem_region(iTCO_wdt_private.gcs_res->start,
	429	resource_size(iTCO_wdt_private.gcs_res), dev->name)) {
	430	ret = -EBUSY;
de8cd9a3 DL	431	goto out;
de8cd9a3 DL	432	}
887c8ec7 AS	433	iTCO_wdt_private.gcs = ioremap(iTCO_wdt_private.gcs_res->start,
	434	resource_size(iTCO_wdt_private.gcs_res));
	435	if (!iTCO_wdt_private.gcs) {
	436	ret = -EIO;
	437	goto unreg_gcs;
	438	}
9e0ea345 WVS	439	}
	440
	441	/* Check chipset's NO_REBOOT bit */
e033351d	442	if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
27c766aa	443	pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
9e0ea345	444	ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
887c8ec7	445	goto unmap_gcs;
9e0ea345 WVS	446	}
	447
	448	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
	449	iTCO_wdt_set_NO_REBOOT_bit();
	450
7cd5b08b	451	/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
887c8ec7 AS	452	if (!request_region(iTCO_wdt_private.smi_res->start,
	453	resource_size(iTCO_wdt_private.smi_res), dev->name)) {
	454	pr_err("I/O address 0x%04llx already in use, device disabled\n",
4b98b32a	455	(u64)SMI_EN);
887c8ec7 AS	456	ret = -EBUSY;
887c8ec7 AS	457	goto unmap_gcs;
9e0ea345	458	}
0d098587	459	if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
887c8ec7 AS	460	/*
	461	* Bit 13: TCO_EN -> 0
	462	* Disables TCO logic generating an SMI#
	463	*/
deb9197b WVS	464	val32 = inl(SMI_EN);
	465	val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
	466	outl(val32, SMI_EN);
	467	}
9e0ea345	468
887c8ec7 AS	469	if (!request_region(iTCO_wdt_private.tco_res->start,
	470	resource_size(iTCO_wdt_private.tco_res), dev->name)) {
	471	pr_err("I/O address 0x%04llx already in use, device disabled\n",
4b98b32a	472	(u64)TCOBASE);
887c8ec7 AS	473	ret = -EBUSY;
887c8ec7 AS	474	goto unreg_smi;
9e0ea345 WVS	475	}
9e0ea345 WVS	476
887c8ec7	477	pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
4b98b32a	478	ich_info->name, ich_info->iTCO_version, (u64)TCOBASE);
9e0ea345 WVS	479
9e0ea345 WVS	480	/* Clear out the (probably old) status */
7e6811da PB	481	outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
	482	outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
	483	outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
9e0ea345	484
bff23431 WVS	485	iTCO_wdt_watchdog_dev.bootstatus = 0;
	486	iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
	487	watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
	488	iTCO_wdt_watchdog_dev.parent = dev->dev.parent;
	489
9e0ea345	490	/* Make sure the watchdog is not running */
bff23431	491	iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
9e0ea345	492
0e6fa3fb AC	493	/* Check that the heartbeat value is within it's range;
0e6fa3fb AC	494	if not reset to the default */
bff23431 WVS	495	if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
	496	iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
	497	pr_info("timeout value out of range, using %d\n",
	498	WATCHDOG_TIMEOUT);
9e0ea345 WVS	499	}
9e0ea345 WVS	500
bff23431	501	ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
9e0ea345	502	if (ret != 0) {
bff23431	503	pr_err("cannot register watchdog device (err=%d)\n", ret);
887c8ec7	504	goto unreg_tco;
9e0ea345 WVS	505	}
9e0ea345 WVS	506
27c766aa JP	507	pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
27c766aa JP	508	heartbeat, nowayout);
9e0ea345 WVS	509
	510	return 0;
	511
887c8ec7 AS	512	unreg_tco:
	513	release_region(iTCO_wdt_private.tco_res->start,
	514	resource_size(iTCO_wdt_private.tco_res));
	515	unreg_smi:
	516	release_region(iTCO_wdt_private.smi_res->start,
	517	resource_size(iTCO_wdt_private.smi_res));
	518	unmap_gcs:
9e0ea345 WVS	519	if (iTCO_wdt_private.iTCO_version == 2)
9e0ea345 WVS	520	iounmap(iTCO_wdt_private.gcs);
887c8ec7	521	unreg_gcs:
9e0ea345	522	if (iTCO_wdt_private.iTCO_version == 2)
887c8ec7 AS	523	release_mem_region(iTCO_wdt_private.gcs_res->start,
	524	resource_size(iTCO_wdt_private.gcs_res));
	525	out:
	526	iTCO_wdt_private.tco_res = NULL;
	527	iTCO_wdt_private.smi_res = NULL;
	528	iTCO_wdt_private.gcs_res = NULL;
	529	iTCO_wdt_private.gcs = NULL;
9e0ea345	530
ec26985b	531	return ret;
9e0ea345 WVS	532	}
9e0ea345 WVS	533
4b12b896	534	static int iTCO_wdt_remove(struct platform_device *dev)
9e0ea345	535	{
887c8ec7	536	if (iTCO_wdt_private.tco_res \|\| iTCO_wdt_private.smi_res)
9e0ea345 WVS	537	iTCO_wdt_cleanup();
9e0ea345 WVS	538
3836cc0f WVS	539	return 0;
	540	}
	541
	542	static void iTCO_wdt_shutdown(struct platform_device *dev)
	543	{
bff23431	544	iTCO_wdt_stop(NULL);
3836cc0f WVS	545	}
3836cc0f WVS	546
3836cc0f WVS	547	static struct platform_driver iTCO_wdt_driver = {
3836cc0f WVS	548	.probe = iTCO_wdt_probe,
82268714	549	.remove = iTCO_wdt_remove,
3836cc0f	550	.shutdown = iTCO_wdt_shutdown,
3836cc0f WVS	551	.driver = {
	552	.owner = THIS_MODULE,
	553	.name = DRV_NAME,
	554	},
	555	};
	556
	557	static int __init iTCO_wdt_init_module(void)
	558	{
	559	int err;
	560
27c766aa	561	pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
3836cc0f WVS	562
	563	err = platform_driver_register(&iTCO_wdt_driver);
	564	if (err)
	565	return err;
	566
3836cc0f	567	return 0;
3836cc0f WVS	568	}
	569
	570	static void __exit iTCO_wdt_cleanup_module(void)
	571	{
3836cc0f	572	platform_driver_unregister(&iTCO_wdt_driver);
27c766aa	573	pr_info("Watchdog Module Unloaded\n");
9e0ea345 WVS	574	}
	575
	576	module_init(iTCO_wdt_init_module);
	577	module_exit(iTCO_wdt_cleanup_module);
	578
	579	MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
	580	MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
3836cc0f	581	MODULE_VERSION(DRV_VERSION);
9e0ea345	582	MODULE_LICENSE("GPL");
e5de32e3	583	MODULE_ALIAS("platform:" DRV_NAME);