[linux-2.6-block.git] / drivers / watchdog / i6300esb.c

/*
 *	i6300esb:	Watchdog timer driver for Intel 6300ESB chipset
 *
 *	(c) Copyright 2004 Google Inc.
 *	(c) Copyright 2005 David Härdeman <david@2gen.com>
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 *
 *	based on i810-tco.c which is in turn based on softdog.c
 *
 *	The timer is implemented in the following I/O controller hubs:
 *	(See the intel documentation on http://developer.intel.com.)
 *	6300ESB chip : document number 300641-004
 *
 *  2004YYZZ Ross Biro
 *	Initial version 0.01
 *  2004YYZZ Ross Biro
 *	Version 0.02
 *  20050210 David Härdeman <david@2gen.com>
 *	Ported driver to kernel 2.6
 *  20171016 Radu Rendec <rrendec@arista.com>
 *	Change driver to use the watchdog subsystem
 *	Add support for multiple 6300ESB devices
 */

/*
 *      Includes, defines, variables, module parameters, ...
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/uaccess.h>
#include <linux/io.h>

/* Module and version information */
#define ESB_MODULE_NAME "i6300ESB timer"

/* PCI configuration registers */
#define ESB_CONFIG_REG  0x60            /* Config register                   */
#define ESB_LOCK_REG    0x68            /* WDT lock register                 */

/* Memory mapped registers */
#define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
#define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
#define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg  */
#define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register               */

/* Lock register bits */
#define ESB_WDT_FUNC    (0x01 << 2)   /* Watchdog functionality            */
#define ESB_WDT_ENABLE  (0x01 << 1)   /* Enable WDT                        */
#define ESB_WDT_LOCK    (0x01 << 0)   /* Lock (nowayout)                   */

/* Config register bits */
#define ESB_WDT_REBOOT  (0x01 << 5)   /* Enable reboot on timeout          */
#define ESB_WDT_FREQ    (0x01 << 2)   /* Decrement frequency               */
#define ESB_WDT_INTTYPE (0x03 << 0)   /* Interrupt type on timer1 timeout  */

/* Reload register bits */
#define ESB_WDT_TIMEOUT (0x01 << 9)    /* Watchdog timed out                */
#define ESB_WDT_RELOAD  (0x01 << 8)    /* prevent timeout                   */

/* Magic constants */
#define ESB_UNLOCK1     0x80            /* Step 1 to unlock reset registers  */
#define ESB_UNLOCK2     0x86            /* Step 2 to unlock reset registers  */

/* module parameters */
/* 30 sec default heartbeat (1 < heartbeat < 2*1023) */
#define ESB_HEARTBEAT_MIN	1
#define ESB_HEARTBEAT_MAX	2046
#define ESB_HEARTBEAT_DEFAULT	30
#define ESB_HEARTBEAT_RANGE __MODULE_STRING(ESB_HEARTBEAT_MIN) \
	"<heartbeat<" __MODULE_STRING(ESB_HEARTBEAT_MAX)
static int heartbeat; /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
	"Watchdog heartbeat in seconds. (" ESB_HEARTBEAT_RANGE
	", default=" __MODULE_STRING(ESB_HEARTBEAT_DEFAULT) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
		"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

/* internal variables */
struct esb_dev {
	struct watchdog_device wdd;
	void __iomem *base;
	struct pci_dev *pdev;
};

#define to_esb_dev(wptr) container_of(wptr, struct esb_dev, wdd)

/*
 * Some i6300ESB specific functions
 */

/*
 * Prepare for reloading the timer by unlocking the proper registers.
 * This is performed by first writing 0x80 followed by 0x86 to the
 * reload register. After this the appropriate registers can be written
 * to once before they need to be unlocked again.
 */
static inline void esb_unlock_registers(struct esb_dev *edev)
{
	writew(ESB_UNLOCK1, ESB_RELOAD_REG(edev));
	writew(ESB_UNLOCK2, ESB_RELOAD_REG(edev));
}

static int esb_timer_start(struct watchdog_device *wdd)
{
	struct esb_dev *edev = to_esb_dev(wdd);
	int _wdd_nowayout = test_bit(WDOG_NO_WAY_OUT, &wdd->status);
	u8 val;

	esb_unlock_registers(edev);
	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
	/* Enable or Enable + Lock? */
	val = ESB_WDT_ENABLE | (_wdd_nowayout ? ESB_WDT_LOCK : 0x00);
	pci_write_config_byte(edev->pdev, ESB_LOCK_REG, val);
	return 0;
}

static int esb_timer_stop(struct watchdog_device *wdd)
{
	struct esb_dev *edev = to_esb_dev(wdd);
	u8 val;

	/* First, reset timers as suggested by the docs */
	esb_unlock_registers(edev);
	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
	/* Then disable the WDT */
	pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x0);
	pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val);

	/* Returns 0 if the timer was disabled, non-zero otherwise */
	return val & ESB_WDT_ENABLE;
}

static int esb_timer_keepalive(struct watchdog_device *wdd)
{
	struct esb_dev *edev = to_esb_dev(wdd);

	esb_unlock_registers(edev);
	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
	/* FIXME: Do we need to flush anything here? */
	return 0;
}

static int esb_timer_set_heartbeat(struct watchdog_device *wdd,
		unsigned int time)
{
	struct esb_dev *edev = to_esb_dev(wdd);
	u32 val;

	/* We shift by 9, so if we are passed a value of 1 sec,
	 * val will be 1 << 9 = 512, then write that to two
	 * timers => 2 * 512 = 1024 (which is decremented at 1KHz)
	 */
	val = time << 9;

	/* Write timer 1 */
	esb_unlock_registers(edev);
	writel(val, ESB_TIMER1_REG(edev));

	/* Write timer 2 */
	esb_unlock_registers(edev);
	writel(val, ESB_TIMER2_REG(edev));

	/* Reload */
	esb_unlock_registers(edev);
	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));

	/* FIXME: Do we need to flush everything out? */

	/* Done */
	wdd->timeout = time;
	return 0;
}

/*
 * Watchdog Subsystem Interfaces
 */

static struct watchdog_info esb_info = {
	.identity = ESB_MODULE_NAME,
	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops esb_ops = {
	.owner = THIS_MODULE,
	.start = esb_timer_start,
	.stop = esb_timer_stop,
	.set_timeout = esb_timer_set_heartbeat,
	.ping = esb_timer_keepalive,
};

/*
 * Data for PCI driver interface
 */
static const struct pci_device_id esb_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
	{ 0, },                 /* End of list */
};
MODULE_DEVICE_TABLE(pci, esb_pci_tbl);

/*
 *      Init & exit routines
 */

static unsigned char esb_getdevice(struct esb_dev *edev)
{
	if (pci_enable_device(edev->pdev)) {
		dev_err(&edev->pdev->dev, "failed to enable device\n");
		goto err_devput;
	}

	if (pci_request_region(edev->pdev, 0, ESB_MODULE_NAME)) {
		dev_err(&edev->pdev->dev, "failed to request region\n");
		goto err_disable;
	}

	edev->base = pci_ioremap_bar(edev->pdev, 0);
	if (edev->base == NULL) {
		/* Something's wrong here, BASEADDR has to be set */
		dev_err(&edev->pdev->dev, "failed to get BASEADDR\n");
		goto err_release;
	}

	/* Done */
	dev_set_drvdata(&edev->pdev->dev, edev);
	return 1;

err_release:
	pci_release_region(edev->pdev, 0);
err_disable:
	pci_disable_device(edev->pdev);
err_devput:
	return 0;
}

static void esb_initdevice(struct esb_dev *edev)
{
	u8 val1;
	u16 val2;

	/*
	 * Config register:
	 * Bit    5 : 0 = Enable WDT_OUTPUT
	 * Bit    2 : 0 = set the timer frequency to the PCI clock
	 * divided by 2^15 (approx 1KHz).
	 * Bits 1:0 : 11 = WDT_INT_TYPE Disabled.
	 * The watchdog has two timers, it can be setup so that the
	 * expiry of timer1 results in an interrupt and the expiry of
	 * timer2 results in a reboot. We set it to not generate
	 * any interrupts as there is not much we can do with it
	 * right now.
	 */
	pci_write_config_word(edev->pdev, ESB_CONFIG_REG, 0x0003);

	/* Check that the WDT isn't already locked */
	pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val1);
	if (val1 & ESB_WDT_LOCK)
		dev_warn(&edev->pdev->dev, "nowayout already set\n");

	/* Set the timer to watchdog mode and disable it for now */
	pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x00);

	/* Check if the watchdog was previously triggered */
	esb_unlock_registers(edev);
	val2 = readw(ESB_RELOAD_REG(edev));
	if (val2 & ESB_WDT_TIMEOUT)
		edev->wdd.bootstatus = WDIOF_CARDRESET;

	/* Reset WDT_TIMEOUT flag and timers */
	esb_unlock_registers(edev);
	writew((ESB_WDT_TIMEOUT | ESB_WDT_RELOAD), ESB_RELOAD_REG(edev));

	/* And set the correct timeout value */
	esb_timer_set_heartbeat(&edev->wdd, edev->wdd.timeout);
}

static int esb_probe(struct pci_dev *pdev,
		const struct pci_device_id *ent)
{
	struct esb_dev *edev;
	int ret;

	edev = devm_kzalloc(&pdev->dev, sizeof(*edev), GFP_KERNEL);
	if (!edev)
		return -ENOMEM;

	/* Check whether or not the hardware watchdog is there */
	edev->pdev = pdev;
	if (!esb_getdevice(edev))
		return -ENODEV;

	/* Initialize the watchdog and make sure it does not run */
	edev->wdd.info = &esb_info;
	edev->wdd.ops = &esb_ops;
	edev->wdd.min_timeout = ESB_HEARTBEAT_MIN;
	edev->wdd.max_timeout = ESB_HEARTBEAT_MAX;
	edev->wdd.timeout = ESB_HEARTBEAT_DEFAULT;
	if (watchdog_init_timeout(&edev->wdd, heartbeat, NULL))
		dev_info(&pdev->dev,
			"heartbeat value must be " ESB_HEARTBEAT_RANGE
			", using %u\n", edev->wdd.timeout);
	watchdog_set_nowayout(&edev->wdd, nowayout);
	watchdog_stop_on_reboot(&edev->wdd);
	watchdog_stop_on_unregister(&edev->wdd);
	esb_initdevice(edev);

	/* Register the watchdog so that userspace has access to it */
	ret = watchdog_register_device(&edev->wdd);
	if (ret != 0) {
		dev_err(&pdev->dev,
			"cannot register watchdog device (err=%d)\n", ret);
		goto err_unmap;
	}
	dev_info(&pdev->dev,
		"initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
		edev->base, edev->wdd.timeout, nowayout);
	return 0;

err_unmap:
	iounmap(edev->base);
	pci_release_region(edev->pdev, 0);
	pci_disable_device(edev->pdev);
	return ret;
}

static void esb_remove(struct pci_dev *pdev)
{
	struct esb_dev *edev = dev_get_drvdata(&pdev->dev);

	watchdog_unregister_device(&edev->wdd);
	iounmap(edev->base);
	pci_release_region(edev->pdev, 0);
	pci_disable_device(edev->pdev);
}

static struct pci_driver esb_driver = {
	.name		= ESB_MODULE_NAME,
	.id_table	= esb_pci_tbl,
	.probe          = esb_probe,
	.remove         = esb_remove,
};

module_pci_driver(esb_driver);

MODULE_AUTHOR("Ross Biro and David Härdeman");
MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
MODULE_LICENSE("GPL");
Commit	Line	Data
cc90ef0f	1	/*
abda5c8b	2	* i6300esb: Watchdog timer driver for Intel 6300ESB chipset
cc90ef0f DH	3	*
cc90ef0f DH	4	* (c) Copyright 2004 Google Inc.
96de0e25	5	* (c) Copyright 2005 David Härdeman <david@2gen.com>
cc90ef0f DH	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
	11	*
7944d3a5	12	* based on i810-tco.c which is in turn based on softdog.c
cc90ef0f	13	*
7944d3a5 WVS	14	* The timer is implemented in the following I/O controller hubs:
7944d3a5 WVS	15	* (See the intel documentation on http://developer.intel.com.)
0426fd0d	16	* 6300ESB chip : document number 300641-004
cc90ef0f DH	17	*
	18	* 2004YYZZ Ross Biro
	19	* Initial version 0.01
	20	* 2004YYZZ Ross Biro
7944d3a5	21	* Version 0.02
96de0e25	22	* 20050210 David Härdeman <david@2gen.com>
7944d3a5	23	* Ported driver to kernel 2.6
7af4ac87 RR	24	* 20171016 Radu Rendec <rrendec@arista.com>
7af4ac87 RR	25	* Change driver to use the watchdog subsystem
cf73120b	26	* Add support for multiple 6300ESB devices
cc90ef0f DH	27	*/
	28
	29	/*
	30	* Includes, defines, variables, module parameters, ...
	31	*/
	32
	33	#include <linux/module.h>
	34	#include <linux/types.h>
	35	#include <linux/kernel.h>
	36	#include <linux/fs.h>
	37	#include <linux/mm.h>
	38	#include <linux/miscdevice.h>
	39	#include <linux/watchdog.h>
cc90ef0f DH	40	#include <linux/pci.h>
cc90ef0f DH	41	#include <linux/ioport.h>
0829291e AC	42	#include <linux/uaccess.h>
0829291e AC	43	#include <linux/io.h>
cc90ef0f	44
cc90ef0f	45	/* Module and version information */
cc90ef0f	46	#define ESB_MODULE_NAME "i6300ESB timer"
cc90ef0f	47
abda5c8b DH	48	/* PCI configuration registers */
	49	#define ESB_CONFIG_REG 0x60 /* Config register */
	50	#define ESB_LOCK_REG 0x68 /* WDT lock register */
	51
	52	/* Memory mapped registers */
cf73120b RR	53	#define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
	54	#define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
	55	#define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
	56	#define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
abda5c8b DH	57
abda5c8b DH	58	/* Lock register bits */
0829291e AC	59	#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
	60	#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
	61	#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
abda5c8b DH	62
abda5c8b DH	63	/* Config register bits */
0829291e AC	64	#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
0829291e AC	65	#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
39f3be72	66	#define ESB_WDT_INTTYPE (0x03 << 0) /* Interrupt type on timer1 timeout */
abda5c8b DH	67
abda5c8b DH	68	/* Reload register bits */
31838d9d	69	#define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */
0829291e	70	#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
abda5c8b DH	71
	72	/* Magic constants */
	73	#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
	74	#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
	75
cc90ef0f	76	/* module parameters */
0829291e	77	/* 30 sec default heartbeat (1 < heartbeat < 21023) /
568d6015 RR	78	#define ESB_HEARTBEAT_MIN 1
	79	#define ESB_HEARTBEAT_MAX 2046
	80	#define ESB_HEARTBEAT_DEFAULT 30
	81	#define ESB_HEARTBEAT_RANGE __MODULE_STRING(ESB_HEARTBEAT_MIN) \
	82	"<heartbeat<" __MODULE_STRING(ESB_HEARTBEAT_MAX)
7af4ac87	83	static int heartbeat; /* in seconds */
cc90ef0f	84	module_param(heartbeat, int, 0);
0829291e	85	MODULE_PARM_DESC(heartbeat,
568d6015 RR	86	"Watchdog heartbeat in seconds. (" ESB_HEARTBEAT_RANGE
568d6015 RR	87	", default=" __MODULE_STRING(ESB_HEARTBEAT_DEFAULT) ")");
cc90ef0f	88
86a1e189 WVS	89	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	90	module_param(nowayout, bool, 0);
0829291e AC	91	MODULE_PARM_DESC(nowayout,
	92	"Watchdog cannot be stopped once started (default="
	93	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
cc90ef0f	94
cf73120b RR	95	/* internal variables */
	96	struct esb_dev {
	97	struct watchdog_device wdd;
	98	void __iomem *base;
	99	struct pci_dev *pdev;
	100	};
	101
	102	#define to_esb_dev(wptr) container_of(wptr, struct esb_dev, wdd)
	103
cc90ef0f DH	104	/*
	105	* Some i6300ESB specific functions
	106	*/
	107
	108	/*
	109	* Prepare for reloading the timer by unlocking the proper registers.
	110	* This is performed by first writing 0x80 followed by 0x86 to the
	111	* reload register. After this the appropriate registers can be written
	112	* to once before they need to be unlocked again.
	113	*/
cf73120b	114	static inline void esb_unlock_registers(struct esb_dev *edev)
7944d3a5	115	{
cf73120b RR	116	writew(ESB_UNLOCK1, ESB_RELOAD_REG(edev));
cf73120b RR	117	writew(ESB_UNLOCK2, ESB_RELOAD_REG(edev));
cc90ef0f DH	118	}
cc90ef0f DH	119
7af4ac87	120	static int esb_timer_start(struct watchdog_device *wdd)
cc90ef0f	121	{
cf73120b	122	struct esb_dev *edev = to_esb_dev(wdd);
7af4ac87	123	int _wdd_nowayout = test_bit(WDOG_NO_WAY_OUT, &wdd->status);
cc90ef0f DH	124	u8 val;
cc90ef0f DH	125
cf73120b RR	126	esb_unlock_registers(edev);
cf73120b RR	127	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
cc90ef0f	128	/* Enable or Enable + Lock? */
7af4ac87	129	val = ESB_WDT_ENABLE \| (_wdd_nowayout ? ESB_WDT_LOCK : 0x00);
cf73120b	130	pci_write_config_byte(edev->pdev, ESB_LOCK_REG, val);
3b9d49ee	131	return 0;
cc90ef0f DH	132	}
cc90ef0f DH	133
7af4ac87	134	static int esb_timer_stop(struct watchdog_device *wdd)
cc90ef0f	135	{
cf73120b	136	struct esb_dev *edev = to_esb_dev(wdd);
cc90ef0f DH	137	u8 val;
cc90ef0f DH	138
cc90ef0f	139	/* First, reset timers as suggested by the docs */
cf73120b RR	140	esb_unlock_registers(edev);
cf73120b RR	141	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
cc90ef0f	142	/* Then disable the WDT */
cf73120b RR	143	pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x0);
cf73120b RR	144	pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val);
cc90ef0f DH	145
cc90ef0f DH	146	/* Returns 0 if the timer was disabled, non-zero otherwise */
fc8a9d83	147	return val & ESB_WDT_ENABLE;
cc90ef0f DH	148	}
cc90ef0f DH	149
7af4ac87	150	static int esb_timer_keepalive(struct watchdog_device *wdd)
cc90ef0f	151	{
cf73120b RR	152	struct esb_dev *edev = to_esb_dev(wdd);
	153
	154	esb_unlock_registers(edev);
	155	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
0829291e	156	/* FIXME: Do we need to flush anything here? */
7af4ac87	157	return 0;
cc90ef0f DH	158	}
cc90ef0f DH	159
7af4ac87 RR	160	static int esb_timer_set_heartbeat(struct watchdog_device *wdd,
7af4ac87 RR	161	unsigned int time)
cc90ef0f	162	{
cf73120b	163	struct esb_dev *edev = to_esb_dev(wdd);
cc90ef0f DH	164	u32 val;
cc90ef0f DH	165
cc90ef0f DH	166	/* We shift by 9, so if we are passed a value of 1 sec,
	167	* val will be 1 << 9 = 512, then write that to two
	168	* timers => 2 * 512 = 1024 (which is decremented at 1KHz)
	169	*/
	170	val = time << 9;
	171
	172	/* Write timer 1 */
cf73120b RR	173	esb_unlock_registers(edev);
cf73120b RR	174	writel(val, ESB_TIMER1_REG(edev));
cc90ef0f DH	175
cc90ef0f DH	176	/* Write timer 2 */
cf73120b RR	177	esb_unlock_registers(edev);
cf73120b RR	178	writel(val, ESB_TIMER2_REG(edev));
cc90ef0f	179
0829291e	180	/* Reload */
cf73120b RR	181	esb_unlock_registers(edev);
cf73120b RR	182	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
cc90ef0f DH	183
	184	/* FIXME: Do we need to flush everything out? */
	185
	186	/* Done */
7af4ac87	187	wdd->timeout = time;
cc90ef0f DH	188	return 0;
	189	}
	190
cc90ef0f	191	/*
7af4ac87	192	* Watchdog Subsystem Interfaces
cc90ef0f DH	193	*/
cc90ef0f DH	194
7af4ac87 RR	195	static struct watchdog_info esb_info = {
	196	.identity = ESB_MODULE_NAME,
	197	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE,
	198	};
cc90ef0f	199
7af4ac87	200	static const struct watchdog_ops esb_ops = {
0829291e	201	.owner = THIS_MODULE,
7af4ac87 RR	202	.start = esb_timer_start,
	203	.stop = esb_timer_stop,
	204	.set_timeout = esb_timer_set_heartbeat,
	205	.ping = esb_timer_keepalive,
cc90ef0f DH	206	};
cc90ef0f DH	207
cc90ef0f DH	208	/*
cc90ef0f DH	209	* Data for PCI driver interface
cc90ef0f	210	*/
bc17f9dc	211	static const struct pci_device_id esb_pci_tbl[] = {
0829291e AC	212	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
0829291e AC	213	{ 0, }, /* End of list */
cc90ef0f	214	};
0829291e	215	MODULE_DEVICE_TABLE(pci, esb_pci_tbl);
cc90ef0f DH	216
	217	/*
	218	* Init & exit routines
	219	*/
	220
cf73120b	221	static unsigned char esb_getdevice(struct esb_dev *edev)
cc90ef0f	222	{
cf73120b RR	223	if (pci_enable_device(edev->pdev)) {
cf73120b RR	224	dev_err(&edev->pdev->dev, "failed to enable device\n");
fc8a9d83 WVS	225	goto err_devput;
fc8a9d83 WVS	226	}
cc90ef0f	227
cf73120b RR	228	if (pci_request_region(edev->pdev, 0, ESB_MODULE_NAME)) {
cf73120b RR	229	dev_err(&edev->pdev->dev, "failed to request region\n");
fc8a9d83 WVS	230	goto err_disable;
fc8a9d83 WVS	231	}
cc90ef0f	232
cf73120b RR	233	edev->base = pci_ioremap_bar(edev->pdev, 0);
cf73120b RR	234	if (edev->base == NULL) {
fc8a9d83	235	/* Something's wrong here, BASEADDR has to be set */
cf73120b	236	dev_err(&edev->pdev->dev, "failed to get BASEADDR\n");
fc8a9d83 WVS	237	goto err_release;
	238	}
	239
	240	/* Done */
cf73120b	241	dev_set_drvdata(&edev->pdev->dev, edev);
fc8a9d83	242	return 1;
cc90ef0f DH	243
cc90ef0f DH	244	err_release:
cf73120b	245	pci_release_region(edev->pdev, 0);
cc90ef0f	246	err_disable:
cf73120b	247	pci_disable_device(edev->pdev);
811f9991	248	err_devput:
cc90ef0f DH	249	return 0;
	250	}
	251
cf73120b	252	static void esb_initdevice(struct esb_dev *edev)
fc8a9d83 WVS	253	{
	254	u8 val1;
	255	u16 val2;
	256
	257	/*
	258	* Config register:
	259	* Bit 5 : 0 = Enable WDT_OUTPUT
	260	* Bit 2 : 0 = set the timer frequency to the PCI clock
	261	* divided by 2^15 (approx 1KHz).
	262	* Bits 1:0 : 11 = WDT_INT_TYPE Disabled.
	263	* The watchdog has two timers, it can be setup so that the
	264	* expiry of timer1 results in an interrupt and the expiry of
	265	* timer2 results in a reboot. We set it to not generate
	266	* any interrupts as there is not much we can do with it
	267	* right now.
	268	*/
cf73120b	269	pci_write_config_word(edev->pdev, ESB_CONFIG_REG, 0x0003);
fc8a9d83 WVS	270
fc8a9d83 WVS	271	/* Check that the WDT isn't already locked */
cf73120b	272	pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val1);
fc8a9d83	273	if (val1 & ESB_WDT_LOCK)
cf73120b	274	dev_warn(&edev->pdev->dev, "nowayout already set\n");
fc8a9d83 WVS	275
fc8a9d83 WVS	276	/* Set the timer to watchdog mode and disable it for now */
cf73120b	277	pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x00);
fc8a9d83 WVS	278
fc8a9d83 WVS	279	/* Check if the watchdog was previously triggered */
cf73120b RR	280	esb_unlock_registers(edev);
cf73120b RR	281	val2 = readw(ESB_RELOAD_REG(edev));
fc8a9d83	282	if (val2 & ESB_WDT_TIMEOUT)
cf73120b	283	edev->wdd.bootstatus = WDIOF_CARDRESET;
fc8a9d83 WVS	284
fc8a9d83 WVS	285	/* Reset WDT_TIMEOUT flag and timers */
cf73120b RR	286	esb_unlock_registers(edev);
cf73120b RR	287	writew((ESB_WDT_TIMEOUT \| ESB_WDT_RELOAD), ESB_RELOAD_REG(edev));
fc8a9d83 WVS	288
fc8a9d83 WVS	289	/* And set the correct timeout value */
cf73120b	290	esb_timer_set_heartbeat(&edev->wdd, edev->wdd.timeout);
fc8a9d83 WVS	291	}
fc8a9d83 WVS	292
2d991a16	293	static int esb_probe(struct pci_dev *pdev,
2786095a	294	const struct pci_device_id *ent)
cc90ef0f	295	{
cf73120b	296	struct esb_dev *edev;
0829291e AC	297	int ret;
0829291e AC	298
cf73120b RR	299	edev = devm_kzalloc(&pdev->dev, sizeof(*edev), GFP_KERNEL);
	300	if (!edev)
	301	return -ENOMEM;
2786095a	302
0829291e	303	/* Check whether or not the hardware watchdog is there */
cf73120b RR	304	edev->pdev = pdev;
cf73120b RR	305	if (!esb_getdevice(edev))
0829291e AC	306	return -ENODEV;
0829291e AC	307
fc8a9d83	308	/* Initialize the watchdog and make sure it does not run */
cf73120b RR	309	edev->wdd.info = &esb_info;
cf73120b RR	310	edev->wdd.ops = &esb_ops;
568d6015 RR	311	edev->wdd.min_timeout = ESB_HEARTBEAT_MIN;
	312	edev->wdd.max_timeout = ESB_HEARTBEAT_MAX;
	313	edev->wdd.timeout = ESB_HEARTBEAT_DEFAULT;
cf73120b RR	314	if (watchdog_init_timeout(&edev->wdd, heartbeat, NULL))
cf73120b RR	315	dev_info(&pdev->dev,
568d6015 RR	316	"heartbeat value must be " ESB_HEARTBEAT_RANGE
568d6015 RR	317	", using %u\n", edev->wdd.timeout);
cf73120b RR	318	watchdog_set_nowayout(&edev->wdd, nowayout);
	319	watchdog_stop_on_reboot(&edev->wdd);
	320	watchdog_stop_on_unregister(&edev->wdd);
	321	esb_initdevice(edev);
fc8a9d83 WVS	322
fc8a9d83 WVS	323	/* Register the watchdog so that userspace has access to it */
cf73120b	324	ret = watchdog_register_device(&edev->wdd);
0829291e	325	if (ret != 0) {
7af4ac87 RR	326	dev_err(&pdev->dev,
7af4ac87 RR	327	"cannot register watchdog device (err=%d)\n", ret);
0426fd0d	328	goto err_unmap;
0829291e	329	}
7af4ac87 RR	330	dev_info(&pdev->dev,
7af4ac87 RR	331	"initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
cf73120b	332	edev->base, edev->wdd.timeout, nowayout);
0829291e	333	return 0;
cc90ef0f	334
cc90ef0f	335	err_unmap:
cf73120b RR	336	iounmap(edev->base);
	337	pci_release_region(edev->pdev, 0);
	338	pci_disable_device(edev->pdev);
0829291e	339	return ret;
cc90ef0f DH	340	}
cc90ef0f DH	341
4b12b896	342	static void esb_remove(struct pci_dev *pdev)
cc90ef0f	343	{
cf73120b RR	344	struct esb_dev *edev = dev_get_drvdata(&pdev->dev);
	345
	346	watchdog_unregister_device(&edev->wdd);
	347	iounmap(edev->base);
	348	pci_release_region(edev->pdev, 0);
	349	pci_disable_device(edev->pdev);
0426fd0d WVS	350	}
0426fd0d WVS	351
2786095a WVS	352	static struct pci_driver esb_driver = {
	353	.name = ESB_MODULE_NAME,
	354	.id_table = esb_pci_tbl,
0426fd0d	355	.probe = esb_probe,
82268714	356	.remove = esb_remove,
0426fd0d WVS	357	};
0426fd0d WVS	358
5ce9c371	359	module_pci_driver(esb_driver);
cc90ef0f	360
96de0e25	361	MODULE_AUTHOR("Ross Biro and David Härdeman");
cc90ef0f DH	362	MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
cc90ef0f DH	363	MODULE_LICENSE("GPL");