Commit | Line | Data |
---|---|---|
cc90ef0f | 1 | /* |
abda5c8b | 2 | * i6300esb: Watchdog timer driver for Intel 6300ESB chipset |
cc90ef0f DH |
3 | * |
4 | * (c) Copyright 2004 Google Inc. | |
96de0e25 | 5 | * (c) Copyright 2005 David Härdeman <david@2gen.com> |
cc90ef0f DH |
6 | * |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | * | |
abda5c8b | 12 | * based on i810-tco.c which is in turn based on softdog.c |
cc90ef0f DH |
13 | * |
14 | * The timer is implemented in the following I/O controller hubs: | |
15 | * (See the intel documentation on http://developer.intel.com.) | |
16 | * 6300ESB chip : document number 300641-003 | |
17 | * | |
18 | * 2004YYZZ Ross Biro | |
19 | * Initial version 0.01 | |
20 | * 2004YYZZ Ross Biro | |
21 | * Version 0.02 | |
96de0e25 | 22 | * 20050210 David Härdeman <david@2gen.com> |
cc90ef0f DH |
23 | * Ported driver to kernel 2.6 |
24 | */ | |
25 | ||
26 | /* | |
27 | * Includes, defines, variables, module parameters, ... | |
28 | */ | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/types.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/fs.h> | |
34 | #include <linux/mm.h> | |
35 | #include <linux/miscdevice.h> | |
36 | #include <linux/watchdog.h> | |
37 | #include <linux/reboot.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/ioport.h> | |
0829291e AC |
41 | #include <linux/uaccess.h> |
42 | #include <linux/io.h> | |
cc90ef0f | 43 | |
cc90ef0f DH |
44 | /* Module and version information */ |
45 | #define ESB_VERSION "0.03" | |
46 | #define ESB_MODULE_NAME "i6300ESB timer" | |
47 | #define ESB_DRIVER_NAME ESB_MODULE_NAME ", v" ESB_VERSION | |
48 | #define PFX ESB_MODULE_NAME ": " | |
49 | ||
abda5c8b DH |
50 | /* PCI configuration registers */ |
51 | #define ESB_CONFIG_REG 0x60 /* Config register */ | |
52 | #define ESB_LOCK_REG 0x68 /* WDT lock register */ | |
53 | ||
54 | /* Memory mapped registers */ | |
55 | #define ESB_TIMER1_REG BASEADDR + 0x00 /* Timer1 value after each reset */ | |
56 | #define ESB_TIMER2_REG BASEADDR + 0x04 /* Timer2 value after each reset */ | |
57 | #define ESB_GINTSR_REG BASEADDR + 0x08 /* General Interrupt Status Register */ | |
58 | #define ESB_RELOAD_REG BASEADDR + 0x0c /* Reload register */ | |
59 | ||
60 | /* Lock register bits */ | |
0829291e AC |
61 | #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */ |
62 | #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */ | |
63 | #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */ | |
abda5c8b DH |
64 | |
65 | /* Config register bits */ | |
0829291e AC |
66 | #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */ |
67 | #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */ | |
68 | #define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */ | |
abda5c8b DH |
69 | |
70 | /* Reload register bits */ | |
0829291e | 71 | #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */ |
abda5c8b DH |
72 | |
73 | /* Magic constants */ | |
74 | #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */ | |
75 | #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */ | |
76 | ||
cc90ef0f DH |
77 | /* internal variables */ |
78 | static void __iomem *BASEADDR; | |
c7dfd0cc | 79 | static DEFINE_SPINLOCK(esb_lock); /* Guards the hardware */ |
cc90ef0f DH |
80 | static unsigned long timer_alive; |
81 | static struct pci_dev *esb_pci; | |
82 | static unsigned short triggered; /* The status of the watchdog upon boot */ | |
83 | static char esb_expect_close; | |
84 | ||
85 | /* module parameters */ | |
0829291e AC |
86 | /* 30 sec default heartbeat (1 < heartbeat < 2*1023) */ |
87 | #define WATCHDOG_HEARTBEAT 30 | |
cc90ef0f | 88 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ |
0829291e | 89 | |
cc90ef0f | 90 | module_param(heartbeat, int, 0); |
0829291e AC |
91 | MODULE_PARM_DESC(heartbeat, |
92 | "Watchdog heartbeat in seconds. (1<heartbeat<2046, default=" | |
93 | __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | |
cc90ef0f | 94 | |
811f9991 | 95 | static int nowayout = WATCHDOG_NOWAYOUT; |
cc90ef0f | 96 | module_param(nowayout, int, 0); |
0829291e AC |
97 | MODULE_PARM_DESC(nowayout, |
98 | "Watchdog cannot be stopped once started (default=" | |
99 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
cc90ef0f DH |
100 | |
101 | /* | |
102 | * Some i6300ESB specific functions | |
103 | */ | |
104 | ||
105 | /* | |
106 | * Prepare for reloading the timer by unlocking the proper registers. | |
107 | * This is performed by first writing 0x80 followed by 0x86 to the | |
108 | * reload register. After this the appropriate registers can be written | |
109 | * to once before they need to be unlocked again. | |
110 | */ | |
111 | static inline void esb_unlock_registers(void) { | |
0829291e AC |
112 | writeb(ESB_UNLOCK1, ESB_RELOAD_REG); |
113 | writeb(ESB_UNLOCK2, ESB_RELOAD_REG); | |
cc90ef0f DH |
114 | } |
115 | ||
116 | static void esb_timer_start(void) | |
117 | { | |
118 | u8 val; | |
119 | ||
120 | /* Enable or Enable + Lock? */ | |
28562af3 | 121 | val = 0x02 | (nowayout ? 0x01 : 0x00); |
0829291e | 122 | pci_write_config_byte(esb_pci, ESB_LOCK_REG, val); |
cc90ef0f DH |
123 | } |
124 | ||
125 | static int esb_timer_stop(void) | |
126 | { | |
127 | u8 val; | |
128 | ||
129 | spin_lock(&esb_lock); | |
130 | /* First, reset timers as suggested by the docs */ | |
131 | esb_unlock_registers(); | |
ce2f50b4 | 132 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); |
cc90ef0f DH |
133 | /* Then disable the WDT */ |
134 | pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0); | |
135 | pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val); | |
136 | spin_unlock(&esb_lock); | |
137 | ||
138 | /* Returns 0 if the timer was disabled, non-zero otherwise */ | |
139 | return (val & 0x01); | |
140 | } | |
141 | ||
142 | static void esb_timer_keepalive(void) | |
143 | { | |
144 | spin_lock(&esb_lock); | |
145 | esb_unlock_registers(); | |
ce2f50b4 | 146 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); |
0829291e | 147 | /* FIXME: Do we need to flush anything here? */ |
cc90ef0f DH |
148 | spin_unlock(&esb_lock); |
149 | } | |
150 | ||
151 | static int esb_timer_set_heartbeat(int time) | |
152 | { | |
153 | u32 val; | |
154 | ||
155 | if (time < 0x1 || time > (2 * 0x03ff)) | |
156 | return -EINVAL; | |
157 | ||
158 | spin_lock(&esb_lock); | |
159 | ||
160 | /* We shift by 9, so if we are passed a value of 1 sec, | |
161 | * val will be 1 << 9 = 512, then write that to two | |
162 | * timers => 2 * 512 = 1024 (which is decremented at 1KHz) | |
163 | */ | |
164 | val = time << 9; | |
165 | ||
166 | /* Write timer 1 */ | |
167 | esb_unlock_registers(); | |
168 | writel(val, ESB_TIMER1_REG); | |
169 | ||
170 | /* Write timer 2 */ | |
171 | esb_unlock_registers(); | |
172 | writel(val, ESB_TIMER2_REG); | |
173 | ||
0829291e | 174 | /* Reload */ |
cc90ef0f | 175 | esb_unlock_registers(); |
ce2f50b4 | 176 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); |
cc90ef0f DH |
177 | |
178 | /* FIXME: Do we need to flush everything out? */ | |
179 | ||
180 | /* Done */ | |
181 | heartbeat = time; | |
182 | spin_unlock(&esb_lock); | |
183 | return 0; | |
184 | } | |
185 | ||
0829291e | 186 | static int esb_timer_read(void) |
cc90ef0f | 187 | { |
0829291e | 188 | u32 count; |
cc90ef0f DH |
189 | |
190 | /* This isn't documented, and doesn't take into | |
0829291e AC |
191 | * acount which stage is running, but it looks |
192 | * like a 20 bit count down, so we might as well report it. | |
193 | */ | |
194 | pci_read_config_dword(esb_pci, 0x64, &count); | |
195 | return (int)count; | |
cc90ef0f DH |
196 | } |
197 | ||
198 | /* | |
199 | * /dev/watchdog handling | |
200 | */ | |
201 | ||
0829291e | 202 | static int esb_open(struct inode *inode, struct file *file) |
cc90ef0f | 203 | { |
0829291e AC |
204 | /* /dev/watchdog can only be opened once */ |
205 | if (test_and_set_bit(0, &timer_alive)) | |
206 | return -EBUSY; | |
cc90ef0f | 207 | |
0829291e AC |
208 | /* Reload and activate timer */ |
209 | esb_timer_keepalive(); | |
210 | esb_timer_start(); | |
cc90ef0f DH |
211 | |
212 | return nonseekable_open(inode, file); | |
213 | } | |
214 | ||
0829291e | 215 | static int esb_release(struct inode *inode, struct file *file) |
cc90ef0f | 216 | { |
0829291e AC |
217 | /* Shut off the timer. */ |
218 | if (esb_expect_close == 42) | |
219 | esb_timer_stop(); | |
220 | else { | |
221 | printk(KERN_CRIT PFX | |
222 | "Unexpected close, not stopping watchdog!\n"); | |
223 | esb_timer_keepalive(); | |
224 | } | |
225 | clear_bit(0, &timer_alive); | |
226 | esb_expect_close = 0; | |
227 | return 0; | |
cc90ef0f DH |
228 | } |
229 | ||
0829291e AC |
230 | static ssize_t esb_write(struct file *file, const char __user *data, |
231 | size_t len, loff_t *ppos) | |
cc90ef0f DH |
232 | { |
233 | /* See if we got the magic character 'V' and reload the timer */ | |
0829291e | 234 | if (len) { |
cc90ef0f DH |
235 | if (!nowayout) { |
236 | size_t i; | |
237 | ||
238 | /* note: just in case someone wrote the magic character | |
239 | * five months ago... */ | |
240 | esb_expect_close = 0; | |
241 | ||
242 | /* scan to see whether or not we got the magic character */ | |
243 | for (i = 0; i != len; i++) { | |
244 | char c; | |
0829291e | 245 | if (get_user(c, data+i)) |
cc90ef0f DH |
246 | return -EFAULT; |
247 | if (c == 'V') | |
248 | esb_expect_close = 42; | |
249 | } | |
250 | } | |
251 | ||
252 | /* someone wrote to us, we should reload the timer */ | |
0829291e | 253 | esb_timer_keepalive(); |
cc90ef0f DH |
254 | } |
255 | return len; | |
256 | } | |
257 | ||
0829291e | 258 | static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
cc90ef0f DH |
259 | { |
260 | int new_options, retval = -EINVAL; | |
261 | int new_heartbeat; | |
262 | void __user *argp = (void __user *)arg; | |
263 | int __user *p = argp; | |
264 | static struct watchdog_info ident = { | |
265 | .options = WDIOF_SETTIMEOUT | | |
266 | WDIOF_KEEPALIVEPING | | |
267 | WDIOF_MAGICCLOSE, | |
268 | .firmware_version = 0, | |
269 | .identity = ESB_MODULE_NAME, | |
270 | }; | |
271 | ||
272 | switch (cmd) { | |
0829291e AC |
273 | case WDIOC_GETSUPPORT: |
274 | return copy_to_user(argp, &ident, | |
275 | sizeof(ident)) ? -EFAULT : 0; | |
cc90ef0f | 276 | |
0829291e AC |
277 | case WDIOC_GETSTATUS: |
278 | return put_user(esb_timer_read(), p); | |
cc90ef0f | 279 | |
0829291e AC |
280 | case WDIOC_GETBOOTSTATUS: |
281 | return put_user(triggered, p); | |
cc90ef0f | 282 | |
0829291e AC |
283 | case WDIOC_KEEPALIVE: |
284 | esb_timer_keepalive(); | |
285 | return 0; | |
cc90ef0f | 286 | |
0829291e AC |
287 | case WDIOC_SETOPTIONS: |
288 | { | |
289 | if (get_user(new_options, p)) | |
290 | return -EFAULT; | |
cc90ef0f | 291 | |
0829291e AC |
292 | if (new_options & WDIOS_DISABLECARD) { |
293 | esb_timer_stop(); | |
294 | retval = 0; | |
295 | } | |
cc90ef0f | 296 | |
0829291e AC |
297 | if (new_options & WDIOS_ENABLECARD) { |
298 | esb_timer_keepalive(); | |
299 | esb_timer_start(); | |
300 | retval = 0; | |
301 | } | |
302 | return retval; | |
303 | } | |
304 | case WDIOC_SETTIMEOUT: | |
305 | { | |
306 | if (get_user(new_heartbeat, p)) | |
307 | return -EFAULT; | |
308 | if (esb_timer_set_heartbeat(new_heartbeat)) | |
309 | return -EINVAL; | |
310 | esb_timer_keepalive(); | |
311 | /* Fall */ | |
312 | } | |
313 | case WDIOC_GETTIMEOUT: | |
314 | return put_user(heartbeat, p); | |
315 | default: | |
316 | return -ENOTTY; | |
317 | } | |
cc90ef0f DH |
318 | } |
319 | ||
320 | /* | |
321 | * Notify system | |
322 | */ | |
323 | ||
0829291e AC |
324 | static int esb_notify_sys(struct notifier_block *this, |
325 | unsigned long code, void *unused) | |
cc90ef0f | 326 | { |
0829291e AC |
327 | if (code == SYS_DOWN || code == SYS_HALT) { |
328 | /* Turn the WDT off */ | |
329 | esb_timer_stop(); | |
330 | } | |
331 | return NOTIFY_DONE; | |
cc90ef0f DH |
332 | } |
333 | ||
334 | /* | |
335 | * Kernel Interfaces | |
336 | */ | |
337 | ||
62322d25 | 338 | static const struct file_operations esb_fops = { |
0829291e AC |
339 | .owner = THIS_MODULE, |
340 | .llseek = no_llseek, | |
341 | .write = esb_write, | |
342 | .unlocked_ioctl = esb_ioctl, | |
343 | .open = esb_open, | |
344 | .release = esb_release, | |
cc90ef0f DH |
345 | }; |
346 | ||
347 | static struct miscdevice esb_miscdev = { | |
0829291e AC |
348 | .minor = WATCHDOG_MINOR, |
349 | .name = "watchdog", | |
350 | .fops = &esb_fops, | |
cc90ef0f DH |
351 | }; |
352 | ||
353 | static struct notifier_block esb_notifier = { | |
0829291e | 354 | .notifier_call = esb_notify_sys, |
cc90ef0f DH |
355 | }; |
356 | ||
357 | /* | |
358 | * Data for PCI driver interface | |
359 | * | |
360 | * This data only exists for exporting the supported | |
361 | * PCI ids via MODULE_DEVICE_TABLE. We do not actually | |
362 | * register a pci_driver, because someone else might one day | |
363 | * want to register another driver on the same PCI id. | |
364 | */ | |
365 | static struct pci_device_id esb_pci_tbl[] = { | |
0829291e AC |
366 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), }, |
367 | { 0, }, /* End of list */ | |
cc90ef0f | 368 | }; |
0829291e | 369 | MODULE_DEVICE_TABLE(pci, esb_pci_tbl); |
cc90ef0f DH |
370 | |
371 | /* | |
372 | * Init & exit routines | |
373 | */ | |
374 | ||
0829291e | 375 | static unsigned char __init esb_getdevice(void) |
cc90ef0f DH |
376 | { |
377 | u8 val1; | |
378 | unsigned short val2; | |
0829291e AC |
379 | /* |
380 | * Find the PCI device | |
381 | */ | |
cc90ef0f | 382 | |
0829291e AC |
383 | esb_pci = pci_get_device(PCI_VENDOR_ID_INTEL, |
384 | PCI_DEVICE_ID_INTEL_ESB_9, NULL); | |
cc90ef0f | 385 | |
0829291e AC |
386 | if (esb_pci) { |
387 | if (pci_enable_device(esb_pci)) { | |
388 | printk(KERN_ERR PFX "failed to enable device\n"); | |
811f9991 | 389 | goto err_devput; |
cc90ef0f DH |
390 | } |
391 | ||
392 | if (pci_request_region(esb_pci, 0, ESB_MODULE_NAME)) { | |
0829291e | 393 | printk(KERN_ERR PFX "failed to request region\n"); |
cc90ef0f DH |
394 | goto err_disable; |
395 | } | |
396 | ||
397 | BASEADDR = ioremap(pci_resource_start(esb_pci, 0), | |
398 | pci_resource_len(esb_pci, 0)); | |
399 | if (BASEADDR == NULL) { | |
0829291e AC |
400 | /* Something's wrong here, BASEADDR has to be set */ |
401 | printk(KERN_ERR PFX "failed to get BASEADDR\n"); | |
402 | goto err_release; | |
403 | } | |
cc90ef0f DH |
404 | |
405 | /* | |
406 | * The watchdog has two timers, it can be setup so that the | |
407 | * expiry of timer1 results in an interrupt and the expiry of | |
408 | * timer2 results in a reboot. We set it to not generate | |
409 | * any interrupts as there is not much we can do with it | |
410 | * right now. | |
411 | * | |
412 | * We also enable reboots and set the timer frequency to | |
413 | * the PCI clock divided by 2^15 (approx 1KHz). | |
414 | */ | |
415 | pci_write_config_word(esb_pci, ESB_CONFIG_REG, 0x0003); | |
416 | ||
417 | /* Check that the WDT isn't already locked */ | |
418 | pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val1); | |
419 | if (val1 & ESB_WDT_LOCK) | |
0829291e | 420 | printk(KERN_WARNING PFX "nowayout already set\n"); |
cc90ef0f DH |
421 | |
422 | /* Set the timer to watchdog mode and disable it for now */ | |
423 | pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x00); | |
424 | ||
425 | /* Check if the watchdog was previously triggered */ | |
426 | esb_unlock_registers(); | |
427 | val2 = readw(ESB_RELOAD_REG); | |
428 | triggered = (val2 & (0x01 << 9) >> 9); | |
429 | ||
430 | /* Reset trigger flag and timers */ | |
431 | esb_unlock_registers(); | |
432 | writew((0x11 << 8), ESB_RELOAD_REG); | |
433 | ||
434 | /* Done */ | |
435 | return 1; | |
436 | ||
437 | err_release: | |
438 | pci_release_region(esb_pci, 0); | |
439 | err_disable: | |
440 | pci_disable_device(esb_pci); | |
811f9991 | 441 | err_devput: |
c69af038 | 442 | pci_dev_put(esb_pci); |
cc90ef0f | 443 | } |
cc90ef0f DH |
444 | return 0; |
445 | } | |
446 | ||
0829291e | 447 | static int __init watchdog_init(void) |
cc90ef0f | 448 | { |
0829291e AC |
449 | int ret; |
450 | ||
451 | /* Check whether or not the hardware watchdog is there */ | |
452 | if (!esb_getdevice() || esb_pci == NULL) | |
453 | return -ENODEV; | |
454 | ||
455 | /* Check that the heartbeat value is within it's range; | |
456 | if not reset to the default */ | |
457 | if (esb_timer_set_heartbeat(heartbeat)) { | |
458 | esb_timer_set_heartbeat(WATCHDOG_HEARTBEAT); | |
459 | printk(KERN_INFO PFX | |
460 | "heartbeat value must be 1<heartbeat<2046, using %d\n", | |
461 | heartbeat); | |
462 | } | |
463 | ret = register_reboot_notifier(&esb_notifier); | |
464 | if (ret != 0) { | |
465 | printk(KERN_ERR PFX | |
466 | "cannot register reboot notifier (err=%d)\n", ret); | |
467 | goto err_unmap; | |
468 | } | |
cc90ef0f | 469 | |
0829291e AC |
470 | ret = misc_register(&esb_miscdev); |
471 | if (ret != 0) { | |
472 | printk(KERN_ERR PFX | |
473 | "cannot register miscdev on minor=%d (err=%d)\n", | |
474 | WATCHDOG_MINOR, ret); | |
475 | goto err_notifier; | |
476 | } | |
477 | esb_timer_stop(); | |
478 | printk(KERN_INFO PFX | |
479 | "initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n", | |
480 | BASEADDR, heartbeat, nowayout); | |
481 | return 0; | |
cc90ef0f DH |
482 | |
483 | err_notifier: | |
0829291e | 484 | unregister_reboot_notifier(&esb_notifier); |
cc90ef0f DH |
485 | err_unmap: |
486 | iounmap(BASEADDR); | |
487 | /* err_release: */ | |
488 | pci_release_region(esb_pci, 0); | |
489 | /* err_disable: */ | |
490 | pci_disable_device(esb_pci); | |
811f9991 | 491 | /* err_devput: */ |
c69af038 | 492 | pci_dev_put(esb_pci); |
0829291e | 493 | return ret; |
cc90ef0f DH |
494 | } |
495 | ||
0829291e | 496 | static void __exit watchdog_cleanup(void) |
cc90ef0f DH |
497 | { |
498 | /* Stop the timer before we leave */ | |
499 | if (!nowayout) | |
0829291e | 500 | esb_timer_stop(); |
cc90ef0f DH |
501 | |
502 | /* Deregister */ | |
503 | misc_deregister(&esb_miscdev); | |
0829291e | 504 | unregister_reboot_notifier(&esb_notifier); |
cc90ef0f DH |
505 | iounmap(BASEADDR); |
506 | pci_release_region(esb_pci, 0); | |
507 | pci_disable_device(esb_pci); | |
c69af038 | 508 | pci_dev_put(esb_pci); |
cc90ef0f DH |
509 | } |
510 | ||
511 | module_init(watchdog_init); | |
512 | module_exit(watchdog_cleanup); | |
513 | ||
96de0e25 | 514 | MODULE_AUTHOR("Ross Biro and David Härdeman"); |
cc90ef0f DH |
515 | MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets"); |
516 | MODULE_LICENSE("GPL"); | |
517 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |