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watchdog: sp5100_tco.c: fix potential build failure
[linux-2.6-block.git] / drivers / watchdog / f71808e_wdt.c
CommitLineData
96cb4eb0
GS		 1/***************************************************************************
2 * Copyright (C) 2006 by Hans Edgington <hans@edgington.nl> *
3 * Copyright (C) 2007-2009 Hans de Goede <hdegoede@redhat.com> *
4 * Copyright (C) 2010 Giel van Schijndel <me@mortis.eu> *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
21
27c766aa
JP		 22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
96cb4eb0
GS		 24#include <linux/err.h>
25#include <linux/fs.h>
26#include <linux/init.h>
27#include <linux/io.h>
28#include <linux/ioport.h>
29#include <linux/miscdevice.h>
30#include <linux/module.h>
31#include <linux/mutex.h>
32#include <linux/notifier.h>
33#include <linux/reboot.h>
34#include <linux/uaccess.h>
35#include <linux/watchdog.h>
36
37#define DRVNAME "f71808e_wdt"
38
39#define SIO_F71808FG_LD_WDT 0x07 /* Watchdog timer logical device */
40#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
85c130a8 41#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
96cb4eb0
GS		 42
43#define SIO_REG_LDSEL 0x07 /* Logical device select */
44#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
45#define SIO_REG_DEVREV 0x22 /* Device revision */
46#define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */
7977ff6e 47#define SIO_REG_ROM_ADDR_SEL 0x27 /* ROM address select */
14b24a88 48#define SIO_F81866_REG_PORT_SEL 0x27 /* F81866 Multi-Function Register */
f9a9f096
LB		 49#define SIO_REG_MFUNCT1 0x29 /* Multi function select 1 */
50#define SIO_REG_MFUNCT2 0x2a /* Multi function select 2 */
51#define SIO_REG_MFUNCT3 0x2b /* Multi function select 3 */
14b24a88 52#define SIO_F81866_REG_GPIO1 0x2c /* F81866 GPIO1 Enable Register */
96cb4eb0
GS		 53#define SIO_REG_ENABLE 0x30 /* Logical device enable */
54#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
55
56#define SIO_FINTEK_ID 0x1934 /* Manufacturers ID */
f9a9f096
LB		 57#define SIO_F71808_ID 0x0901 /* Chipset ID */
58#define SIO_F71858_ID 0x0507 /* Chipset ID */
96cb4eb0 59#define SIO_F71862_ID 0x0601 /* Chipset ID */
166fbcf8 60#define SIO_F71868_ID 0x1106 /* Chipset ID */
df278dac 61#define SIO_F71869_ID 0x0814 /* Chipset ID */
3017020d 62#define SIO_F71869A_ID 0x1007 /* Chipset ID */
96cb4eb0
GS		 63#define SIO_F71882_ID 0x0541 /* Chipset ID */
64#define SIO_F71889_ID 0x0723 /* Chipset ID */
ea0c03e8 65#define SIO_F81865_ID 0x0704 /* Chipset ID */
14b24a88 66#define SIO_F81866_ID 0x1010 /* Chipset ID */
96cb4eb0 67
96cb4eb0
GS		 68#define F71808FG_REG_WDO_CONF 0xf0
69#define F71808FG_REG_WDT_CONF 0xf5
70#define F71808FG_REG_WD_TIME 0xf6
71
72#define F71808FG_FLAG_WDOUT_EN 7
73
b97cb21a 74#define F71808FG_FLAG_WDTMOUT_STS 6
96cb4eb0
GS		 75#define F71808FG_FLAG_WD_EN 5
76#define F71808FG_FLAG_WD_PULSE 4
77#define F71808FG_FLAG_WD_UNIT 3
78
ea0c03e8
KP		 79#define F81865_REG_WDO_CONF 0xfa
80#define F81865_FLAG_WDOUT_EN 0
81
96cb4eb0
GS		 82/* Default values */
83#define WATCHDOG_TIMEOUT 60 /* 1 minute default timeout */
84#define WATCHDOG_MAX_TIMEOUT (60 * 255)
85#define WATCHDOG_PULSE_WIDTH 125 /* 125 ms, default pulse width for
86 watchdog signal */
7977ff6e
LB		 87#define WATCHDOG_F71862FG_PIN 63 /* default watchdog reset output
88 pin number 63 */
96cb4eb0
GS		 89
90static unsigned short force_id;
91module_param(force_id, ushort, 0);
92MODULE_PARM_DESC(force_id, "Override the detected device ID");
93
94static const int max_timeout = WATCHDOG_MAX_TIMEOUT;
f9a9f096 95static int timeout = WATCHDOG_TIMEOUT; /* default timeout in seconds */
96cb4eb0
GS		 96module_param(timeout, int, 0);
97MODULE_PARM_DESC(timeout,
98 "Watchdog timeout in seconds. 1<= timeout <="
99 __MODULE_STRING(WATCHDOG_MAX_TIMEOUT) " (default="
100 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
101
102static unsigned int pulse_width = WATCHDOG_PULSE_WIDTH;
103module_param(pulse_width, uint, 0);
104MODULE_PARM_DESC(pulse_width,
166fbcf8 105 "Watchdog signal pulse width. 0(=level), 1, 25, 30, 125, 150, 5000 or 6000 ms"
96cb4eb0
GS		 106 " (default=" __MODULE_STRING(WATCHDOG_PULSE_WIDTH) ")");
107
7977ff6e
LB		 108static unsigned int f71862fg_pin = WATCHDOG_F71862FG_PIN;
109module_param(f71862fg_pin, uint, 0);
110MODULE_PARM_DESC(f71862fg_pin,
111 "Watchdog f71862fg reset output pin configuration. Choose pin 56 or 63"
112 " (default=" __MODULE_STRING(WATCHDOG_F71862FG_PIN)")");
113
90ab5ee9 114static bool nowayout = WATCHDOG_NOWAYOUT;
96cb4eb0
GS		 115module_param(nowayout, bool, 0444);
116MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
117
118static unsigned int start_withtimeout;
119module_param(start_withtimeout, uint, 0);
120MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with"
121 " given initial timeout. Zero (default) disables this feature.");
122
166fbcf8
MS		 123enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg,
124 f81865, f81866};
96cb4eb0
GS		 125
126static const char *f71808e_names[] = {
127 "f71808fg",
128 "f71858fg",
129 "f71862fg",
166fbcf8 130 "f71868",
df278dac 131 "f71869",
96cb4eb0
GS		 132 "f71882fg",
133 "f71889fg",
ea0c03e8 134 "f81865",
14b24a88 135 "f81866",
96cb4eb0
GS		 136};
137
138/* Super-I/O Function prototypes */
139static inline int superio_inb(int base, int reg);
140static inline int superio_inw(int base, int reg);
141static inline void superio_outb(int base, int reg, u8 val);
142static inline void superio_set_bit(int base, int reg, int bit);
143static inline void superio_clear_bit(int base, int reg, int bit);
144static inline int superio_enter(int base);
145static inline void superio_select(int base, int ld);
146static inline void superio_exit(int base);
147
148struct watchdog_data {
149 unsigned short sioaddr;
150 enum chips type;
151 unsigned long opened;
152 struct mutex lock;
153 char expect_close;
154 struct watchdog_info ident;
155
156 unsigned short timeout;
157 u8 timer_val; /* content for the wd_time register */
158 char minutes_mode;
159 u8 pulse_val; /* pulse width flag */
160 char pulse_mode; /* enable pulse output mode? */
161 char caused_reboot; /* last reboot was by the watchdog */
162};
163
164static struct watchdog_data watchdog = {
165 .lock = __MUTEX_INITIALIZER(watchdog.lock),
166};
167
168/* Super I/O functions */
169static inline int superio_inb(int base, int reg)
170{
171 outb(reg, base);
172 return inb(base + 1);
173}
174
175static int superio_inw(int base, int reg)
176{
177 int val;
178 val = superio_inb(base, reg) << 8;
179 val |= superio_inb(base, reg + 1);
180 return val;
181}
182
183static inline void superio_outb(int base, int reg, u8 val)
184{
185 outb(reg, base);
186 outb(val, base + 1);
187}
188
189static inline void superio_set_bit(int base, int reg, int bit)
190{
191 unsigned long val = superio_inb(base, reg);
192 __set_bit(bit, &val);
193 superio_outb(base, reg, val);
194}
195
196static inline void superio_clear_bit(int base, int reg, int bit)
197{
198 unsigned long val = superio_inb(base, reg);
199 __clear_bit(bit, &val);
200 superio_outb(base, reg, val);
201}
202
203static inline int superio_enter(int base)
204{
205 /* Don't step on other drivers' I/O space by accident */
206 if (!request_muxed_region(base, 2, DRVNAME)) {
27c766aa 207 pr_err("I/O address 0x%04x already in use\n", (int)base);
96cb4eb0
GS		 208 return -EBUSY;
209 }
210
3017020d 211 /* according to the datasheet the key must be sent twice! */
96cb4eb0
GS		 212 outb(SIO_UNLOCK_KEY, base);
213 outb(SIO_UNLOCK_KEY, base);
214
215 return 0;
216}
217
218static inline void superio_select(int base, int ld)
219{
220 outb(SIO_REG_LDSEL, base);
221 outb(ld, base + 1);
222}
223
224static inline void superio_exit(int base)
225{
226 outb(SIO_LOCK_KEY, base);
227 release_region(base, 2);
228}
229
230static int watchdog_set_timeout(int timeout)
231{
232 if (timeout <= 0
233 || timeout > max_timeout) {
27c766aa 234 pr_err("watchdog timeout out of range\n");
96cb4eb0
GS		 235 return -EINVAL;
236 }
237
238 mutex_lock(&watchdog.lock);
239
240 watchdog.timeout = timeout;
241 if (timeout > 0xff) {
242 watchdog.timer_val = DIV_ROUND_UP(timeout, 60);
243 watchdog.minutes_mode = true;
244 } else {
245 watchdog.timer_val = timeout;
246 watchdog.minutes_mode = false;
247 }
248
249 mutex_unlock(&watchdog.lock);
250
251 return 0;
252}
253
254static int watchdog_set_pulse_width(unsigned int pw)
255{
256 int err = 0;
166fbcf8
MS		 257 unsigned int t1 = 25, t2 = 125, t3 = 5000;
258
259 if (watchdog.type == f71868) {
260 t1 = 30;
261 t2 = 150;
262 t3 = 6000;
263 }
96cb4eb0
GS		 264
265 mutex_lock(&watchdog.lock);
266
166fbcf8 267 if (pw <= 1) {
96cb4eb0 268 watchdog.pulse_val = 0;
166fbcf8 269 } else if (pw <= t1) {
96cb4eb0 270 watchdog.pulse_val = 1;
166fbcf8 271 } else if (pw <= t2) {
96cb4eb0 272 watchdog.pulse_val = 2;
166fbcf8 273 } else if (pw <= t3) {
96cb4eb0
GS		 274 watchdog.pulse_val = 3;
275 } else {
27c766aa 276 pr_err("pulse width out of range\n");
96cb4eb0
GS		 277 err = -EINVAL;
278 goto exit_unlock;
279 }
280
281 watchdog.pulse_mode = pw;
282
283exit_unlock:
284 mutex_unlock(&watchdog.lock);
285 return err;
286}
287
288static int watchdog_keepalive(void)
289{
290 int err = 0;
291
292 mutex_lock(&watchdog.lock);
293 err = superio_enter(watchdog.sioaddr);
294 if (err)
295 goto exit_unlock;
296 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
297
298 if (watchdog.minutes_mode)
299 /* select minutes for timer units */
300 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
301 F71808FG_FLAG_WD_UNIT);
302 else
303 /* select seconds for timer units */
304 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
305 F71808FG_FLAG_WD_UNIT);
306
307 /* Set timer value */
308 superio_outb(watchdog.sioaddr, F71808FG_REG_WD_TIME,
309 watchdog.timer_val);
310
311 superio_exit(watchdog.sioaddr);
312
313exit_unlock:
314 mutex_unlock(&watchdog.lock);
315 return err;
316}
317
7977ff6e
LB		 318static int f71862fg_pin_configure(unsigned short ioaddr)
319{
320 /* When ioaddr is non-zero the calling function has to take care of
321 mutex handling and superio preparation! */
322
323 if (f71862fg_pin == 63) {
324 if (ioaddr) {
325 /* SPI must be disabled first to use this pin! */
326 superio_clear_bit(ioaddr, SIO_REG_ROM_ADDR_SEL, 6);
327 superio_set_bit(ioaddr, SIO_REG_MFUNCT3, 4);
328 }
329 } else if (f71862fg_pin == 56) {
330 if (ioaddr)
331 superio_set_bit(ioaddr, SIO_REG_MFUNCT1, 1);
332 } else {
27c766aa 333 pr_err("Invalid argument f71862fg_pin=%d\n", f71862fg_pin);
7977ff6e
LB		 334 return -EINVAL;
335 }
336 return 0;
337}
338
96cb4eb0
GS		 339static int watchdog_start(void)
340{
341 /* Make sure we don't die as soon as the watchdog is enabled below */
342 int err = watchdog_keepalive();
343 if (err)
344 return err;
345
346 mutex_lock(&watchdog.lock);
347 err = superio_enter(watchdog.sioaddr);
348 if (err)
349 goto exit_unlock;
350 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
351
352 /* Watchdog pin configuration */
353 switch (watchdog.type) {
354 case f71808fg:
355 /* Set pin 21 to GPIO23/WDTRST#, then to WDTRST# */
f9a9f096
LB		 356 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT2, 3);
357 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 3);
96cb4eb0
GS		 358 break;
359
7977ff6e
LB		 360 case f71862fg:
361 err = f71862fg_pin_configure(watchdog.sioaddr);
362 if (err)
363 goto exit_superio;
364 break;
365
166fbcf8 366 case f71868:
df278dac
MA		 367 case f71869:
368 /* GPIO14 --> WDTRST# */
369 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 4);
370 break;
371
96cb4eb0
GS		 372 case f71882fg:
373 /* Set pin 56 to WDTRST# */
f9a9f096 374 superio_set_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 1);
96cb4eb0
GS		 375 break;
376
dee00abb
GS		 377 case f71889fg:
378 /* set pin 40 to WDTRST# */
f9a9f096
LB		 379 superio_outb(watchdog.sioaddr, SIO_REG_MFUNCT3,
380 superio_inb(watchdog.sioaddr, SIO_REG_MFUNCT3) & 0xcf);
dee00abb
GS		 381 break;
382
ea0c03e8
KP		 383 case f81865:
384 /* Set pin 70 to WDTRST# */
385 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 5);
386 break;
387
14b24a88
JZHPH		 388 case f81866:
389 /* Set pin 70 to WDTRST# */
390 superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL,
391 BIT(3) | BIT(0));
392 superio_set_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL,
393 BIT(2));
394 /*
395 * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
396 * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
397 * BIT5: 0 -> WDTRST#
398 * 1 -> GPIO15
399 */
400 superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1,
401 BIT(5));
402 break;
403
96cb4eb0
GS		 404 default:
405 /*
406 * 'default' label to shut up the compiler and catch
407 * programmer errors
408 */
409 err = -ENODEV;
410 goto exit_superio;
411 }
412
413 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
414 superio_set_bit(watchdog.sioaddr, SIO_REG_ENABLE, 0);
ea0c03e8 415
14b24a88 416 if (watchdog.type == f81865 || watchdog.type == f81866)
ea0c03e8
KP		 417 superio_set_bit(watchdog.sioaddr, F81865_REG_WDO_CONF,
418 F81865_FLAG_WDOUT_EN);
419 else
420 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDO_CONF,
421 F71808FG_FLAG_WDOUT_EN);
96cb4eb0
GS		 422
423 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
424 F71808FG_FLAG_WD_EN);
425
426 if (watchdog.pulse_mode) {
427 /* Select "pulse" output mode with given duration */
428 u8 wdt_conf = superio_inb(watchdog.sioaddr,
429 F71808FG_REG_WDT_CONF);
430
431 /* Set WD_PSWIDTH bits (1:0) */
432 wdt_conf = (wdt_conf & 0xfc) | (watchdog.pulse_val & 0x03);
433 /* Set WD_PULSE to "pulse" mode */
434 wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE);
435
436 superio_outb(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
437 wdt_conf);
438 } else {
439 /* Select "level" output mode */
440 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
441 F71808FG_FLAG_WD_PULSE);
442 }
443
444exit_superio:
445 superio_exit(watchdog.sioaddr);
446exit_unlock:
447 mutex_unlock(&watchdog.lock);
448
449 return err;
450}
451
452static int watchdog_stop(void)
453{
454 int err = 0;
455
456 mutex_lock(&watchdog.lock);
457 err = superio_enter(watchdog.sioaddr);
458 if (err)
459 goto exit_unlock;
460 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
461
462 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
463 F71808FG_FLAG_WD_EN);
464
465 superio_exit(watchdog.sioaddr);
466
467exit_unlock:
468 mutex_unlock(&watchdog.lock);
469
470 return err;
471}
472
473static int watchdog_get_status(void)
474{
475 int status = 0;
476
477 mutex_lock(&watchdog.lock);
478 status = (watchdog.caused_reboot) ? WDIOF_CARDRESET : 0;
479 mutex_unlock(&watchdog.lock);
480
481 return status;
482}
483
484static bool watchdog_is_running(void)
485{
486 /*
487 * if we fail to determine the watchdog's status assume it to be
488 * running to be on the safe side
489 */
490 bool is_running = true;
491
492 mutex_lock(&watchdog.lock);
493 if (superio_enter(watchdog.sioaddr))
494 goto exit_unlock;
495 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
496
497 is_running = (superio_inb(watchdog.sioaddr, SIO_REG_ENABLE) & BIT(0))
498 && (superio_inb(watchdog.sioaddr, F71808FG_REG_WDT_CONF)
499 & F71808FG_FLAG_WD_EN);
500
501 superio_exit(watchdog.sioaddr);
502
503exit_unlock:
504 mutex_unlock(&watchdog.lock);
505 return is_running;
506}
507
508/* /dev/watchdog api */
509
510static int watchdog_open(struct inode *inode, struct file *file)
511{
512 int err;
513
514 /* If the watchdog is alive we don't need to start it again */
515 if (test_and_set_bit(0, &watchdog.opened))
516 return -EBUSY;
517
518 err = watchdog_start();
519 if (err) {
520 clear_bit(0, &watchdog.opened);
521 return err;
522 }
523
524 if (nowayout)
525 __module_get(THIS_MODULE);
526
527 watchdog.expect_close = 0;
528 return nonseekable_open(inode, file);
529}
530
531static int watchdog_release(struct inode *inode, struct file *file)
532{
533 clear_bit(0, &watchdog.opened);
534
535 if (!watchdog.expect_close) {
536 watchdog_keepalive();
27c766aa 537 pr_crit("Unexpected close, not stopping watchdog!\n");
96cb4eb0
GS		 538 } else if (!nowayout) {
539 watchdog_stop();
540 }
541 return 0;
542}
543
544/*
545 * watchdog_write:
546 * @file: file handle to the watchdog
547 * @buf: buffer to write
548 * @count: count of bytes
549 * @ppos: pointer to the position to write. No seeks allowed
550 *
551 * A write to a watchdog device is defined as a keepalive signal. Any
552 * write of data will do, as we we don't define content meaning.
553 */
554
555static ssize_t watchdog_write(struct file *file, const char __user *buf,
556 size_t count, loff_t *ppos)
557{
558 if (count) {
559 if (!nowayout) {
560 size_t i;
561
562 /* In case it was set long ago */
563 bool expect_close = false;
564
565 for (i = 0; i != count; i++) {
566 char c;
567 if (get_user(c, buf + i))
568 return -EFAULT;
569 expect_close = (c == 'V');
570 }
571
572 /* Properly order writes across fork()ed processes */
573 mutex_lock(&watchdog.lock);
574 watchdog.expect_close = expect_close;
575 mutex_unlock(&watchdog.lock);
576 }
577
578 /* someone wrote to us, we should restart timer */
579 watchdog_keepalive();
580 }
581 return count;
582}
583
584/*
585 * watchdog_ioctl:
586 * @inode: inode of the device
587 * @file: file handle to the device
588 * @cmd: watchdog command
589 * @arg: argument pointer
590 *
591 * The watchdog API defines a common set of functions for all watchdogs
592 * according to their available features.
593 */
594static long watchdog_ioctl(struct file *file, unsigned int cmd,
595 unsigned long arg)
596{
597 int status;
598 int new_options;
599 int new_timeout;
600 union {
601 struct watchdog_info __user *ident;
602 int __user *i;
603 } uarg;
604
605 uarg.i = (int __user *)arg;
606
607 switch (cmd) {
608 case WDIOC_GETSUPPORT:
609 return copy_to_user(uarg.ident, &watchdog.ident,
610 sizeof(watchdog.ident)) ? -EFAULT : 0;
611
612 case WDIOC_GETSTATUS:
613 status = watchdog_get_status();
614 if (status < 0)
615 return status;
616 return put_user(status, uarg.i);
617
618 case WDIOC_GETBOOTSTATUS:
619 return put_user(0, uarg.i);
620
621 case WDIOC_SETOPTIONS:
622 if (get_user(new_options, uarg.i))
623 return -EFAULT;
624
625 if (new_options & WDIOS_DISABLECARD)
626 watchdog_stop();
627
628 if (new_options & WDIOS_ENABLECARD)
629 return watchdog_start();
fd846b57 630 /* fall through */
96cb4eb0
GS		 631
632 case WDIOC_KEEPALIVE:
633 watchdog_keepalive();
634 return 0;
635
636 case WDIOC_SETTIMEOUT:
637 if (get_user(new_timeout, uarg.i))
638 return -EFAULT;
639
640 if (watchdog_set_timeout(new_timeout))
641 return -EINVAL;
642
643 watchdog_keepalive();
fd846b57 644 /* fall through */
96cb4eb0
GS		 645
646 case WDIOC_GETTIMEOUT:
647 return put_user(watchdog.timeout, uarg.i);
648
649 default:
650 return -ENOTTY;
651
652 }
653}
654
655static int watchdog_notify_sys(struct notifier_block *this, unsigned long code,
656 void *unused)
657{
658 if (code == SYS_DOWN || code == SYS_HALT)
659 watchdog_stop();
660 return NOTIFY_DONE;
661}
662
663static const struct file_operations watchdog_fops = {
664 .owner = THIS_MODULE,
665 .llseek = no_llseek,
666 .open = watchdog_open,
667 .release = watchdog_release,
668 .write = watchdog_write,
669 .unlocked_ioctl = watchdog_ioctl,
670};
671
672static struct miscdevice watchdog_miscdev = {
673 .minor = WATCHDOG_MINOR,
674 .name = "watchdog",
675 .fops = &watchdog_fops,
676};
677
678static struct notifier_block watchdog_notifier = {
679 .notifier_call = watchdog_notify_sys,
680};
681
682static int __init watchdog_init(int sioaddr)
683{
684 int wdt_conf, err = 0;
685
686 /* No need to lock watchdog.lock here because no entry points
687 * into the module have been registered yet.
688 */
689 watchdog.sioaddr = sioaddr;
690 watchdog.ident.options = WDIOC_SETTIMEOUT
691 | WDIOF_MAGICCLOSE
692 | WDIOF_KEEPALIVEPING;
693
694 snprintf(watchdog.ident.identity,
695 sizeof(watchdog.ident.identity), "%s watchdog",
696 f71808e_names[watchdog.type]);
697
698 err = superio_enter(sioaddr);
699 if (err)
700 return err;
701 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
702
703 wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
b97cb21a 704 watchdog.caused_reboot = wdt_conf & BIT(F71808FG_FLAG_WDTMOUT_STS);
96cb4eb0
GS		 705
706 superio_exit(sioaddr);
707
708 err = watchdog_set_timeout(timeout);
709 if (err)
710 return err;
711 err = watchdog_set_pulse_width(pulse_width);
712 if (err)
713 return err;
714
715 err = register_reboot_notifier(&watchdog_notifier);
716 if (err)
717 return err;
718
719 err = misc_register(&watchdog_miscdev);
720 if (err) {
27c766aa
JP		 721 pr_err("cannot register miscdev on minor=%d\n",
722 watchdog_miscdev.minor);
96cb4eb0
GS		 723 goto exit_reboot;
724 }
725
726 if (start_withtimeout) {
727 if (start_withtimeout <= 0
728 || start_withtimeout > max_timeout) {
27c766aa 729 pr_err("starting timeout out of range\n");
96cb4eb0
GS		 730 err = -EINVAL;
731 goto exit_miscdev;
732 }
733
734 err = watchdog_start();
735 if (err) {
27c766aa 736 pr_err("cannot start watchdog timer\n");
96cb4eb0
GS		 737 goto exit_miscdev;
738 }
739
740 mutex_lock(&watchdog.lock);
741 err = superio_enter(sioaddr);
742 if (err)
743 goto exit_unlock;
744 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
745
746 if (start_withtimeout > 0xff) {
747 /* select minutes for timer units */
748 superio_set_bit(sioaddr, F71808FG_REG_WDT_CONF,
749 F71808FG_FLAG_WD_UNIT);
750 superio_outb(sioaddr, F71808FG_REG_WD_TIME,
751 DIV_ROUND_UP(start_withtimeout, 60));
752 } else {
753 /* select seconds for timer units */
754 superio_clear_bit(sioaddr, F71808FG_REG_WDT_CONF,
755 F71808FG_FLAG_WD_UNIT);
756 superio_outb(sioaddr, F71808FG_REG_WD_TIME,
757 start_withtimeout);
758 }
759
760 superio_exit(sioaddr);
761 mutex_unlock(&watchdog.lock);
762
763 if (nowayout)
764 __module_get(THIS_MODULE);
765
27c766aa 766 pr_info("watchdog started with initial timeout of %u sec\n",
96cb4eb0
GS		 767 start_withtimeout);
768 }
769
770 return 0;
771
772exit_unlock:
773 mutex_unlock(&watchdog.lock);
774exit_miscdev:
775 misc_deregister(&watchdog_miscdev);
776exit_reboot:
777 unregister_reboot_notifier(&watchdog_notifier);
778
779 return err;
780}
781
782static int __init f71808e_find(int sioaddr)
783{
784 u16 devid;
785 int err = superio_enter(sioaddr);
786 if (err)
787 return err;
788
789 devid = superio_inw(sioaddr, SIO_REG_MANID);
790 if (devid != SIO_FINTEK_ID) {
27c766aa 791 pr_debug("Not a Fintek device\n");
96cb4eb0
GS		 792 err = -ENODEV;
793 goto exit;
794 }
795
796 devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID);
797 switch (devid) {
798 case SIO_F71808_ID:
799 watchdog.type = f71808fg;
800 break;
7977ff6e
LB		 801 case SIO_F71862_ID:
802 watchdog.type = f71862fg;
803 err = f71862fg_pin_configure(0); /* validate module parameter */
804 break;
166fbcf8
MS		 805 case SIO_F71868_ID:
806 watchdog.type = f71868;
807 break;
df278dac 808 case SIO_F71869_ID:
3017020d 809 case SIO_F71869A_ID:
df278dac
MA		 810 watchdog.type = f71869;
811 break;
96cb4eb0
GS		 812 case SIO_F71882_ID:
813 watchdog.type = f71882fg;
814 break;
96cb4eb0 815 case SIO_F71889_ID:
dee00abb
GS		 816 watchdog.type = f71889fg;
817 break;
96cb4eb0
GS		 818 case SIO_F71858_ID:
819 /* Confirmed (by datasheet) not to have a watchdog. */
820 err = -ENODEV;
821 goto exit;
ea0c03e8
KP		 822 case SIO_F81865_ID:
823 watchdog.type = f81865;
14b24a88
JZHPH		 824 break;
825 case SIO_F81866_ID:
826 watchdog.type = f81866;
ea0c03e8 827 break;
96cb4eb0 828 default:
27c766aa
JP		 829 pr_info("Unrecognized Fintek device: %04x\n",
830 (unsigned int)devid);
96cb4eb0
GS		 831 err = -ENODEV;
832 goto exit;
833 }
834
27c766aa 835 pr_info("Found %s watchdog chip, revision %d\n",
96cb4eb0
GS		 836 f71808e_names[watchdog.type],
837 (int)superio_inb(sioaddr, SIO_REG_DEVREV));
838exit:
839 superio_exit(sioaddr);
840 return err;
841}
842
843static int __init f71808e_init(void)
844{
845 static const unsigned short addrs[] = { 0x2e, 0x4e };
846 int err = -ENODEV;
847 int i;
848
849 for (i = 0; i < ARRAY_SIZE(addrs); i++) {
850 err = f71808e_find(addrs[i]);
851 if (err == 0)
852 break;
853 }
854 if (i == ARRAY_SIZE(addrs))
855 return err;
856
857 return watchdog_init(addrs[i]);
858}
859
860static void __exit f71808e_exit(void)
861{
862 if (watchdog_is_running()) {
27c766aa 863 pr_warn("Watchdog timer still running, stopping it\n");
96cb4eb0
GS		 864 watchdog_stop();
865 }
866 misc_deregister(&watchdog_miscdev);
867 unregister_reboot_notifier(&watchdog_notifier);
868}
869
870MODULE_DESCRIPTION("F71808E Watchdog Driver");
871MODULE_AUTHOR("Giel van Schijndel <me@mortis.eu>");
872MODULE_LICENSE("GPL");
873
874module_init(f71808e_init);
875module_exit(f71808e_exit);
Linux 6.x block layer and io_uring tree(s)