Commit | Line | Data |
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c9353ae1 JI |
1 | /* |
2 | * Copyright 2010-2011 Picochip Ltd., Jamie Iles | |
3 | * http://www.picochip.com | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * This file implements a driver for the Synopsys DesignWare watchdog device | |
58a251f2 | 11 | * in the many subsystems. The watchdog has 16 different timeout periods |
c9353ae1 JI |
12 | * and these are a function of the input clock frequency. |
13 | * | |
14 | * The DesignWare watchdog cannot be stopped once it has been started so we | |
f29a72c2 GR |
15 | * do not implement a stop function. The watchdog core will continue to send |
16 | * heartbeat requests after the watchdog device has been closed. | |
c9353ae1 | 17 | */ |
27c766aa JP |
18 | |
19 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
c9353ae1 JI |
20 | |
21 | #include <linux/bitops.h> | |
22 | #include <linux/clk.h> | |
31228f43 | 23 | #include <linux/delay.h> |
c9353ae1 | 24 | #include <linux/err.h> |
c9353ae1 JI |
25 | #include <linux/io.h> |
26 | #include <linux/kernel.h> | |
c9353ae1 JI |
27 | #include <linux/module.h> |
28 | #include <linux/moduleparam.h> | |
58e56373 | 29 | #include <linux/of.h> |
c9353ae1 JI |
30 | #include <linux/pm.h> |
31 | #include <linux/platform_device.h> | |
65a3b693 | 32 | #include <linux/reset.h> |
c9353ae1 JI |
33 | #include <linux/watchdog.h> |
34 | ||
35 | #define WDOG_CONTROL_REG_OFFSET 0x00 | |
36 | #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01 | |
a81abbb4 | 37 | #define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02 |
c9353ae1 | 38 | #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04 |
dfa07141 | 39 | #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4 |
c9353ae1 JI |
40 | #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08 |
41 | #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c | |
42 | #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76 | |
43 | ||
44 | /* The maximum TOP (timeout period) value that can be set in the watchdog. */ | |
45 | #define DW_WDT_MAX_TOP 15 | |
46 | ||
b5ade9bc DA |
47 | #define DW_WDT_DEFAULT_SECONDS 30 |
48 | ||
86a1e189 WVS |
49 | static bool nowayout = WATCHDOG_NOWAYOUT; |
50 | module_param(nowayout, bool, 0); | |
c9353ae1 JI |
51 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " |
52 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
53 | ||
f29a72c2 | 54 | struct dw_wdt { |
c9353ae1 JI |
55 | void __iomem *regs; |
56 | struct clk *clk; | |
c97344f7 | 57 | unsigned long rate; |
f29a72c2 | 58 | struct watchdog_device wdd; |
65a3b693 | 59 | struct reset_control *rst; |
8c088370 BN |
60 | /* Save/restore */ |
61 | u32 control; | |
62 | u32 timeout; | |
f29a72c2 GR |
63 | }; |
64 | ||
65 | #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) | |
c9353ae1 | 66 | |
f29a72c2 | 67 | static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt) |
c9353ae1 | 68 | { |
f29a72c2 | 69 | return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) & |
c9353ae1 JI |
70 | WDOG_CONTROL_REG_WDT_EN_MASK; |
71 | } | |
72 | ||
f29a72c2 | 73 | static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top) |
c9353ae1 JI |
74 | { |
75 | /* | |
76 | * There are 16 possible timeout values in 0..15 where the number of | |
77 | * cycles is 2 ^ (16 + i) and the watchdog counts down. | |
78 | */ | |
c97344f7 | 79 | return (1U << (16 + top)) / dw_wdt->rate; |
c9353ae1 JI |
80 | } |
81 | ||
f29a72c2 | 82 | static int dw_wdt_get_top(struct dw_wdt *dw_wdt) |
c9353ae1 | 83 | { |
f29a72c2 | 84 | int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF; |
c9353ae1 | 85 | |
f29a72c2 | 86 | return dw_wdt_top_in_seconds(dw_wdt, top); |
c9353ae1 JI |
87 | } |
88 | ||
f29a72c2 | 89 | static int dw_wdt_ping(struct watchdog_device *wdd) |
c9353ae1 | 90 | { |
f29a72c2 | 91 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 | 92 | |
f29a72c2 | 93 | writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs + |
a0085010 | 94 | WDOG_COUNTER_RESTART_REG_OFFSET); |
f29a72c2 GR |
95 | |
96 | return 0; | |
a0085010 DA |
97 | } |
98 | ||
f29a72c2 | 99 | static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s) |
c9353ae1 | 100 | { |
f29a72c2 | 101 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 JI |
102 | int i, top_val = DW_WDT_MAX_TOP; |
103 | ||
104 | /* | |
105 | * Iterate over the timeout values until we find the closest match. We | |
106 | * always look for >=. | |
107 | */ | |
108 | for (i = 0; i <= DW_WDT_MAX_TOP; ++i) | |
f29a72c2 | 109 | if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) { |
c9353ae1 JI |
110 | top_val = i; |
111 | break; | |
112 | } | |
113 | ||
a0085010 DA |
114 | /* |
115 | * Set the new value in the watchdog. Some versions of dw_wdt | |
116 | * have have TOPINIT in the TIMEOUT_RANGE register (as per | |
117 | * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we | |
118 | * effectively get a pat of the watchdog right here. | |
119 | */ | |
dfa07141 | 120 | writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT, |
f29a72c2 | 121 | dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
c9353ae1 | 122 | |
f29a72c2 | 123 | wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val); |
a0085010 | 124 | |
f29a72c2 GR |
125 | return 0; |
126 | } | |
127 | ||
a81abbb4 BN |
128 | static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt) |
129 | { | |
130 | u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); | |
131 | ||
132 | /* Disable interrupt mode; always perform system reset. */ | |
133 | val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK; | |
134 | /* Enable watchdog. */ | |
135 | val |= WDOG_CONTROL_REG_WDT_EN_MASK; | |
136 | writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); | |
137 | } | |
138 | ||
f29a72c2 GR |
139 | static int dw_wdt_start(struct watchdog_device *wdd) |
140 | { | |
141 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); | |
142 | ||
143 | dw_wdt_set_timeout(wdd, wdd->timeout); | |
a81abbb4 | 144 | dw_wdt_arm_system_reset(dw_wdt); |
f29a72c2 GR |
145 | |
146 | return 0; | |
c9353ae1 JI |
147 | } |
148 | ||
1bfe8889 OR |
149 | static int dw_wdt_stop(struct watchdog_device *wdd) |
150 | { | |
151 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); | |
152 | ||
153 | if (!dw_wdt->rst) { | |
154 | set_bit(WDOG_HW_RUNNING, &wdd->status); | |
155 | return 0; | |
156 | } | |
157 | ||
158 | reset_control_assert(dw_wdt->rst); | |
159 | reset_control_deassert(dw_wdt->rst); | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
a70dcc01 GR |
164 | static int dw_wdt_restart(struct watchdog_device *wdd, |
165 | unsigned long action, void *data) | |
31228f43 | 166 | { |
a70dcc01 | 167 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
31228f43 | 168 | |
f29a72c2 | 169 | writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
a81abbb4 | 170 | if (dw_wdt_is_enabled(dw_wdt)) |
f29a72c2 GR |
171 | writel(WDOG_COUNTER_RESTART_KICK_VALUE, |
172 | dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET); | |
31228f43 | 173 | else |
a81abbb4 | 174 | dw_wdt_arm_system_reset(dw_wdt); |
31228f43 JZ |
175 | |
176 | /* wait for reset to assert... */ | |
177 | mdelay(500); | |
178 | ||
a70dcc01 | 179 | return 0; |
31228f43 JZ |
180 | } |
181 | ||
f29a72c2 | 182 | static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd) |
c9353ae1 | 183 | { |
f29a72c2 | 184 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 | 185 | |
f29a72c2 | 186 | return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) / |
c97344f7 | 187 | dw_wdt->rate; |
c9353ae1 JI |
188 | } |
189 | ||
190 | static const struct watchdog_info dw_wdt_ident = { | |
191 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | | |
192 | WDIOF_MAGICCLOSE, | |
193 | .identity = "Synopsys DesignWare Watchdog", | |
194 | }; | |
195 | ||
f29a72c2 GR |
196 | static const struct watchdog_ops dw_wdt_ops = { |
197 | .owner = THIS_MODULE, | |
198 | .start = dw_wdt_start, | |
1bfe8889 | 199 | .stop = dw_wdt_stop, |
f29a72c2 GR |
200 | .ping = dw_wdt_ping, |
201 | .set_timeout = dw_wdt_set_timeout, | |
202 | .get_timeleft = dw_wdt_get_timeleft, | |
a70dcc01 | 203 | .restart = dw_wdt_restart, |
f29a72c2 | 204 | }; |
c9353ae1 | 205 | |
ad83c6cb | 206 | #ifdef CONFIG_PM_SLEEP |
c9353ae1 JI |
207 | static int dw_wdt_suspend(struct device *dev) |
208 | { | |
f29a72c2 GR |
209 | struct dw_wdt *dw_wdt = dev_get_drvdata(dev); |
210 | ||
8c088370 BN |
211 | dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); |
212 | dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); | |
213 | ||
f29a72c2 | 214 | clk_disable_unprepare(dw_wdt->clk); |
c9353ae1 JI |
215 | |
216 | return 0; | |
217 | } | |
218 | ||
219 | static int dw_wdt_resume(struct device *dev) | |
220 | { | |
f29a72c2 GR |
221 | struct dw_wdt *dw_wdt = dev_get_drvdata(dev); |
222 | int err = clk_prepare_enable(dw_wdt->clk); | |
c9353ae1 JI |
223 | |
224 | if (err) | |
225 | return err; | |
226 | ||
8c088370 BN |
227 | writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
228 | writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); | |
229 | ||
f29a72c2 | 230 | dw_wdt_ping(&dw_wdt->wdd); |
c9353ae1 JI |
231 | |
232 | return 0; | |
233 | } | |
ad83c6cb | 234 | #endif /* CONFIG_PM_SLEEP */ |
c9353ae1 | 235 | |
ad83c6cb | 236 | static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume); |
c9353ae1 | 237 | |
2d991a16 | 238 | static int dw_wdt_drv_probe(struct platform_device *pdev) |
c9353ae1 | 239 | { |
f29a72c2 GR |
240 | struct device *dev = &pdev->dev; |
241 | struct watchdog_device *wdd; | |
242 | struct dw_wdt *dw_wdt; | |
243 | struct resource *mem; | |
c9353ae1 | 244 | int ret; |
c9353ae1 | 245 | |
f29a72c2 GR |
246 | dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL); |
247 | if (!dw_wdt) | |
248 | return -ENOMEM; | |
249 | ||
250 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
251 | dw_wdt->regs = devm_ioremap_resource(dev, mem); | |
252 | if (IS_ERR(dw_wdt->regs)) | |
253 | return PTR_ERR(dw_wdt->regs); | |
c9353ae1 | 254 | |
f29a72c2 GR |
255 | dw_wdt->clk = devm_clk_get(dev, NULL); |
256 | if (IS_ERR(dw_wdt->clk)) | |
257 | return PTR_ERR(dw_wdt->clk); | |
c9353ae1 | 258 | |
f29a72c2 | 259 | ret = clk_prepare_enable(dw_wdt->clk); |
c9353ae1 | 260 | if (ret) |
cf3cc8c2 | 261 | return ret; |
c9353ae1 | 262 | |
c97344f7 GR |
263 | dw_wdt->rate = clk_get_rate(dw_wdt->clk); |
264 | if (dw_wdt->rate == 0) { | |
265 | ret = -EINVAL; | |
266 | goto out_disable_clk; | |
267 | } | |
268 | ||
65a3b693 ST |
269 | dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); |
270 | if (IS_ERR(dw_wdt->rst)) { | |
271 | ret = PTR_ERR(dw_wdt->rst); | |
272 | goto out_disable_clk; | |
273 | } | |
274 | ||
275 | reset_control_deassert(dw_wdt->rst); | |
276 | ||
f29a72c2 GR |
277 | wdd = &dw_wdt->wdd; |
278 | wdd->info = &dw_wdt_ident; | |
279 | wdd->ops = &dw_wdt_ops; | |
280 | wdd->min_timeout = 1; | |
281 | wdd->max_hw_heartbeat_ms = | |
282 | dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000; | |
283 | wdd->parent = dev; | |
284 | ||
285 | watchdog_set_drvdata(wdd, dw_wdt); | |
286 | watchdog_set_nowayout(wdd, nowayout); | |
287 | watchdog_init_timeout(wdd, 0, dev); | |
288 | ||
289 | /* | |
290 | * If the watchdog is already running, use its already configured | |
291 | * timeout. Otherwise use the default or the value provided through | |
292 | * devicetree. | |
293 | */ | |
294 | if (dw_wdt_is_enabled(dw_wdt)) { | |
295 | wdd->timeout = dw_wdt_get_top(dw_wdt); | |
296 | set_bit(WDOG_HW_RUNNING, &wdd->status); | |
297 | } else { | |
298 | wdd->timeout = DW_WDT_DEFAULT_SECONDS; | |
299 | watchdog_init_timeout(wdd, 0, dev); | |
300 | } | |
301 | ||
302 | platform_set_drvdata(pdev, dw_wdt); | |
303 | ||
a70dcc01 GR |
304 | watchdog_set_restart_priority(wdd, 128); |
305 | ||
f29a72c2 | 306 | ret = watchdog_register_device(wdd); |
c9353ae1 JI |
307 | if (ret) |
308 | goto out_disable_clk; | |
309 | ||
c9353ae1 JI |
310 | return 0; |
311 | ||
312 | out_disable_clk: | |
f29a72c2 | 313 | clk_disable_unprepare(dw_wdt->clk); |
c9353ae1 JI |
314 | return ret; |
315 | } | |
316 | ||
4b12b896 | 317 | static int dw_wdt_drv_remove(struct platform_device *pdev) |
c9353ae1 | 318 | { |
f29a72c2 | 319 | struct dw_wdt *dw_wdt = platform_get_drvdata(pdev); |
c9353ae1 | 320 | |
f29a72c2 | 321 | watchdog_unregister_device(&dw_wdt->wdd); |
65a3b693 | 322 | reset_control_assert(dw_wdt->rst); |
f29a72c2 | 323 | clk_disable_unprepare(dw_wdt->clk); |
c9353ae1 JI |
324 | |
325 | return 0; | |
326 | } | |
327 | ||
58e56373 DN |
328 | #ifdef CONFIG_OF |
329 | static const struct of_device_id dw_wdt_of_match[] = { | |
330 | { .compatible = "snps,dw-wdt", }, | |
331 | { /* sentinel */ } | |
332 | }; | |
333 | MODULE_DEVICE_TABLE(of, dw_wdt_of_match); | |
334 | #endif | |
335 | ||
c9353ae1 JI |
336 | static struct platform_driver dw_wdt_driver = { |
337 | .probe = dw_wdt_drv_probe, | |
82268714 | 338 | .remove = dw_wdt_drv_remove, |
c9353ae1 JI |
339 | .driver = { |
340 | .name = "dw_wdt", | |
58e56373 | 341 | .of_match_table = of_match_ptr(dw_wdt_of_match), |
c9353ae1 | 342 | .pm = &dw_wdt_pm_ops, |
c9353ae1 JI |
343 | }, |
344 | }; | |
345 | ||
b8ec6118 | 346 | module_platform_driver(dw_wdt_driver); |
c9353ae1 JI |
347 | |
348 | MODULE_AUTHOR("Jamie Iles"); | |
349 | MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver"); | |
350 | MODULE_LICENSE("GPL"); |