[linux-block.git] / drivers / watchdog / davinci_wdt.c

/*
 * drivers/char/watchdog/davinci_wdt.c
 *
 * Watchdog driver for DaVinci DM644x/DM646x processors
 *
 * Copyright (C) 2006-2013 Texas Instruments.
 *
 * 2007 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mod_devicetable.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/err.h>

#define MODULE_NAME "DAVINCI-WDT: "

#define DEFAULT_HEARTBEAT 60
#define MAX_HEARTBEAT     600	/* really the max margin is 264/27MHz*/

/* Timer register set definition */
#define PID12	(0x0)
#define EMUMGT	(0x4)
#define TIM12	(0x10)
#define TIM34	(0x14)
#define PRD12	(0x18)
#define PRD34	(0x1C)
#define TCR	(0x20)
#define TGCR	(0x24)
#define WDTCR	(0x28)

/* TCR bit definitions */
#define ENAMODE12_DISABLED	(0 << 6)
#define ENAMODE12_ONESHOT	(1 << 6)
#define ENAMODE12_PERIODIC	(2 << 6)

/* TGCR bit definitions */
#define TIM12RS_UNRESET		(1 << 0)
#define TIM34RS_UNRESET		(1 << 1)
#define TIMMODE_64BIT_WDOG      (2 << 2)

/* WDTCR bit definitions */
#define WDEN			(1 << 14)
#define WDFLAG			(1 << 15)
#define WDKEY_SEQ0		(0xa5c6 << 16)
#define WDKEY_SEQ1		(0xda7e << 16)

static int heartbeat;

/*
 * struct to hold data for each WDT device
 * @base - base io address of WD device
 * @clk - source clock of WDT
 * @wdd - hold watchdog device as is in WDT core
 */
struct davinci_wdt_device {
	void __iomem		*base;
	struct clk		*clk;
	struct watchdog_device	wdd;
};

static int davinci_wdt_start(struct watchdog_device *wdd)
{
	u32 tgcr;
	u32 timer_margin;
	unsigned long wdt_freq;
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);

	wdt_freq = clk_get_rate(davinci_wdt->clk);

	/* disable, internal clock source */
	iowrite32(0, davinci_wdt->base + TCR);
	/* reset timer, set mode to 64-bit watchdog, and unreset */
	iowrite32(0, davinci_wdt->base + TGCR);
	tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
	iowrite32(tgcr, davinci_wdt->base + TGCR);
	/* clear counter regs */
	iowrite32(0, davinci_wdt->base + TIM12);
	iowrite32(0, davinci_wdt->base + TIM34);
	/* set timeout period */
	timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
	iowrite32(timer_margin, davinci_wdt->base + PRD12);
	timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
	iowrite32(timer_margin, davinci_wdt->base + PRD34);
	/* enable run continuously */
	iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
	/* Once the WDT is in pre-active state write to
	 * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
	 * write protected (except for the WDKEY field)
	 */
	/* put watchdog in pre-active state */
	iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR);
	/* put watchdog in active state */
	iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR);
	return 0;
}

static int davinci_wdt_ping(struct watchdog_device *wdd)
{
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);

	/* put watchdog in service state */
	iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
	/* put watchdog in active state */
	iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
	return 0;
}

static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
{
	u64 timer_counter;
	unsigned long freq;
	u32 val;
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);

	/* if timeout has occured then return 0 */
	val = ioread32(davinci_wdt->base + WDTCR);
	if (val & WDFLAG)
		return 0;

	freq = clk_get_rate(davinci_wdt->clk);

	if (!freq)
		return 0;

	timer_counter = ioread32(davinci_wdt->base + TIM12);
	timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);

	do_div(timer_counter, freq);

	return wdd->timeout - timer_counter;
}

static int davinci_wdt_restart(struct watchdog_device *wdd,
			       unsigned long action, void *data)
{
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
	u32 tgcr, wdtcr;

	/* disable, internal clock source */
	iowrite32(0, davinci_wdt->base + TCR);

	/* reset timer, set mode to 64-bit watchdog, and unreset */
	tgcr = 0;
	iowrite32(tgcr, davinci_wdt->base + TGCR);
	tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
	iowrite32(tgcr, davinci_wdt->base + TGCR);

	/* clear counter and period regs */
	iowrite32(0, davinci_wdt->base + TIM12);
	iowrite32(0, davinci_wdt->base + TIM34);
	iowrite32(0, davinci_wdt->base + PRD12);
	iowrite32(0, davinci_wdt->base + PRD34);

	/* put watchdog in pre-active state */
	wdtcr = WDKEY_SEQ0 | WDEN;
	iowrite32(wdtcr, davinci_wdt->base + WDTCR);

	/* put watchdog in active state */
	wdtcr = WDKEY_SEQ1 | WDEN;
	iowrite32(wdtcr, davinci_wdt->base + WDTCR);

	/* write an invalid value to the WDKEY field to trigger a restart */
	wdtcr = 0x00004000;
	iowrite32(wdtcr, davinci_wdt->base + WDTCR);

	return 0;
}

static const struct watchdog_info davinci_wdt_info = {
	.options = WDIOF_KEEPALIVEPING,
	.identity = "DaVinci/Keystone Watchdog",
};

static const struct watchdog_ops davinci_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= davinci_wdt_start,
	.stop		= davinci_wdt_ping,
	.ping		= davinci_wdt_ping,
	.get_timeleft	= davinci_wdt_get_timeleft,
	.restart	= davinci_wdt_restart,
};

static int davinci_wdt_probe(struct platform_device *pdev)
{
	int ret = 0;
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdd;
	struct davinci_wdt_device *davinci_wdt;

	davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
	if (!davinci_wdt)
		return -ENOMEM;

	davinci_wdt->clk = devm_clk_get(dev, NULL);

	if (IS_ERR(davinci_wdt->clk)) {
		if (PTR_ERR(davinci_wdt->clk) != -EPROBE_DEFER)
			dev_err(&pdev->dev, "failed to get clock node\n");
		return PTR_ERR(davinci_wdt->clk);
	}

	ret = clk_prepare_enable(davinci_wdt->clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to prepare clock\n");
		return ret;
	}

	platform_set_drvdata(pdev, davinci_wdt);

	wdd			= &davinci_wdt->wdd;
	wdd->info		= &davinci_wdt_info;
	wdd->ops		= &davinci_wdt_ops;
	wdd->min_timeout	= 1;
	wdd->max_timeout	= MAX_HEARTBEAT;
	wdd->timeout		= DEFAULT_HEARTBEAT;
	wdd->parent		= &pdev->dev;

	watchdog_init_timeout(wdd, heartbeat, dev);

	dev_info(dev, "heartbeat %d sec\n", wdd->timeout);

	watchdog_set_drvdata(wdd, davinci_wdt);
	watchdog_set_nowayout(wdd, 1);
	watchdog_set_restart_priority(wdd, 128);

	davinci_wdt->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(davinci_wdt->base)) {
		ret = PTR_ERR(davinci_wdt->base);
		goto err_clk_disable;
	}

	ret = watchdog_register_device(wdd);
	if (ret) {
		dev_err(dev, "cannot register watchdog device\n");
		goto err_clk_disable;
	}

	return 0;

err_clk_disable:
	clk_disable_unprepare(davinci_wdt->clk);

	return ret;
}

static int davinci_wdt_remove(struct platform_device *pdev)
{
	struct davinci_wdt_device *davinci_wdt = platform_get_drvdata(pdev);

	watchdog_unregister_device(&davinci_wdt->wdd);
	clk_disable_unprepare(davinci_wdt->clk);

	return 0;
}

static const struct of_device_id davinci_wdt_of_match[] = {
	{ .compatible = "ti,davinci-wdt", },
	{},
};
MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);

static struct platform_driver platform_wdt_driver = {
	.driver = {
		.name = "davinci-wdt",
		.of_match_table = davinci_wdt_of_match,
	},
	.probe = davinci_wdt_probe,
	.remove = davinci_wdt_remove,
};

module_platform_driver(platform_wdt_driver);

MODULE_AUTHOR("Texas Instruments");
MODULE_DESCRIPTION("DaVinci Watchdog Driver");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
		 "Watchdog heartbeat period in seconds from 1 to "
		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
		 __MODULE_STRING(DEFAULT_HEARTBEAT));

MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:davinci-wdt");
Commit	Line	Data
7d831bf5 VB	1	/*
	2	* drivers/char/watchdog/davinci_wdt.c
	3	*
	4	* Watchdog driver for DaVinci DM644x/DM646x processors
	5	*
f48f3cea	6	* Copyright (C) 2006-2013 Texas Instruments.
7d831bf5 VB	7	*
	8	* 2007 (c) MontaVista Software, Inc. This file is licensed under
	9	* the terms of the GNU General Public License version 2. This program
	10	* is licensed "as is" without any warranty of any kind, whether express
	11	* or implied.
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/moduleparam.h>
ac316725	16	#include <linux/mod_devicetable.h>
7d831bf5 VB	17	#include <linux/types.h>
7d831bf5 VB	18	#include <linux/kernel.h>
7d831bf5	19	#include <linux/watchdog.h>
7d831bf5	20	#include <linux/platform_device.h>
f78b0a8f	21	#include <linux/io.h>
371d3525	22	#include <linux/device.h>
9fd868f4	23	#include <linux/clk.h>
6330c707	24	#include <linux/err.h>
7d831bf5 VB	25
	26	#define MODULE_NAME "DAVINCI-WDT: "
	27
	28	#define DEFAULT_HEARTBEAT 60
	29	#define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
	30
	31	/* Timer register set definition */
	32	#define PID12 (0x0)
	33	#define EMUMGT (0x4)
	34	#define TIM12 (0x10)
	35	#define TIM34 (0x14)
	36	#define PRD12 (0x18)
	37	#define PRD34 (0x1C)
	38	#define TCR (0x20)
	39	#define TGCR (0x24)
	40	#define WDTCR (0x28)
	41
	42	/* TCR bit definitions */
	43	#define ENAMODE12_DISABLED (0 << 6)
	44	#define ENAMODE12_ONESHOT (1 << 6)
	45	#define ENAMODE12_PERIODIC (2 << 6)
	46
	47	/* TGCR bit definitions */
	48	#define TIM12RS_UNRESET (1 << 0)
	49	#define TIM34RS_UNRESET (1 << 1)
	50	#define TIMMODE_64BIT_WDOG (2 << 2)
	51
	52	/* WDTCR bit definitions */
	53	#define WDEN (1 << 14)
	54	#define WDFLAG (1 << 15)
	55	#define WDKEY_SEQ0 (0xa5c6 << 16)
	56	#define WDKEY_SEQ1 (0xda7e << 16)
	57
f48f3cea	58	static int heartbeat;
6d9a6cf5 IK	59
	60	/*
	61	* struct to hold data for each WDT device
	62	* @base - base io address of WD device
	63	* @clk - source clock of WDT
	64	* @wdd - hold watchdog device as is in WDT core
	65	*/
	66	struct davinci_wdt_device {
	67	void __iomem *base;
	68	struct clk *clk;
	69	struct watchdog_device wdd;
	70	};
7d831bf5	71
f48f3cea	72	static int davinci_wdt_start(struct watchdog_device *wdd)
7d831bf5 VB	73	{
	74	u32 tgcr;
	75	u32 timer_margin;
9fd868f4	76	unsigned long wdt_freq;
6d9a6cf5	77	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
9fd868f4	78
6d9a6cf5	79	wdt_freq = clk_get_rate(davinci_wdt->clk);
7d831bf5	80
7d831bf5	81	/* disable, internal clock source */
6d9a6cf5	82	iowrite32(0, davinci_wdt->base + TCR);
7d831bf5	83	/* reset timer, set mode to 64-bit watchdog, and unreset */
6d9a6cf5	84	iowrite32(0, davinci_wdt->base + TGCR);
7d831bf5	85	tgcr = TIMMODE_64BIT_WDOG \| TIM12RS_UNRESET \| TIM34RS_UNRESET;
6d9a6cf5	86	iowrite32(tgcr, davinci_wdt->base + TGCR);
7d831bf5	87	/* clear counter regs */
6d9a6cf5 IK	88	iowrite32(0, davinci_wdt->base + TIM12);
6d9a6cf5 IK	89	iowrite32(0, davinci_wdt->base + TIM34);
7d831bf5	90	/* set timeout period */
f48f3cea	91	timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
6d9a6cf5	92	iowrite32(timer_margin, davinci_wdt->base + PRD12);
f48f3cea	93	timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
6d9a6cf5	94	iowrite32(timer_margin, davinci_wdt->base + PRD34);
7d831bf5	95	/* enable run continuously */
6d9a6cf5	96	iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
7d831bf5 VB	97	/* Once the WDT is in pre-active state write to
	98	* TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
	99	* write protected (except for the WDKEY field)
	100	*/
	101	/* put watchdog in pre-active state */
6d9a6cf5	102	iowrite32(WDKEY_SEQ0 \| WDEN, davinci_wdt->base + WDTCR);
7d831bf5	103	/* put watchdog in active state */
6d9a6cf5	104	iowrite32(WDKEY_SEQ1 \| WDEN, davinci_wdt->base + WDTCR);
f48f3cea	105	return 0;
7d831bf5 VB	106	}
7d831bf5 VB	107
f48f3cea	108	static int davinci_wdt_ping(struct watchdog_device *wdd)
7d831bf5	109	{
6d9a6cf5 IK	110	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
6d9a6cf5 IK	111
f48f3cea	112	/* put watchdog in service state */
6d9a6cf5	113	iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
f48f3cea	114	/* put watchdog in active state */
6d9a6cf5	115	iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
f48f3cea	116	return 0;
7d831bf5 VB	117	}
7d831bf5 VB	118
a7719949 IK	119	static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
	120	{
	121	u64 timer_counter;
	122	unsigned long freq;
	123	u32 val;
	124	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
	125
	126	/* if timeout has occured then return 0 */
	127	val = ioread32(davinci_wdt->base + WDTCR);
	128	if (val & WDFLAG)
	129	return 0;
	130
	131	freq = clk_get_rate(davinci_wdt->clk);
	132
	133	if (!freq)
	134	return 0;
	135
	136	timer_counter = ioread32(davinci_wdt->base + TIM12);
	137	timer_counter \|= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);
	138
	139	do_div(timer_counter, freq);
	140
	141	return wdd->timeout - timer_counter;
	142	}
	143
71d1f058 DL	144	static int davinci_wdt_restart(struct watchdog_device *wdd,
	145	unsigned long action, void *data)
	146	{
	147	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
	148	u32 tgcr, wdtcr;
	149
	150	/* disable, internal clock source */
	151	iowrite32(0, davinci_wdt->base + TCR);
	152
	153	/* reset timer, set mode to 64-bit watchdog, and unreset */
	154	tgcr = 0;
	155	iowrite32(tgcr, davinci_wdt->base + TGCR);
	156	tgcr = TIMMODE_64BIT_WDOG \| TIM12RS_UNRESET \| TIM34RS_UNRESET;
	157	iowrite32(tgcr, davinci_wdt->base + TGCR);
	158
	159	/* clear counter and period regs */
	160	iowrite32(0, davinci_wdt->base + TIM12);
	161	iowrite32(0, davinci_wdt->base + TIM34);
	162	iowrite32(0, davinci_wdt->base + PRD12);
	163	iowrite32(0, davinci_wdt->base + PRD34);
	164
	165	/* put watchdog in pre-active state */
	166	wdtcr = WDKEY_SEQ0 \| WDEN;
	167	iowrite32(wdtcr, davinci_wdt->base + WDTCR);
	168
	169	/* put watchdog in active state */
	170	wdtcr = WDKEY_SEQ1 \| WDEN;
	171	iowrite32(wdtcr, davinci_wdt->base + WDTCR);
	172
	173	/* write an invalid value to the WDKEY field to trigger a restart */
	174	wdtcr = 0x00004000;
	175	iowrite32(wdtcr, davinci_wdt->base + WDTCR);
	176
	177	return 0;
	178	}
	179
f48f3cea	180	static const struct watchdog_info davinci_wdt_info = {
f1a08cc9	181	.options = WDIOF_KEEPALIVEPING,
8832b200	182	.identity = "DaVinci/Keystone Watchdog",
7d831bf5 VB	183	};
7d831bf5 VB	184
f48f3cea IK	185	static const struct watchdog_ops davinci_wdt_ops = {
	186	.owner = THIS_MODULE,
	187	.start = davinci_wdt_start,
	188	.stop = davinci_wdt_ping,
	189	.ping = davinci_wdt_ping,
a7719949	190	.get_timeleft = davinci_wdt_get_timeleft,
71d1f058	191	.restart = davinci_wdt_restart,
7d831bf5 VB	192	};
7d831bf5 VB	193
2d991a16	194	static int davinci_wdt_probe(struct platform_device *pdev)
7d831bf5	195	{
e20880e6	196	int ret = 0;
371d3525	197	struct device *dev = &pdev->dev;
f48f3cea	198	struct watchdog_device *wdd;
6d9a6cf5 IK	199	struct davinci_wdt_device *davinci_wdt;
	200
	201	davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
	202	if (!davinci_wdt)
	203	return -ENOMEM;
7d831bf5	204
6d9a6cf5	205	davinci_wdt->clk = devm_clk_get(dev, NULL);
9b386574 TK	206
	207	if (IS_ERR(davinci_wdt->clk)) {
	208	if (PTR_ERR(davinci_wdt->clk) != -EPROBE_DEFER)
	209	dev_err(&pdev->dev, "failed to get clock node\n");
6d9a6cf5	210	return PTR_ERR(davinci_wdt->clk);
9b386574	211	}
9fd868f4	212
8f11eb58 AY	213	ret = clk_prepare_enable(davinci_wdt->clk);
	214	if (ret) {
	215	dev_err(&pdev->dev, "failed to prepare clock\n");
	216	return ret;
	217	}
9fd868f4	218
6d9a6cf5 IK	219	platform_set_drvdata(pdev, davinci_wdt);
	220
	221	wdd = &davinci_wdt->wdd;
f48f3cea IK	222	wdd->info = &davinci_wdt_info;
	223	wdd->ops = &davinci_wdt_ops;
	224	wdd->min_timeout = 1;
	225	wdd->max_timeout = MAX_HEARTBEAT;
	226	wdd->timeout = DEFAULT_HEARTBEAT;
6551881c	227	wdd->parent = &pdev->dev;
f48f3cea IK	228
	229	watchdog_init_timeout(wdd, heartbeat, dev);
	230
	231	dev_info(dev, "heartbeat %d sec\n", wdd->timeout);
7d831bf5	232
6d9a6cf5	233	watchdog_set_drvdata(wdd, davinci_wdt);
f48f3cea	234	watchdog_set_nowayout(wdd, 1);
71d1f058	235	watchdog_set_restart_priority(wdd, 128);
7d831bf5	236
0f0a6a28	237	davinci_wdt->base = devm_platform_ioremap_resource(pdev, 0);
d66e5364 AK	238	if (IS_ERR(davinci_wdt->base)) {
	239	ret = PTR_ERR(davinci_wdt->base);
	240	goto err_clk_disable;
	241	}
7d831bf5	242
f48f3cea	243	ret = watchdog_register_device(wdd);
d66e5364	244	if (ret) {
f48f3cea	245	dev_err(dev, "cannot register watchdog device\n");
d66e5364	246	goto err_clk_disable;
737bcff5	247	}
7d831bf5	248
d66e5364 AK	249	return 0;
	250
	251	err_clk_disable:
	252	clk_disable_unprepare(davinci_wdt->clk);
	253
7d831bf5 VB	254	return ret;
	255	}
	256
4b12b896	257	static int davinci_wdt_remove(struct platform_device *pdev)
7d831bf5	258	{
6d9a6cf5 IK	259	struct davinci_wdt_device *davinci_wdt = platform_get_drvdata(pdev);
	260
	261	watchdog_unregister_device(&davinci_wdt->wdd);
	262	clk_disable_unprepare(davinci_wdt->clk);
9fd868f4	263
7d831bf5 VB	264	return 0;
	265	}
	266
902e2e7d MK	267	static const struct of_device_id davinci_wdt_of_match[] = {
	268	{ .compatible = "ti,davinci-wdt", },
	269	{},
	270	};
	271	MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
	272
7d831bf5 VB	273	static struct platform_driver platform_wdt_driver = {
7d831bf5 VB	274	.driver = {
84374812	275	.name = "davinci-wdt",
902e2e7d	276	.of_match_table = davinci_wdt_of_match,
7d831bf5 VB	277	},
7d831bf5 VB	278	.probe = davinci_wdt_probe,
82268714	279	.remove = davinci_wdt_remove,
7d831bf5 VB	280	};
7d831bf5 VB	281
b8ec6118	282	module_platform_driver(platform_wdt_driver);
7d831bf5 VB	283
	284	MODULE_AUTHOR("Texas Instruments");
	285	MODULE_DESCRIPTION("DaVinci Watchdog Driver");
	286
	287	module_param(heartbeat, int, 0);
	288	MODULE_PARM_DESC(heartbeat,
	289	"Watchdog heartbeat period in seconds from 1 to "
	290	__MODULE_STRING(MAX_HEARTBEAT) ", default "
	291	__MODULE_STRING(DEFAULT_HEARTBEAT));
	292
	293	MODULE_LICENSE("GPL");
84374812	294	MODULE_ALIAS("platform:davinci-wdt");