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d0173278 | 1 | // SPDX-License-Identifier: GPL-2.0 |
7d831bf5 VB |
2 | /* |
3 | * drivers/char/watchdog/davinci_wdt.c | |
4 | * | |
5 | * Watchdog driver for DaVinci DM644x/DM646x processors | |
6 | * | |
f48f3cea | 7 | * Copyright (C) 2006-2013 Texas Instruments. |
7d831bf5 | 8 | * |
d0173278 | 9 | * 2007 (c) MontaVista Software, Inc. |
7d831bf5 VB |
10 | */ |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
ac316725 | 14 | #include <linux/mod_devicetable.h> |
7d831bf5 VB |
15 | #include <linux/types.h> |
16 | #include <linux/kernel.h> | |
7d831bf5 | 17 | #include <linux/watchdog.h> |
7d831bf5 | 18 | #include <linux/platform_device.h> |
f78b0a8f | 19 | #include <linux/io.h> |
371d3525 | 20 | #include <linux/device.h> |
9fd868f4 | 21 | #include <linux/clk.h> |
6330c707 | 22 | #include <linux/err.h> |
7d831bf5 VB |
23 | |
24 | #define MODULE_NAME "DAVINCI-WDT: " | |
25 | ||
26 | #define DEFAULT_HEARTBEAT 60 | |
27 | #define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/ | |
28 | ||
29 | /* Timer register set definition */ | |
30 | #define PID12 (0x0) | |
31 | #define EMUMGT (0x4) | |
32 | #define TIM12 (0x10) | |
33 | #define TIM34 (0x14) | |
34 | #define PRD12 (0x18) | |
35 | #define PRD34 (0x1C) | |
36 | #define TCR (0x20) | |
37 | #define TGCR (0x24) | |
38 | #define WDTCR (0x28) | |
39 | ||
40 | /* TCR bit definitions */ | |
41 | #define ENAMODE12_DISABLED (0 << 6) | |
42 | #define ENAMODE12_ONESHOT (1 << 6) | |
43 | #define ENAMODE12_PERIODIC (2 << 6) | |
44 | ||
45 | /* TGCR bit definitions */ | |
46 | #define TIM12RS_UNRESET (1 << 0) | |
47 | #define TIM34RS_UNRESET (1 << 1) | |
48 | #define TIMMODE_64BIT_WDOG (2 << 2) | |
49 | ||
50 | /* WDTCR bit definitions */ | |
51 | #define WDEN (1 << 14) | |
52 | #define WDFLAG (1 << 15) | |
53 | #define WDKEY_SEQ0 (0xa5c6 << 16) | |
54 | #define WDKEY_SEQ1 (0xda7e << 16) | |
55 | ||
f48f3cea | 56 | static int heartbeat; |
6d9a6cf5 IK |
57 | |
58 | /* | |
59 | * struct to hold data for each WDT device | |
60 | * @base - base io address of WD device | |
61 | * @clk - source clock of WDT | |
62 | * @wdd - hold watchdog device as is in WDT core | |
63 | */ | |
64 | struct davinci_wdt_device { | |
65 | void __iomem *base; | |
66 | struct clk *clk; | |
67 | struct watchdog_device wdd; | |
68 | }; | |
7d831bf5 | 69 | |
f48f3cea | 70 | static int davinci_wdt_start(struct watchdog_device *wdd) |
7d831bf5 VB |
71 | { |
72 | u32 tgcr; | |
73 | u32 timer_margin; | |
9fd868f4 | 74 | unsigned long wdt_freq; |
6d9a6cf5 | 75 | struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd); |
9fd868f4 | 76 | |
6d9a6cf5 | 77 | wdt_freq = clk_get_rate(davinci_wdt->clk); |
7d831bf5 | 78 | |
7d831bf5 | 79 | /* disable, internal clock source */ |
6d9a6cf5 | 80 | iowrite32(0, davinci_wdt->base + TCR); |
7d831bf5 | 81 | /* reset timer, set mode to 64-bit watchdog, and unreset */ |
6d9a6cf5 | 82 | iowrite32(0, davinci_wdt->base + TGCR); |
7d831bf5 | 83 | tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET; |
6d9a6cf5 | 84 | iowrite32(tgcr, davinci_wdt->base + TGCR); |
7d831bf5 | 85 | /* clear counter regs */ |
6d9a6cf5 IK |
86 | iowrite32(0, davinci_wdt->base + TIM12); |
87 | iowrite32(0, davinci_wdt->base + TIM34); | |
7d831bf5 | 88 | /* set timeout period */ |
f48f3cea | 89 | timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff); |
6d9a6cf5 | 90 | iowrite32(timer_margin, davinci_wdt->base + PRD12); |
f48f3cea | 91 | timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32); |
6d9a6cf5 | 92 | iowrite32(timer_margin, davinci_wdt->base + PRD34); |
7d831bf5 | 93 | /* enable run continuously */ |
6d9a6cf5 | 94 | iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR); |
7d831bf5 VB |
95 | /* Once the WDT is in pre-active state write to |
96 | * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are | |
97 | * write protected (except for the WDKEY field) | |
98 | */ | |
99 | /* put watchdog in pre-active state */ | |
6d9a6cf5 | 100 | iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR); |
7d831bf5 | 101 | /* put watchdog in active state */ |
6d9a6cf5 | 102 | iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR); |
f48f3cea | 103 | return 0; |
7d831bf5 VB |
104 | } |
105 | ||
f48f3cea | 106 | static int davinci_wdt_ping(struct watchdog_device *wdd) |
7d831bf5 | 107 | { |
6d9a6cf5 IK |
108 | struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd); |
109 | ||
f48f3cea | 110 | /* put watchdog in service state */ |
6d9a6cf5 | 111 | iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR); |
f48f3cea | 112 | /* put watchdog in active state */ |
6d9a6cf5 | 113 | iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR); |
f48f3cea | 114 | return 0; |
7d831bf5 VB |
115 | } |
116 | ||
a7719949 IK |
117 | static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd) |
118 | { | |
119 | u64 timer_counter; | |
120 | unsigned long freq; | |
121 | u32 val; | |
122 | struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd); | |
123 | ||
124 | /* if timeout has occured then return 0 */ | |
125 | val = ioread32(davinci_wdt->base + WDTCR); | |
126 | if (val & WDFLAG) | |
127 | return 0; | |
128 | ||
129 | freq = clk_get_rate(davinci_wdt->clk); | |
130 | ||
131 | if (!freq) | |
132 | return 0; | |
133 | ||
134 | timer_counter = ioread32(davinci_wdt->base + TIM12); | |
135 | timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32); | |
136 | ||
1fc8a2c0 | 137 | timer_counter = div64_ul(timer_counter, freq); |
a7719949 IK |
138 | |
139 | return wdd->timeout - timer_counter; | |
140 | } | |
141 | ||
71d1f058 DL |
142 | static int davinci_wdt_restart(struct watchdog_device *wdd, |
143 | unsigned long action, void *data) | |
144 | { | |
145 | struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd); | |
146 | u32 tgcr, wdtcr; | |
147 | ||
148 | /* disable, internal clock source */ | |
149 | iowrite32(0, davinci_wdt->base + TCR); | |
150 | ||
151 | /* reset timer, set mode to 64-bit watchdog, and unreset */ | |
152 | tgcr = 0; | |
153 | iowrite32(tgcr, davinci_wdt->base + TGCR); | |
154 | tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET; | |
155 | iowrite32(tgcr, davinci_wdt->base + TGCR); | |
156 | ||
157 | /* clear counter and period regs */ | |
158 | iowrite32(0, davinci_wdt->base + TIM12); | |
159 | iowrite32(0, davinci_wdt->base + TIM34); | |
160 | iowrite32(0, davinci_wdt->base + PRD12); | |
161 | iowrite32(0, davinci_wdt->base + PRD34); | |
162 | ||
163 | /* put watchdog in pre-active state */ | |
164 | wdtcr = WDKEY_SEQ0 | WDEN; | |
165 | iowrite32(wdtcr, davinci_wdt->base + WDTCR); | |
166 | ||
167 | /* put watchdog in active state */ | |
168 | wdtcr = WDKEY_SEQ1 | WDEN; | |
169 | iowrite32(wdtcr, davinci_wdt->base + WDTCR); | |
170 | ||
171 | /* write an invalid value to the WDKEY field to trigger a restart */ | |
172 | wdtcr = 0x00004000; | |
173 | iowrite32(wdtcr, davinci_wdt->base + WDTCR); | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
f48f3cea | 178 | static const struct watchdog_info davinci_wdt_info = { |
f1a08cc9 | 179 | .options = WDIOF_KEEPALIVEPING, |
8832b200 | 180 | .identity = "DaVinci/Keystone Watchdog", |
7d831bf5 VB |
181 | }; |
182 | ||
f48f3cea IK |
183 | static const struct watchdog_ops davinci_wdt_ops = { |
184 | .owner = THIS_MODULE, | |
185 | .start = davinci_wdt_start, | |
186 | .stop = davinci_wdt_ping, | |
187 | .ping = davinci_wdt_ping, | |
a7719949 | 188 | .get_timeleft = davinci_wdt_get_timeleft, |
71d1f058 | 189 | .restart = davinci_wdt_restart, |
7d831bf5 VB |
190 | }; |
191 | ||
cecda010 GR |
192 | static void davinci_clk_disable_unprepare(void *data) |
193 | { | |
194 | clk_disable_unprepare(data); | |
195 | } | |
196 | ||
2d991a16 | 197 | static int davinci_wdt_probe(struct platform_device *pdev) |
7d831bf5 | 198 | { |
e20880e6 | 199 | int ret = 0; |
371d3525 | 200 | struct device *dev = &pdev->dev; |
f48f3cea | 201 | struct watchdog_device *wdd; |
6d9a6cf5 IK |
202 | struct davinci_wdt_device *davinci_wdt; |
203 | ||
204 | davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL); | |
205 | if (!davinci_wdt) | |
206 | return -ENOMEM; | |
7d831bf5 | 207 | |
6d9a6cf5 | 208 | davinci_wdt->clk = devm_clk_get(dev, NULL); |
fc772040 KK |
209 | if (IS_ERR(davinci_wdt->clk)) |
210 | return dev_err_probe(dev, PTR_ERR(davinci_wdt->clk), | |
211 | "failed to get clock node\n"); | |
9fd868f4 | 212 | |
8f11eb58 AY |
213 | ret = clk_prepare_enable(davinci_wdt->clk); |
214 | if (ret) { | |
cecda010 | 215 | dev_err(dev, "failed to prepare clock\n"); |
8f11eb58 AY |
216 | return ret; |
217 | } | |
cecda010 GR |
218 | ret = devm_add_action_or_reset(dev, davinci_clk_disable_unprepare, |
219 | davinci_wdt->clk); | |
220 | if (ret) | |
221 | return ret; | |
9fd868f4 | 222 | |
6d9a6cf5 IK |
223 | platform_set_drvdata(pdev, davinci_wdt); |
224 | ||
225 | wdd = &davinci_wdt->wdd; | |
f48f3cea IK |
226 | wdd->info = &davinci_wdt_info; |
227 | wdd->ops = &davinci_wdt_ops; | |
228 | wdd->min_timeout = 1; | |
229 | wdd->max_timeout = MAX_HEARTBEAT; | |
230 | wdd->timeout = DEFAULT_HEARTBEAT; | |
cecda010 | 231 | wdd->parent = dev; |
f48f3cea IK |
232 | |
233 | watchdog_init_timeout(wdd, heartbeat, dev); | |
234 | ||
235 | dev_info(dev, "heartbeat %d sec\n", wdd->timeout); | |
7d831bf5 | 236 | |
6d9a6cf5 | 237 | watchdog_set_drvdata(wdd, davinci_wdt); |
f48f3cea | 238 | watchdog_set_nowayout(wdd, 1); |
71d1f058 | 239 | watchdog_set_restart_priority(wdd, 128); |
7d831bf5 | 240 | |
0f0a6a28 | 241 | davinci_wdt->base = devm_platform_ioremap_resource(pdev, 0); |
cecda010 GR |
242 | if (IS_ERR(davinci_wdt->base)) |
243 | return PTR_ERR(davinci_wdt->base); | |
7d831bf5 | 244 | |
6ab6d33e | 245 | return devm_watchdog_register_device(dev, wdd); |
7d831bf5 VB |
246 | } |
247 | ||
902e2e7d MK |
248 | static const struct of_device_id davinci_wdt_of_match[] = { |
249 | { .compatible = "ti,davinci-wdt", }, | |
250 | {}, | |
251 | }; | |
252 | MODULE_DEVICE_TABLE(of, davinci_wdt_of_match); | |
253 | ||
7d831bf5 VB |
254 | static struct platform_driver platform_wdt_driver = { |
255 | .driver = { | |
84374812 | 256 | .name = "davinci-wdt", |
902e2e7d | 257 | .of_match_table = davinci_wdt_of_match, |
7d831bf5 VB |
258 | }, |
259 | .probe = davinci_wdt_probe, | |
7d831bf5 VB |
260 | }; |
261 | ||
b8ec6118 | 262 | module_platform_driver(platform_wdt_driver); |
7d831bf5 VB |
263 | |
264 | MODULE_AUTHOR("Texas Instruments"); | |
265 | MODULE_DESCRIPTION("DaVinci Watchdog Driver"); | |
266 | ||
267 | module_param(heartbeat, int, 0); | |
268 | MODULE_PARM_DESC(heartbeat, | |
269 | "Watchdog heartbeat period in seconds from 1 to " | |
270 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | |
271 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | |
272 | ||
273 | MODULE_LICENSE("GPL"); | |
84374812 | 274 | MODULE_ALIAS("platform:davinci-wdt"); |