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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
a2f40ccd | 2 | /* |
a2f40ccd KG |
3 | * Watchdog timer for PowerPC Book-E systems |
4 | * | |
5 | * Author: Matthew McClintock | |
4c8d3d99 | 6 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
a2f40ccd | 7 | * |
112e7546 | 8 | * Copyright 2005, 2008, 2010-2011 Freescale Semiconductor Inc. |
a2f40ccd KG |
9 | */ |
10 | ||
27c766aa JP |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
12 | ||
a2f40ccd | 13 | #include <linux/module.h> |
f172ddc6 | 14 | #include <linux/smp.h> |
a2f40ccd KG |
15 | #include <linux/watchdog.h> |
16 | ||
17 | #include <asm/reg_booke.h> | |
dcfb7484 CF |
18 | #include <asm/time.h> |
19 | #include <asm/div64.h> | |
a2f40ccd | 20 | |
40ebbcbf | 21 | /* If the kernel parameter wdt=1, the watchdog will be enabled at boot. |
a2f40ccd KG |
22 | * Also, the wdt_period sets the watchdog timer period timeout. |
23 | * For E500 cpus the wdt_period sets which bit changing from 0->1 will | |
d08ec7be | 24 | * trigger a watchdog timeout. This watchdog timeout will occur 3 times, the |
a2f40ccd KG |
25 | * first time nothing will happen, the second time a watchdog exception will |
26 | * occur, and the final time the board will reset. | |
27 | */ | |
28 | ||
a2f40ccd | 29 | |
be0884ce | 30 | #ifdef CONFIG_PPC_FSL_BOOK3E |
dcfb7484 | 31 | #define WDTP(x) ((((x)&0x3)<<30)|(((x)&0x3c)<<15)) |
0fb06571 | 32 | #define WDTP_MASK (WDTP(0x3f)) |
a2f40ccd KG |
33 | #else |
34 | #define WDTP(x) (TCR_WP(x)) | |
0a0e9e0c | 35 | #define WDTP_MASK (TCR_WP_MASK) |
a2f40ccd KG |
36 | #endif |
37 | ||
62ce2543 PK |
38 | static bool booke_wdt_enabled; |
39 | module_param(booke_wdt_enabled, bool, 0); | |
40 | static int booke_wdt_period = CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT; | |
41 | module_param(booke_wdt_period, int, 0); | |
ee86a03a TM |
42 | static bool nowayout = WATCHDOG_NOWAYOUT; |
43 | module_param(nowayout, bool, 0); | |
44 | MODULE_PARM_DESC(nowayout, | |
45 | "Watchdog cannot be stopped once started (default=" | |
46 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
d2deebab | 47 | |
52e5cc4e | 48 | #ifdef CONFIG_PPC_FSL_BOOK3E |
f172ddc6 | 49 | |
dcfb7484 CF |
50 | /* For the specified period, determine the number of seconds |
51 | * corresponding to the reset time. There will be a watchdog | |
52 | * exception at approximately 3/5 of this time. | |
53 | * | |
54 | * The formula to calculate this is given by: | |
55 | * 2.5 * (2^(63-period+1)) / timebase_freq | |
56 | * | |
57 | * In order to simplify things, we assume that period is | |
58 | * at least 1. This will still result in a very long timeout. | |
59 | */ | |
60 | static unsigned long long period_to_sec(unsigned int period) | |
61 | { | |
62 | unsigned long long tmp = 1ULL << (64 - period); | |
63 | unsigned long tmp2 = ppc_tb_freq; | |
64 | ||
65 | /* tmp may be a very large number and we don't want to overflow, | |
66 | * so divide the timebase freq instead of multiplying tmp | |
67 | */ | |
68 | tmp2 = tmp2 / 5 * 2; | |
69 | ||
70 | do_div(tmp, tmp2); | |
71 | return tmp; | |
72 | } | |
73 | ||
74 | /* | |
75 | * This procedure will find the highest period which will give a timeout | |
76 | * greater than the one required. e.g. for a bus speed of 66666666 and | |
77 | * and a parameter of 2 secs, then this procedure will return a value of 38. | |
78 | */ | |
79 | static unsigned int sec_to_period(unsigned int secs) | |
80 | { | |
81 | unsigned int period; | |
82 | for (period = 63; period > 0; period--) { | |
83 | if (period_to_sec(period) >= secs) | |
84 | return period; | |
85 | } | |
86 | return 0; | |
87 | } | |
88 | ||
52e5cc4e GR |
89 | #define MAX_WDT_TIMEOUT period_to_sec(1) |
90 | ||
91 | #else /* CONFIG_PPC_FSL_BOOK3E */ | |
92 | ||
93 | static unsigned long long period_to_sec(unsigned int period) | |
94 | { | |
95 | return period; | |
96 | } | |
97 | ||
98 | static unsigned int sec_to_period(unsigned int secs) | |
99 | { | |
100 | return secs; | |
101 | } | |
102 | ||
103 | #define MAX_WDT_TIMEOUT 3 /* from Kconfig */ | |
104 | ||
105 | #endif /* !CONFIG_PPC_FSL_BOOK3E */ | |
106 | ||
6ae98ed1 RV |
107 | static void __booke_wdt_set(void *data) |
108 | { | |
109 | u32 val; | |
d2deebab | 110 | struct watchdog_device *wdog = data; |
6ae98ed1 RV |
111 | |
112 | val = mfspr(SPRN_TCR); | |
113 | val &= ~WDTP_MASK; | |
d2deebab | 114 | val |= WDTP(sec_to_period(wdog->timeout)); |
6ae98ed1 RV |
115 | |
116 | mtspr(SPRN_TCR, val); | |
117 | } | |
118 | ||
d2deebab | 119 | static void booke_wdt_set(void *data) |
6ae98ed1 | 120 | { |
d2deebab | 121 | on_each_cpu(__booke_wdt_set, data, 0); |
6ae98ed1 RV |
122 | } |
123 | ||
f172ddc6 | 124 | static void __booke_wdt_ping(void *data) |
f31909c0 SR |
125 | { |
126 | mtspr(SPRN_TSR, TSR_ENW|TSR_WIS); | |
127 | } | |
128 | ||
52e5cc4e | 129 | static int booke_wdt_ping(struct watchdog_device *wdog) |
f172ddc6 | 130 | { |
f6f88e9b | 131 | on_each_cpu(__booke_wdt_ping, NULL, 0); |
52e5cc4e GR |
132 | |
133 | return 0; | |
f172ddc6 CG |
134 | } |
135 | ||
136 | static void __booke_wdt_enable(void *data) | |
a2f40ccd KG |
137 | { |
138 | u32 val; | |
d2deebab | 139 | struct watchdog_device *wdog = data; |
a2f40ccd | 140 | |
f31909c0 | 141 | /* clear status before enabling watchdog */ |
f172ddc6 | 142 | __booke_wdt_ping(NULL); |
a2f40ccd | 143 | val = mfspr(SPRN_TCR); |
0a0e9e0c | 144 | val &= ~WDTP_MASK; |
d2deebab | 145 | val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(sec_to_period(wdog->timeout))); |
a2f40ccd KG |
146 | |
147 | mtspr(SPRN_TCR, val); | |
148 | } | |
149 | ||
fbdd7144 | 150 | /** |
4700df05 | 151 | * __booke_wdt_disable - disable the watchdog on the given CPU |
fbdd7144 TT |
152 | * |
153 | * This function is called on each CPU. It disables the watchdog on that CPU. | |
154 | * | |
155 | * TCR[WRC] cannot be changed once it has been set to non-zero, but we can | |
156 | * effectively disable the watchdog by setting its period to the maximum value. | |
157 | */ | |
158 | static void __booke_wdt_disable(void *data) | |
159 | { | |
160 | u32 val; | |
161 | ||
162 | val = mfspr(SPRN_TCR); | |
163 | val &= ~(TCR_WIE | WDTP_MASK); | |
164 | mtspr(SPRN_TCR, val); | |
165 | ||
166 | /* clear status to make sure nothing is pending */ | |
167 | __booke_wdt_ping(NULL); | |
168 | ||
169 | } | |
170 | ||
d2deebab | 171 | static int booke_wdt_start(struct watchdog_device *wdog) |
a2f40ccd | 172 | { |
d2deebab | 173 | on_each_cpu(__booke_wdt_enable, wdog, 0); |
52e5cc4e | 174 | pr_debug("watchdog enabled (timeout = %u sec)\n", wdog->timeout); |
a2f40ccd | 175 | |
52e5cc4e | 176 | return 0; |
a2f40ccd KG |
177 | } |
178 | ||
52e5cc4e | 179 | static int booke_wdt_stop(struct watchdog_device *wdog) |
fbdd7144 TT |
180 | { |
181 | on_each_cpu(__booke_wdt_disable, NULL, 0); | |
27c766aa | 182 | pr_debug("watchdog disabled\n"); |
5d63c134 | 183 | |
52e5cc4e GR |
184 | return 0; |
185 | } | |
186 | ||
187 | static int booke_wdt_set_timeout(struct watchdog_device *wdt_dev, | |
188 | unsigned int timeout) | |
189 | { | |
52e5cc4e | 190 | wdt_dev->timeout = timeout; |
d2deebab | 191 | booke_wdt_set(wdt_dev); |
fbdd7144 TT |
192 | |
193 | return 0; | |
194 | } | |
195 | ||
8d97005e | 196 | static struct watchdog_info booke_wdt_info __ro_after_init = { |
52e5cc4e GR |
197 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, |
198 | .identity = "PowerPC Book-E Watchdog", | |
199 | }; | |
200 | ||
b893e344 | 201 | static const struct watchdog_ops booke_wdt_ops = { |
f172ddc6 | 202 | .owner = THIS_MODULE, |
52e5cc4e GR |
203 | .start = booke_wdt_start, |
204 | .stop = booke_wdt_stop, | |
205 | .ping = booke_wdt_ping, | |
206 | .set_timeout = booke_wdt_set_timeout, | |
a2f40ccd KG |
207 | }; |
208 | ||
52e5cc4e GR |
209 | static struct watchdog_device booke_wdt_dev = { |
210 | .info = &booke_wdt_info, | |
211 | .ops = &booke_wdt_ops, | |
212 | .min_timeout = 1, | |
a2f40ccd KG |
213 | }; |
214 | ||
215 | static void __exit booke_wdt_exit(void) | |
216 | { | |
52e5cc4e | 217 | watchdog_unregister_device(&booke_wdt_dev); |
a2f40ccd KG |
218 | } |
219 | ||
a2f40ccd KG |
220 | static int __init booke_wdt_init(void) |
221 | { | |
222 | int ret = 0; | |
223 | ||
27c766aa | 224 | pr_info("powerpc book-e watchdog driver loaded\n"); |
52e5cc4e GR |
225 | booke_wdt_info.firmware_version = cur_cpu_spec->pvr_value; |
226 | booke_wdt_set_timeout(&booke_wdt_dev, | |
d2deebab | 227 | period_to_sec(booke_wdt_period)); |
52e5cc4e | 228 | watchdog_set_nowayout(&booke_wdt_dev, nowayout); |
fa928ee8 | 229 | booke_wdt_dev.max_timeout = MAX_WDT_TIMEOUT; |
52e5cc4e | 230 | if (booke_wdt_enabled) |
d2deebab | 231 | booke_wdt_start(&booke_wdt_dev); |
52e5cc4e GR |
232 | |
233 | ret = watchdog_register_device(&booke_wdt_dev); | |
a2f40ccd KG |
234 | |
235 | return ret; | |
236 | } | |
fbdd7144 TT |
237 | |
238 | module_init(booke_wdt_init); | |
239 | module_exit(booke_wdt_exit); | |
240 | ||
62ce2543 | 241 | MODULE_ALIAS("booke_wdt"); |
fbdd7144 TT |
242 | MODULE_DESCRIPTION("PowerPC Book-E watchdog driver"); |
243 | MODULE_LICENSE("GPL"); |