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2e62c498 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
938d0a84 LR |
2 | /* |
3 | * Watchdog driver for Broadcom BCM2835 | |
4 | * | |
5 | * "bcm2708_wdog" driver written by Luke Diamand that was obtained from | |
6 | * branch "rpi-3.6.y" of git://github.com/raspberrypi/linux.git was used | |
7 | * as a hardware reference for the Broadcom BCM2835 watchdog timer. | |
8 | * | |
9 | * Copyright (C) 2013 Lubomir Rintel <lkundrak@v3.sk> | |
10 | * | |
938d0a84 LR |
11 | */ |
12 | ||
33a9f5bc | 13 | #include <linux/delay.h> |
938d0a84 LR |
14 | #include <linux/types.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/watchdog.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/of_address.h> | |
33a9f5bc | 20 | #include <linux/of_platform.h> |
938d0a84 LR |
21 | |
22 | #define PM_RSTC 0x1c | |
33a9f5bc | 23 | #define PM_RSTS 0x20 |
938d0a84 LR |
24 | #define PM_WDOG 0x24 |
25 | ||
26 | #define PM_PASSWORD 0x5a000000 | |
27 | ||
28 | #define PM_WDOG_TIME_SET 0x000fffff | |
29 | #define PM_RSTC_WRCFG_CLR 0xffffffcf | |
33a9f5bc | 30 | #define PM_RSTS_HADWRH_SET 0x00000040 |
938d0a84 LR |
31 | #define PM_RSTC_WRCFG_SET 0x00000030 |
32 | #define PM_RSTC_WRCFG_FULL_RESET 0x00000020 | |
33 | #define PM_RSTC_RESET 0x00000102 | |
34 | ||
898e6861 | 35 | /* |
8ab102d6 MY |
36 | * The Raspberry Pi firmware uses the RSTS register to know which partition |
37 | * to boot from. The partition value is spread into bits 0, 2, 4, 6, 8, 10. | |
38 | * Partition 63 is a special partition used by the firmware to indicate halt. | |
898e6861 NT |
39 | */ |
40 | #define PM_RSTS_RASPBERRYPI_HALT 0x555 | |
41 | ||
938d0a84 LR |
42 | #define SECS_TO_WDOG_TICKS(x) ((x) << 16) |
43 | #define WDOG_TICKS_TO_SECS(x) ((x) >> 16) | |
44 | ||
45 | struct bcm2835_wdt { | |
46 | void __iomem *base; | |
47 | spinlock_t lock; | |
48 | }; | |
49 | ||
50 | static unsigned int heartbeat; | |
51 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
52 | ||
054ae194 RV |
53 | static bool bcm2835_wdt_is_running(struct bcm2835_wdt *wdt) |
54 | { | |
55 | uint32_t cur; | |
56 | ||
57 | cur = readl(wdt->base + PM_RSTC); | |
58 | ||
59 | return !!(cur & PM_RSTC_WRCFG_FULL_RESET); | |
60 | } | |
61 | ||
938d0a84 LR |
62 | static int bcm2835_wdt_start(struct watchdog_device *wdog) |
63 | { | |
64 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
65 | uint32_t cur; | |
66 | unsigned long flags; | |
67 | ||
68 | spin_lock_irqsave(&wdt->lock, flags); | |
69 | ||
70 | writel_relaxed(PM_PASSWORD | (SECS_TO_WDOG_TICKS(wdog->timeout) & | |
71 | PM_WDOG_TIME_SET), wdt->base + PM_WDOG); | |
72 | cur = readl_relaxed(wdt->base + PM_RSTC); | |
73 | writel_relaxed(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | | |
74 | PM_RSTC_WRCFG_FULL_RESET, wdt->base + PM_RSTC); | |
75 | ||
76 | spin_unlock_irqrestore(&wdt->lock, flags); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static int bcm2835_wdt_stop(struct watchdog_device *wdog) | |
82 | { | |
83 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
84 | ||
85 | writel_relaxed(PM_PASSWORD | PM_RSTC_RESET, wdt->base + PM_RSTC); | |
938d0a84 LR |
86 | return 0; |
87 | } | |
88 | ||
938d0a84 LR |
89 | static unsigned int bcm2835_wdt_get_timeleft(struct watchdog_device *wdog) |
90 | { | |
91 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
92 | ||
93 | uint32_t ret = readl_relaxed(wdt->base + PM_WDOG); | |
94 | return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET); | |
95 | } | |
96 | ||
71e9b2f0 GR |
97 | static void __bcm2835_restart(struct bcm2835_wdt *wdt) |
98 | { | |
99 | u32 val; | |
100 | ||
101 | /* use a timeout of 10 ticks (~150us) */ | |
102 | writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG); | |
103 | val = readl_relaxed(wdt->base + PM_RSTC); | |
104 | val &= PM_RSTC_WRCFG_CLR; | |
105 | val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET; | |
106 | writel_relaxed(val, wdt->base + PM_RSTC); | |
107 | ||
108 | /* No sleeping, possibly atomic. */ | |
109 | mdelay(1); | |
110 | } | |
111 | ||
112 | static int bcm2835_restart(struct watchdog_device *wdog, | |
113 | unsigned long action, void *data) | |
114 | { | |
115 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
116 | ||
117 | __bcm2835_restart(wdt); | |
118 | ||
119 | return 0; | |
120 | } | |
121 | ||
aea4b477 | 122 | static const struct watchdog_ops bcm2835_wdt_ops = { |
938d0a84 LR |
123 | .owner = THIS_MODULE, |
124 | .start = bcm2835_wdt_start, | |
125 | .stop = bcm2835_wdt_stop, | |
938d0a84 | 126 | .get_timeleft = bcm2835_wdt_get_timeleft, |
71e9b2f0 | 127 | .restart = bcm2835_restart, |
938d0a84 LR |
128 | }; |
129 | ||
aea4b477 | 130 | static const struct watchdog_info bcm2835_wdt_info = { |
938d0a84 LR |
131 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | |
132 | WDIOF_KEEPALIVEPING, | |
133 | .identity = "Broadcom BCM2835 Watchdog timer", | |
134 | }; | |
135 | ||
136 | static struct watchdog_device bcm2835_wdt_wdd = { | |
137 | .info = &bcm2835_wdt_info, | |
138 | .ops = &bcm2835_wdt_ops, | |
139 | .min_timeout = 1, | |
140 | .max_timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET), | |
141 | .timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET), | |
142 | }; | |
143 | ||
33a9f5bc EA |
144 | /* |
145 | * We can't really power off, but if we do the normal reset scheme, and | |
146 | * indicate to bootcode.bin not to reboot, then most of the chip will be | |
147 | * powered off. | |
148 | */ | |
149 | static void bcm2835_power_off(void) | |
150 | { | |
151 | struct device_node *np = | |
152 | of_find_compatible_node(NULL, NULL, "brcm,bcm2835-pm-wdt"); | |
153 | struct platform_device *pdev = of_find_device_by_node(np); | |
154 | struct bcm2835_wdt *wdt = platform_get_drvdata(pdev); | |
155 | u32 val; | |
156 | ||
157 | /* | |
158 | * We set the watchdog hard reset bit here to distinguish this reset | |
159 | * from the normal (full) reset. bootcode.bin will not reboot after a | |
160 | * hard reset. | |
161 | */ | |
162 | val = readl_relaxed(wdt->base + PM_RSTS); | |
898e6861 | 163 | val |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT; |
33a9f5bc EA |
164 | writel_relaxed(val, wdt->base + PM_RSTS); |
165 | ||
166 | /* Continue with normal reset mechanism */ | |
71e9b2f0 | 167 | __bcm2835_restart(wdt); |
33a9f5bc EA |
168 | } |
169 | ||
938d0a84 LR |
170 | static int bcm2835_wdt_probe(struct platform_device *pdev) |
171 | { | |
5f5aa6f1 | 172 | struct resource *res; |
938d0a84 | 173 | struct device *dev = &pdev->dev; |
938d0a84 LR |
174 | struct bcm2835_wdt *wdt; |
175 | int err; | |
176 | ||
177 | wdt = devm_kzalloc(dev, sizeof(struct bcm2835_wdt), GFP_KERNEL); | |
8deea830 | 178 | if (!wdt) |
938d0a84 | 179 | return -ENOMEM; |
938d0a84 LR |
180 | platform_set_drvdata(pdev, wdt); |
181 | ||
182 | spin_lock_init(&wdt->lock); | |
183 | ||
5f5aa6f1 GR |
184 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
185 | wdt->base = devm_ioremap_resource(dev, res); | |
186 | if (IS_ERR(wdt->base)) | |
187 | return PTR_ERR(wdt->base); | |
938d0a84 LR |
188 | |
189 | watchdog_set_drvdata(&bcm2835_wdt_wdd, wdt); | |
190 | watchdog_init_timeout(&bcm2835_wdt_wdd, heartbeat, dev); | |
191 | watchdog_set_nowayout(&bcm2835_wdt_wdd, nowayout); | |
5f5aa6f1 | 192 | bcm2835_wdt_wdd.parent = dev; |
054ae194 RV |
193 | if (bcm2835_wdt_is_running(wdt)) { |
194 | /* | |
195 | * The currently active timeout value (set by the | |
196 | * bootloader) may be different from the module | |
197 | * heartbeat parameter or the value in device | |
198 | * tree. But we just need to set WDOG_HW_RUNNING, | |
199 | * because then the framework will "immediately" ping | |
200 | * the device, updating the timeout. | |
201 | */ | |
202 | set_bit(WDOG_HW_RUNNING, &bcm2835_wdt_wdd.status); | |
203 | } | |
71e9b2f0 GR |
204 | |
205 | watchdog_set_restart_priority(&bcm2835_wdt_wdd, 128); | |
206 | ||
5f5aa6f1 GR |
207 | watchdog_stop_on_reboot(&bcm2835_wdt_wdd); |
208 | err = devm_watchdog_register_device(dev, &bcm2835_wdt_wdd); | |
938d0a84 LR |
209 | if (err) { |
210 | dev_err(dev, "Failed to register watchdog device"); | |
938d0a84 LR |
211 | return err; |
212 | } | |
213 | ||
33a9f5bc EA |
214 | if (pm_power_off == NULL) |
215 | pm_power_off = bcm2835_power_off; | |
216 | ||
938d0a84 LR |
217 | dev_info(dev, "Broadcom BCM2835 watchdog timer"); |
218 | return 0; | |
219 | } | |
220 | ||
221 | static int bcm2835_wdt_remove(struct platform_device *pdev) | |
222 | { | |
33a9f5bc EA |
223 | if (pm_power_off == bcm2835_power_off) |
224 | pm_power_off = NULL; | |
938d0a84 LR |
225 | |
226 | return 0; | |
227 | } | |
228 | ||
938d0a84 LR |
229 | static const struct of_device_id bcm2835_wdt_of_match[] = { |
230 | { .compatible = "brcm,bcm2835-pm-wdt", }, | |
231 | {}, | |
232 | }; | |
233 | MODULE_DEVICE_TABLE(of, bcm2835_wdt_of_match); | |
234 | ||
235 | static struct platform_driver bcm2835_wdt_driver = { | |
236 | .probe = bcm2835_wdt_probe, | |
237 | .remove = bcm2835_wdt_remove, | |
938d0a84 LR |
238 | .driver = { |
239 | .name = "bcm2835-wdt", | |
938d0a84 LR |
240 | .of_match_table = bcm2835_wdt_of_match, |
241 | }, | |
242 | }; | |
243 | module_platform_driver(bcm2835_wdt_driver); | |
244 | ||
245 | module_param(heartbeat, uint, 0); | |
246 | MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds"); | |
247 | ||
248 | module_param(nowayout, bool, 0); | |
249 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
250 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
251 | ||
252 | MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>"); | |
253 | MODULE_DESCRIPTION("Driver for Broadcom BCM2835 watchdog timer"); | |
254 | MODULE_LICENSE("GPL"); |