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938d0a84 LR |
1 | /* |
2 | * Watchdog driver for Broadcom BCM2835 | |
3 | * | |
4 | * "bcm2708_wdog" driver written by Luke Diamand that was obtained from | |
5 | * branch "rpi-3.6.y" of git://github.com/raspberrypi/linux.git was used | |
6 | * as a hardware reference for the Broadcom BCM2835 watchdog timer. | |
7 | * | |
8 | * Copyright (C) 2013 Lubomir Rintel <lkundrak@v3.sk> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | ||
33a9f5bc | 16 | #include <linux/delay.h> |
938d0a84 LR |
17 | #include <linux/types.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/watchdog.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/of_address.h> | |
33a9f5bc | 23 | #include <linux/of_platform.h> |
938d0a84 LR |
24 | |
25 | #define PM_RSTC 0x1c | |
33a9f5bc | 26 | #define PM_RSTS 0x20 |
938d0a84 LR |
27 | #define PM_WDOG 0x24 |
28 | ||
29 | #define PM_PASSWORD 0x5a000000 | |
30 | ||
31 | #define PM_WDOG_TIME_SET 0x000fffff | |
32 | #define PM_RSTC_WRCFG_CLR 0xffffffcf | |
33a9f5bc | 33 | #define PM_RSTS_HADWRH_SET 0x00000040 |
938d0a84 LR |
34 | #define PM_RSTC_WRCFG_SET 0x00000030 |
35 | #define PM_RSTC_WRCFG_FULL_RESET 0x00000020 | |
36 | #define PM_RSTC_RESET 0x00000102 | |
37 | ||
898e6861 | 38 | /* |
8ab102d6 MY |
39 | * The Raspberry Pi firmware uses the RSTS register to know which partition |
40 | * to boot from. The partition value is spread into bits 0, 2, 4, 6, 8, 10. | |
41 | * Partition 63 is a special partition used by the firmware to indicate halt. | |
898e6861 NT |
42 | */ |
43 | #define PM_RSTS_RASPBERRYPI_HALT 0x555 | |
44 | ||
938d0a84 LR |
45 | #define SECS_TO_WDOG_TICKS(x) ((x) << 16) |
46 | #define WDOG_TICKS_TO_SECS(x) ((x) >> 16) | |
47 | ||
48 | struct bcm2835_wdt { | |
49 | void __iomem *base; | |
50 | spinlock_t lock; | |
51 | }; | |
52 | ||
53 | static unsigned int heartbeat; | |
54 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
55 | ||
054ae194 RV |
56 | static bool bcm2835_wdt_is_running(struct bcm2835_wdt *wdt) |
57 | { | |
58 | uint32_t cur; | |
59 | ||
60 | cur = readl(wdt->base + PM_RSTC); | |
61 | ||
62 | return !!(cur & PM_RSTC_WRCFG_FULL_RESET); | |
63 | } | |
64 | ||
938d0a84 LR |
65 | static int bcm2835_wdt_start(struct watchdog_device *wdog) |
66 | { | |
67 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
68 | uint32_t cur; | |
69 | unsigned long flags; | |
70 | ||
71 | spin_lock_irqsave(&wdt->lock, flags); | |
72 | ||
73 | writel_relaxed(PM_PASSWORD | (SECS_TO_WDOG_TICKS(wdog->timeout) & | |
74 | PM_WDOG_TIME_SET), wdt->base + PM_WDOG); | |
75 | cur = readl_relaxed(wdt->base + PM_RSTC); | |
76 | writel_relaxed(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | | |
77 | PM_RSTC_WRCFG_FULL_RESET, wdt->base + PM_RSTC); | |
78 | ||
79 | spin_unlock_irqrestore(&wdt->lock, flags); | |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
84 | static int bcm2835_wdt_stop(struct watchdog_device *wdog) | |
85 | { | |
86 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
87 | ||
88 | writel_relaxed(PM_PASSWORD | PM_RSTC_RESET, wdt->base + PM_RSTC); | |
938d0a84 LR |
89 | return 0; |
90 | } | |
91 | ||
938d0a84 LR |
92 | static unsigned int bcm2835_wdt_get_timeleft(struct watchdog_device *wdog) |
93 | { | |
94 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
95 | ||
96 | uint32_t ret = readl_relaxed(wdt->base + PM_WDOG); | |
97 | return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET); | |
98 | } | |
99 | ||
71e9b2f0 GR |
100 | static void __bcm2835_restart(struct bcm2835_wdt *wdt) |
101 | { | |
102 | u32 val; | |
103 | ||
104 | /* use a timeout of 10 ticks (~150us) */ | |
105 | writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG); | |
106 | val = readl_relaxed(wdt->base + PM_RSTC); | |
107 | val &= PM_RSTC_WRCFG_CLR; | |
108 | val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET; | |
109 | writel_relaxed(val, wdt->base + PM_RSTC); | |
110 | ||
111 | /* No sleeping, possibly atomic. */ | |
112 | mdelay(1); | |
113 | } | |
114 | ||
115 | static int bcm2835_restart(struct watchdog_device *wdog, | |
116 | unsigned long action, void *data) | |
117 | { | |
118 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
119 | ||
120 | __bcm2835_restart(wdt); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
aea4b477 | 125 | static const struct watchdog_ops bcm2835_wdt_ops = { |
938d0a84 LR |
126 | .owner = THIS_MODULE, |
127 | .start = bcm2835_wdt_start, | |
128 | .stop = bcm2835_wdt_stop, | |
938d0a84 | 129 | .get_timeleft = bcm2835_wdt_get_timeleft, |
71e9b2f0 | 130 | .restart = bcm2835_restart, |
938d0a84 LR |
131 | }; |
132 | ||
aea4b477 | 133 | static const struct watchdog_info bcm2835_wdt_info = { |
938d0a84 LR |
134 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | |
135 | WDIOF_KEEPALIVEPING, | |
136 | .identity = "Broadcom BCM2835 Watchdog timer", | |
137 | }; | |
138 | ||
139 | static struct watchdog_device bcm2835_wdt_wdd = { | |
140 | .info = &bcm2835_wdt_info, | |
141 | .ops = &bcm2835_wdt_ops, | |
142 | .min_timeout = 1, | |
143 | .max_timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET), | |
144 | .timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET), | |
145 | }; | |
146 | ||
33a9f5bc EA |
147 | /* |
148 | * We can't really power off, but if we do the normal reset scheme, and | |
149 | * indicate to bootcode.bin not to reboot, then most of the chip will be | |
150 | * powered off. | |
151 | */ | |
152 | static void bcm2835_power_off(void) | |
153 | { | |
154 | struct device_node *np = | |
155 | of_find_compatible_node(NULL, NULL, "brcm,bcm2835-pm-wdt"); | |
156 | struct platform_device *pdev = of_find_device_by_node(np); | |
157 | struct bcm2835_wdt *wdt = platform_get_drvdata(pdev); | |
158 | u32 val; | |
159 | ||
160 | /* | |
161 | * We set the watchdog hard reset bit here to distinguish this reset | |
162 | * from the normal (full) reset. bootcode.bin will not reboot after a | |
163 | * hard reset. | |
164 | */ | |
165 | val = readl_relaxed(wdt->base + PM_RSTS); | |
898e6861 | 166 | val |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT; |
33a9f5bc EA |
167 | writel_relaxed(val, wdt->base + PM_RSTS); |
168 | ||
169 | /* Continue with normal reset mechanism */ | |
71e9b2f0 | 170 | __bcm2835_restart(wdt); |
33a9f5bc EA |
171 | } |
172 | ||
938d0a84 LR |
173 | static int bcm2835_wdt_probe(struct platform_device *pdev) |
174 | { | |
5f5aa6f1 | 175 | struct resource *res; |
938d0a84 | 176 | struct device *dev = &pdev->dev; |
938d0a84 LR |
177 | struct bcm2835_wdt *wdt; |
178 | int err; | |
179 | ||
180 | wdt = devm_kzalloc(dev, sizeof(struct bcm2835_wdt), GFP_KERNEL); | |
8deea830 | 181 | if (!wdt) |
938d0a84 | 182 | return -ENOMEM; |
938d0a84 LR |
183 | platform_set_drvdata(pdev, wdt); |
184 | ||
185 | spin_lock_init(&wdt->lock); | |
186 | ||
5f5aa6f1 GR |
187 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
188 | wdt->base = devm_ioremap_resource(dev, res); | |
189 | if (IS_ERR(wdt->base)) | |
190 | return PTR_ERR(wdt->base); | |
938d0a84 LR |
191 | |
192 | watchdog_set_drvdata(&bcm2835_wdt_wdd, wdt); | |
193 | watchdog_init_timeout(&bcm2835_wdt_wdd, heartbeat, dev); | |
194 | watchdog_set_nowayout(&bcm2835_wdt_wdd, nowayout); | |
5f5aa6f1 | 195 | bcm2835_wdt_wdd.parent = dev; |
054ae194 RV |
196 | if (bcm2835_wdt_is_running(wdt)) { |
197 | /* | |
198 | * The currently active timeout value (set by the | |
199 | * bootloader) may be different from the module | |
200 | * heartbeat parameter or the value in device | |
201 | * tree. But we just need to set WDOG_HW_RUNNING, | |
202 | * because then the framework will "immediately" ping | |
203 | * the device, updating the timeout. | |
204 | */ | |
205 | set_bit(WDOG_HW_RUNNING, &bcm2835_wdt_wdd.status); | |
206 | } | |
71e9b2f0 GR |
207 | |
208 | watchdog_set_restart_priority(&bcm2835_wdt_wdd, 128); | |
209 | ||
5f5aa6f1 GR |
210 | watchdog_stop_on_reboot(&bcm2835_wdt_wdd); |
211 | err = devm_watchdog_register_device(dev, &bcm2835_wdt_wdd); | |
938d0a84 LR |
212 | if (err) { |
213 | dev_err(dev, "Failed to register watchdog device"); | |
938d0a84 LR |
214 | return err; |
215 | } | |
216 | ||
33a9f5bc EA |
217 | if (pm_power_off == NULL) |
218 | pm_power_off = bcm2835_power_off; | |
219 | ||
938d0a84 LR |
220 | dev_info(dev, "Broadcom BCM2835 watchdog timer"); |
221 | return 0; | |
222 | } | |
223 | ||
224 | static int bcm2835_wdt_remove(struct platform_device *pdev) | |
225 | { | |
33a9f5bc EA |
226 | if (pm_power_off == bcm2835_power_off) |
227 | pm_power_off = NULL; | |
938d0a84 LR |
228 | |
229 | return 0; | |
230 | } | |
231 | ||
938d0a84 LR |
232 | static const struct of_device_id bcm2835_wdt_of_match[] = { |
233 | { .compatible = "brcm,bcm2835-pm-wdt", }, | |
234 | {}, | |
235 | }; | |
236 | MODULE_DEVICE_TABLE(of, bcm2835_wdt_of_match); | |
237 | ||
238 | static struct platform_driver bcm2835_wdt_driver = { | |
239 | .probe = bcm2835_wdt_probe, | |
240 | .remove = bcm2835_wdt_remove, | |
938d0a84 LR |
241 | .driver = { |
242 | .name = "bcm2835-wdt", | |
938d0a84 LR |
243 | .of_match_table = bcm2835_wdt_of_match, |
244 | }, | |
245 | }; | |
246 | module_platform_driver(bcm2835_wdt_driver); | |
247 | ||
248 | module_param(heartbeat, uint, 0); | |
249 | MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds"); | |
250 | ||
251 | module_param(nowayout, bool, 0); | |
252 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
253 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
254 | ||
255 | MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>"); | |
256 | MODULE_DESCRIPTION("Driver for Broadcom BCM2835 watchdog timer"); | |
257 | MODULE_LICENSE("GPL"); |