[linux-2.6-block.git] / drivers / watchdog / aspeed_wdt.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2016 IBM Corporation
 *
 * Joel Stanley <joel@jms.id.au>
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>

struct aspeed_wdt {
	struct watchdog_device	wdd;
	void __iomem		*base;
	u32			ctrl;
};

struct aspeed_wdt_config {
	u32 ext_pulse_width_mask;
};

static const struct aspeed_wdt_config ast2400_config = {
	.ext_pulse_width_mask = 0xff,
};

static const struct aspeed_wdt_config ast2500_config = {
	.ext_pulse_width_mask = 0xfffff,
};

static const struct of_device_id aspeed_wdt_of_table[] = {
	{ .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
	{ .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
	{ },
};
MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);

#define WDT_STATUS		0x00
#define WDT_RELOAD_VALUE	0x04
#define WDT_RESTART		0x08
#define WDT_CTRL		0x0C
#define   WDT_CTRL_BOOT_SECONDARY	BIT(7)
#define   WDT_CTRL_RESET_MODE_SOC	(0x00 << 5)
#define   WDT_CTRL_RESET_MODE_FULL_CHIP	(0x01 << 5)
#define   WDT_CTRL_RESET_MODE_ARM_CPU	(0x10 << 5)
#define   WDT_CTRL_1MHZ_CLK		BIT(4)
#define   WDT_CTRL_WDT_EXT		BIT(3)
#define   WDT_CTRL_WDT_INTR		BIT(2)
#define   WDT_CTRL_RESET_SYSTEM		BIT(1)
#define   WDT_CTRL_ENABLE		BIT(0)
#define WDT_TIMEOUT_STATUS	0x10
#define   WDT_TIMEOUT_STATUS_BOOT_SECONDARY	BIT(1)

/*
 * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
 * enabled), specifically:
 *
 * * Pulse duration
 * * Drive mode: push-pull vs open-drain
 * * Polarity: Active high or active low
 *
 * Pulse duration configuration is available on both the AST2400 and AST2500,
 * though the field changes between SoCs:
 *
 * AST2400: Bits 7:0
 * AST2500: Bits 19:0
 *
 * This difference is captured in struct aspeed_wdt_config.
 *
 * The AST2500 exposes the drive mode and polarity options, but not in a
 * regular fashion. For read purposes, bit 31 represents active high or low,
 * and bit 30 represents push-pull or open-drain. With respect to write, magic
 * values need to be written to the top byte to change the state of the drive
 * mode and polarity bits. Any other value written to the top byte has no
 * effect on the state of the drive mode or polarity bits. However, the pulse
 * width value must be preserved (as desired) if written.
 */
#define WDT_RESET_WIDTH		0x18
#define   WDT_RESET_WIDTH_ACTIVE_HIGH	BIT(31)
#define     WDT_ACTIVE_HIGH_MAGIC	(0xA5 << 24)
#define     WDT_ACTIVE_LOW_MAGIC	(0x5A << 24)
#define   WDT_RESET_WIDTH_PUSH_PULL	BIT(30)
#define     WDT_PUSH_PULL_MAGIC		(0xA8 << 24)
#define     WDT_OPEN_DRAIN_MAGIC	(0x8A << 24)

#define WDT_RESTART_MAGIC	0x4755

/* 32 bits at 1MHz, in milliseconds */
#define WDT_MAX_TIMEOUT_MS	4294967
#define WDT_DEFAULT_TIMEOUT	30
#define WDT_RATE_1MHZ		1000000

static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
{
	return container_of(wdd, struct aspeed_wdt, wdd);
}

static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
{
	wdt->ctrl |= WDT_CTRL_ENABLE;

	writel(0, wdt->base + WDT_CTRL);
	writel(count, wdt->base + WDT_RELOAD_VALUE);
	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
	writel(wdt->ctrl, wdt->base + WDT_CTRL);
}

static int aspeed_wdt_start(struct watchdog_device *wdd)
{
	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);

	aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);

	return 0;
}

static int aspeed_wdt_stop(struct watchdog_device *wdd)
{
	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);

	wdt->ctrl &= ~WDT_CTRL_ENABLE;
	writel(wdt->ctrl, wdt->base + WDT_CTRL);

	return 0;
}

static int aspeed_wdt_ping(struct watchdog_device *wdd)
{
	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);

	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);

	return 0;
}

static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
				  unsigned int timeout)
{
	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
	u32 actual;

	wdd->timeout = timeout;

	actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000);

	writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);

	return 0;
}

static int aspeed_wdt_restart(struct watchdog_device *wdd,
			      unsigned long action, void *data)
{
	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);

	wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
	aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);

	mdelay(1000);

	return 0;
}

static const struct watchdog_ops aspeed_wdt_ops = {
	.start		= aspeed_wdt_start,
	.stop		= aspeed_wdt_stop,
	.ping		= aspeed_wdt_ping,
	.set_timeout	= aspeed_wdt_set_timeout,
	.restart	= aspeed_wdt_restart,
	.owner		= THIS_MODULE,
};

static const struct watchdog_info aspeed_wdt_info = {
	.options	= WDIOF_KEEPALIVEPING
			| WDIOF_MAGICCLOSE
			| WDIOF_SETTIMEOUT,
	.identity	= KBUILD_MODNAME,
};

static int aspeed_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct aspeed_wdt_config *config;
	const struct of_device_id *ofdid;
	struct aspeed_wdt *wdt;
	struct device_node *np;
	const char *reset_type;
	u32 duration;
	u32 status;
	int ret;

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	wdt->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	/*
	 * The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only
	 * runs at 1MHz. We chose to always run at 1MHz, as there's no
	 * good reason to have a faster watchdog counter.
	 */
	wdt->wdd.info = &aspeed_wdt_info;
	wdt->wdd.ops = &aspeed_wdt_ops;
	wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
	wdt->wdd.parent = dev;

	wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
	watchdog_init_timeout(&wdt->wdd, 0, dev);

	np = dev->of_node;

	ofdid = of_match_node(aspeed_wdt_of_table, np);
	if (!ofdid)
		return -EINVAL;
	config = ofdid->data;

	wdt->ctrl = WDT_CTRL_1MHZ_CLK;

	/*
	 * Control reset on a per-device basis to ensure the
	 * host is not affected by a BMC reboot
	 */
	ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
	if (ret) {
		wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
	} else {
		if (!strcmp(reset_type, "cpu"))
			wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
				     WDT_CTRL_RESET_SYSTEM;
		else if (!strcmp(reset_type, "soc"))
			wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
				     WDT_CTRL_RESET_SYSTEM;
		else if (!strcmp(reset_type, "system"))
			wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
				     WDT_CTRL_RESET_SYSTEM;
		else if (strcmp(reset_type, "none"))
			return -EINVAL;
	}
	if (of_property_read_bool(np, "aspeed,external-signal"))
		wdt->ctrl |= WDT_CTRL_WDT_EXT;
	if (of_property_read_bool(np, "aspeed,alt-boot"))
		wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;

	if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE)  {
		/*
		 * The watchdog is running, but invoke aspeed_wdt_start() to
		 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
		 * configuration conforms to the driver's expectations.
		 * Primarily, ensure we're using the 1MHz clock source.
		 */
		aspeed_wdt_start(&wdt->wdd);
		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
	}

	if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) {
		u32 reg = readl(wdt->base + WDT_RESET_WIDTH);

		reg &= config->ext_pulse_width_mask;
		if (of_property_read_bool(np, "aspeed,ext-push-pull"))
			reg |= WDT_PUSH_PULL_MAGIC;
		else
			reg |= WDT_OPEN_DRAIN_MAGIC;

		writel(reg, wdt->base + WDT_RESET_WIDTH);

		reg &= config->ext_pulse_width_mask;
		if (of_property_read_bool(np, "aspeed,ext-active-high"))
			reg |= WDT_ACTIVE_HIGH_MAGIC;
		else
			reg |= WDT_ACTIVE_LOW_MAGIC;

		writel(reg, wdt->base + WDT_RESET_WIDTH);
	}

	if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
		u32 max_duration = config->ext_pulse_width_mask + 1;

		if (duration == 0 || duration > max_duration) {
			dev_err(dev, "Invalid pulse duration: %uus\n",
				duration);
			duration = max(1U, min(max_duration, duration));
			dev_info(dev, "Pulse duration set to %uus\n",
				 duration);
		}

		/*
		 * The watchdog is always configured with a 1MHz source, so
		 * there is no need to scale the microsecond value. However we
		 * need to offset it - from the datasheet:
		 *
		 * "This register decides the asserting duration of wdt_ext and
		 * wdt_rstarm signal. The default value is 0xFF. It means the
		 * default asserting duration of wdt_ext and wdt_rstarm is
		 * 256us."
		 *
		 * This implies a value of 0 gives a 1us pulse.
		 */
		writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
	}

	status = readl(wdt->base + WDT_TIMEOUT_STATUS);
	if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY)
		wdt->wdd.bootstatus = WDIOF_CARDRESET;

	return devm_watchdog_register_device(dev, &wdt->wdd);
}

static struct platform_driver aspeed_watchdog_driver = {
	.probe = aspeed_wdt_probe,
	.driver = {
		.name = KBUILD_MODNAME,
		.of_match_table = of_match_ptr(aspeed_wdt_of_table),
	},
};

static int __init aspeed_wdt_init(void)
{
	return platform_driver_register(&aspeed_watchdog_driver);
}
arch_initcall(aspeed_wdt_init);

static void __exit aspeed_wdt_exit(void)
{
	platform_driver_unregister(&aspeed_watchdog_driver);
}
module_exit(aspeed_wdt_exit);

MODULE_DESCRIPTION("Aspeed Watchdog Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
efa859f7 JS	2	/*
	3	* Copyright 2016 IBM Corporation
	4	*
	5	* Joel Stanley <joel@jms.id.au>
efa859f7 JS	6	*/
	7
	8	#include <linux/delay.h>
	9	#include <linux/io.h>
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/of.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/watchdog.h>
	15
	16	struct aspeed_wdt {
	17	struct watchdog_device wdd;
	18	void __iomem *base;
	19	u32 ctrl;
	20	};
	21
012c0460 AJ	22	struct aspeed_wdt_config {
	23	u32 ext_pulse_width_mask;
	24	};
	25
	26	static const struct aspeed_wdt_config ast2400_config = {
	27	.ext_pulse_width_mask = 0xff,
	28	};
	29
	30	static const struct aspeed_wdt_config ast2500_config = {
	31	.ext_pulse_width_mask = 0xfffff,
	32	};
	33
efa859f7	34	static const struct of_device_id aspeed_wdt_of_table[] = {
012c0460 AJ	35	{ .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
012c0460 AJ	36	{ .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
efa859f7 JS	37	{ },
	38	};
	39	MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
	40
	41	#define WDT_STATUS 0x00
	42	#define WDT_RELOAD_VALUE 0x04
	43	#define WDT_RESTART 0x08
	44	#define WDT_CTRL 0x0C
6ffa3402	45	#define WDT_CTRL_BOOT_SECONDARY BIT(7)
efa859f7 JS	46	#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
efa859f7 JS	47	#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
b7f0b8ad	48	#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
efa859f7 JS	49	#define WDT_CTRL_1MHZ_CLK BIT(4)
	50	#define WDT_CTRL_WDT_EXT BIT(3)
	51	#define WDT_CTRL_WDT_INTR BIT(2)
	52	#define WDT_CTRL_RESET_SYSTEM BIT(1)
	53	#define WDT_CTRL_ENABLE BIT(0)
49d4d277 EJ	54	#define WDT_TIMEOUT_STATUS 0x10
49d4d277 EJ	55	#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
efa859f7	56
012c0460 AJ	57	/*
	58	* WDT_RESET_WIDTH controls the characteristics of the external pulse (if
	59	* enabled), specifically:
	60	*
	61	* * Pulse duration
	62	* * Drive mode: push-pull vs open-drain
	63	* * Polarity: Active high or active low
	64	*
	65	* Pulse duration configuration is available on both the AST2400 and AST2500,
	66	* though the field changes between SoCs:
	67	*
	68	* AST2400: Bits 7:0
	69	* AST2500: Bits 19:0
	70	*
	71	* This difference is captured in struct aspeed_wdt_config.
	72	*
	73	* The AST2500 exposes the drive mode and polarity options, but not in a
	74	* regular fashion. For read purposes, bit 31 represents active high or low,
	75	* and bit 30 represents push-pull or open-drain. With respect to write, magic
	76	* values need to be written to the top byte to change the state of the drive
	77	* mode and polarity bits. Any other value written to the top byte has no
	78	* effect on the state of the drive mode or polarity bits. However, the pulse
	79	* width value must be preserved (as desired) if written.
	80	*/
	81	#define WDT_RESET_WIDTH 0x18
	82	#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
	83	#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
	84	#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
	85	#define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
	86	#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
	87	#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
	88
efa859f7 JS	89	#define WDT_RESTART_MAGIC 0x4755
	90
	91	/* 32 bits at 1MHz, in milliseconds */
	92	#define WDT_MAX_TIMEOUT_MS 4294967
	93	#define WDT_DEFAULT_TIMEOUT 30
	94	#define WDT_RATE_1MHZ 1000000
	95
	96	static struct aspeed_wdt to_aspeed_wdt(struct watchdog_device wdd)
	97	{
	98	return container_of(wdd, struct aspeed_wdt, wdd);
	99	}
	100
	101	static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
	102	{
	103	wdt->ctrl \|= WDT_CTRL_ENABLE;
	104
	105	writel(0, wdt->base + WDT_CTRL);
	106	writel(count, wdt->base + WDT_RELOAD_VALUE);
	107	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
	108	writel(wdt->ctrl, wdt->base + WDT_CTRL);
	109	}
	110
	111	static int aspeed_wdt_start(struct watchdog_device *wdd)
	112	{
	113	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
	114
	115	aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
	116
	117	return 0;
	118	}
	119
	120	static int aspeed_wdt_stop(struct watchdog_device *wdd)
	121	{
	122	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
	123
	124	wdt->ctrl &= ~WDT_CTRL_ENABLE;
	125	writel(wdt->ctrl, wdt->base + WDT_CTRL);
	126
	127	return 0;
	128	}
	129
	130	static int aspeed_wdt_ping(struct watchdog_device *wdd)
	131	{
	132	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
	133
	134	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
	135
	136	return 0;
	137	}
	138
	139	static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
	140	unsigned int timeout)
	141	{
	142	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
	143	u32 actual;
	144
	145	wdd->timeout = timeout;
	146
	147	actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000);
	148
	149	writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
	150	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
	151
	152	return 0;
153	}
154
155	static int aspeed_wdt_restart(struct watchdog_device *wdd,
156	unsigned long action, void *data)
157	{
158	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
159
6ffa3402	160	wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
efa859f7 JS	161	aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
	162
	163	mdelay(1000);
	164
	165	return 0;
	166	}
	167
	168	static const struct watchdog_ops aspeed_wdt_ops = {
	169	.start = aspeed_wdt_start,
	170	.stop = aspeed_wdt_stop,
	171	.ping = aspeed_wdt_ping,
	172	.set_timeout = aspeed_wdt_set_timeout,
	173	.restart = aspeed_wdt_restart,
	174	.owner = THIS_MODULE,
	175	};
	176
	177	static const struct watchdog_info aspeed_wdt_info = {
	178	.options = WDIOF_KEEPALIVEPING
	179	\| WDIOF_MAGICCLOSE
	180	\| WDIOF_SETTIMEOUT,
	181	.identity = KBUILD_MODNAME,
	182	};
	183
efa859f7 JS	184	static int aspeed_wdt_probe(struct platform_device *pdev)
efa859f7 JS	185	{
eda21ee9	186	struct device *dev = &pdev->dev;
012c0460 AJ	187	const struct aspeed_wdt_config *config;
012c0460 AJ	188	const struct of_device_id *ofdid;
efa859f7	189	struct aspeed_wdt *wdt;
b7f0b8ad CB	190	struct device_node *np;
b7f0b8ad CB	191	const char *reset_type;
012c0460	192	u32 duration;
49d4d277	193	u32 status;
efa859f7 JS	194	int ret;
efa859f7 JS	195
eda21ee9	196	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
efa859f7 JS	197	if (!wdt)
	198	return -ENOMEM;
	199
0f0a6a28	200	wdt->base = devm_platform_ioremap_resource(pdev, 0);
efa859f7 JS	201	if (IS_ERR(wdt->base))
	202	return PTR_ERR(wdt->base);
	203
	204	/*
	205	* The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only
	206	* runs at 1MHz. We chose to always run at 1MHz, as there's no
	207	* good reason to have a faster watchdog counter.
	208	*/
	209	wdt->wdd.info = &aspeed_wdt_info;
	210	wdt->wdd.ops = &aspeed_wdt_ops;
	211	wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
eda21ee9	212	wdt->wdd.parent = dev;
efa859f7 JS	213
efa859f7 JS	214	wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
eda21ee9	215	watchdog_init_timeout(&wdt->wdd, 0, dev);
efa859f7	216
eda21ee9	217	np = dev->of_node;
012c0460 AJ	218
	219	ofdid = of_match_node(aspeed_wdt_of_table, np);
	220	if (!ofdid)
	221	return -EINVAL;
	222	config = ofdid->data;
	223
b7f0b8ad CB	224	wdt->ctrl = WDT_CTRL_1MHZ_CLK;
b7f0b8ad CB	225
efa859f7 JS	226	/*
efa859f7 JS	227	* Control reset on a per-device basis to ensure the
b7f0b8ad	228	* host is not affected by a BMC reboot
efa859f7	229	*/
b7f0b8ad CB	230	ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
	231	if (ret) {
	232	wdt->ctrl \|= WDT_CTRL_RESET_MODE_SOC \| WDT_CTRL_RESET_SYSTEM;
	233	} else {
	234	if (!strcmp(reset_type, "cpu"))
d2fc8db6 MM	235	wdt->ctrl \|= WDT_CTRL_RESET_MODE_ARM_CPU \|
d2fc8db6 MM	236	WDT_CTRL_RESET_SYSTEM;
b7f0b8ad	237	else if (!strcmp(reset_type, "soc"))
d2fc8db6 MM	238	wdt->ctrl \|= WDT_CTRL_RESET_MODE_SOC \|
d2fc8db6 MM	239	WDT_CTRL_RESET_SYSTEM;
b7f0b8ad	240	else if (!strcmp(reset_type, "system"))
d2fc8db6 MM	241	wdt->ctrl \|= WDT_CTRL_RESET_MODE_FULL_CHIP \|
d2fc8db6 MM	242	WDT_CTRL_RESET_SYSTEM;
b7f0b8ad CB	243	else if (strcmp(reset_type, "none"))
	244	return -EINVAL;
	245	}
	246	if (of_property_read_bool(np, "aspeed,external-signal"))
	247	wdt->ctrl \|= WDT_CTRL_WDT_EXT;
6ffa3402 MM	248	if (of_property_read_bool(np, "aspeed,alt-boot"))
6ffa3402 MM	249	wdt->ctrl \|= WDT_CTRL_BOOT_SECONDARY;
b7f0b8ad	250
efa859f7	251	if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
9f3e13c7 AJ	252	/*
	253	* The watchdog is running, but invoke aspeed_wdt_start() to
	254	* write wdt->ctrl to WDT_CTRL to ensure the watchdog's
	255	* configuration conforms to the driver's expectations.
	256	* Primarily, ensure we're using the 1MHz clock source.
	257	*/
efa859f7 JS	258	aspeed_wdt_start(&wdt->wdd);
	259	set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
	260	}
	261
012c0460 AJ	262	if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) {
	263	u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
	264
	265	reg &= config->ext_pulse_width_mask;
	266	if (of_property_read_bool(np, "aspeed,ext-push-pull"))
	267	reg \|= WDT_PUSH_PULL_MAGIC;
	268	else
	269	reg \|= WDT_OPEN_DRAIN_MAGIC;
	270
	271	writel(reg, wdt->base + WDT_RESET_WIDTH);
	272
	273	reg &= config->ext_pulse_width_mask;
	274	if (of_property_read_bool(np, "aspeed,ext-active-high"))
	275	reg \|= WDT_ACTIVE_HIGH_MAGIC;
	276	else
	277	reg \|= WDT_ACTIVE_LOW_MAGIC;
	278
	279	writel(reg, wdt->base + WDT_RESET_WIDTH);
	280	}
	281
	282	if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
	283	u32 max_duration = config->ext_pulse_width_mask + 1;
	284
	285	if (duration == 0 \|\| duration > max_duration) {
eda21ee9 GR	286	dev_err(dev, "Invalid pulse duration: %uus\n",
eda21ee9 GR	287	duration);
012c0460	288	duration = max(1U, min(max_duration, duration));
eda21ee9 GR	289	dev_info(dev, "Pulse duration set to %uus\n",
eda21ee9 GR	290	duration);
012c0460 AJ	291	}
	292
	293	/*
	294	* The watchdog is always configured with a 1MHz source, so
	295	* there is no need to scale the microsecond value. However we
	296	* need to offset it - from the datasheet:
	297	*
	298	* "This register decides the asserting duration of wdt_ext and
	299	* wdt_rstarm signal. The default value is 0xFF. It means the
	300	* default asserting duration of wdt_ext and wdt_rstarm is
	301	* 256us."
	302	*
	303	* This implies a value of 0 gives a 1us pulse.
	304	*/
	305	writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
	306	}
	307
49d4d277 EJ	308	status = readl(wdt->base + WDT_TIMEOUT_STATUS);
	309	if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY)
	310	wdt->wdd.bootstatus = WDIOF_CARDRESET;
	311
4ab05433	312	return devm_watchdog_register_device(dev, &wdt->wdd);
efa859f7 JS	313	}
	314
	315	static struct platform_driver aspeed_watchdog_driver = {
	316	.probe = aspeed_wdt_probe,
efa859f7 JS	317	.driver = {
	318	.name = KBUILD_MODNAME,
	319	.of_match_table = of_match_ptr(aspeed_wdt_of_table),
	320	},
	321	};
d4238aa4 AJ	322
	323	static int __init aspeed_wdt_init(void)
	324	{
	325	return platform_driver_register(&aspeed_watchdog_driver);
	326	}
	327	arch_initcall(aspeed_wdt_init);
	328
	329	static void __exit aspeed_wdt_exit(void)
	330	{
	331	platform_driver_unregister(&aspeed_watchdog_driver);
	332	}
	333	module_exit(aspeed_wdt_exit);
efa859f7 JS	334
	335	MODULE_DESCRIPTION("Aspeed Watchdog Driver");
	336	MODULE_LICENSE("GPL");