Commit | Line | Data |
---|---|---|
2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
d22b8ed9 MW |
2 | /* |
3 | * tsi148.h | |
4 | * | |
5 | * Support for the Tundra TSI148 VME Bridge chip | |
6 | * | |
7 | * Author: Tom Armistead | |
8 | * Updated and maintained by Ajit Prem | |
9 | * Copyright 2004 Motorola Inc. | |
d22b8ed9 MW |
10 | */ |
11 | ||
12 | #ifndef TSI148_H | |
13 | #define TSI148_H | |
14 | ||
15 | #ifndef PCI_VENDOR_ID_TUNDRA | |
16 | #define PCI_VENDOR_ID_TUNDRA 0x10e3 | |
17 | #endif | |
18 | ||
19 | #ifndef PCI_DEVICE_ID_TUNDRA_TSI148 | |
20 | #define PCI_DEVICE_ID_TUNDRA_TSI148 0x148 | |
21 | #endif | |
22 | ||
23 | /* | |
24 | * Define the number of each that the Tsi148 supports. | |
25 | */ | |
26 | #define TSI148_MAX_MASTER 8 /* Max Master Windows */ | |
27 | #define TSI148_MAX_SLAVE 8 /* Max Slave Windows */ | |
28 | #define TSI148_MAX_DMA 2 /* Max DMA Controllers */ | |
29 | #define TSI148_MAX_MAILBOX 4 /* Max Mail Box registers */ | |
30 | #define TSI148_MAX_SEMAPHORE 8 /* Max Semaphores */ | |
31 | ||
29848ac9 MW |
32 | /* Structure used to hold driver specific information */ |
33 | struct tsi148_driver { | |
e20cbcf1 | 34 | void __iomem *base; /* Base Address of device registers */ |
29848ac9 MW |
35 | wait_queue_head_t dma_queue[2]; |
36 | wait_queue_head_t iack_queue; | |
fa54b326 AS |
37 | void (*lm_callback[4])(void *); /* Called in interrupt handler */ |
38 | void *lm_data[4]; | |
29848ac9 MW |
39 | void *crcsr_kernel; |
40 | dma_addr_t crcsr_bus; | |
41 | struct vme_master_resource *flush_image; | |
42 | struct mutex vme_rmw; /* Only one RMW cycle at a time */ | |
43 | struct mutex vme_int; /* | |
44 | * Only one VME interrupt can be | |
45 | * generated at a time, provide locking | |
46 | */ | |
47 | }; | |
48 | ||
d22b8ed9 MW |
49 | /* |
50 | * Layout of a DMAC Linked-List Descriptor | |
51 | * | |
52 | * Note: This structure is accessed via the chip and therefore must be | |
53 | * correctly laid out - It must also be aligned on 64-bit boundaries. | |
54 | */ | |
55 | struct tsi148_dma_descriptor { | |
ac1a4f2c MW |
56 | __be32 dsau; /* Source Address */ |
57 | __be32 dsal; | |
58 | __be32 ddau; /* Destination Address */ | |
59 | __be32 ddal; | |
60 | __be32 dsat; /* Source attributes */ | |
61 | __be32 ddat; /* Destination attributes */ | |
62 | __be32 dnlau; /* Next link address */ | |
63 | __be32 dnlal; | |
64 | __be32 dcnt; /* Byte count */ | |
65 | __be32 ddbs; /* 2eSST Broadcast select */ | |
d22b8ed9 MW |
66 | }; |
67 | ||
68 | struct tsi148_dma_entry { | |
69 | /* | |
70 | * The descriptor needs to be aligned on a 64-bit boundary, we increase | |
71 | * the chance of this by putting it first in the structure. | |
72 | */ | |
73 | struct tsi148_dma_descriptor descriptor; | |
74 | struct list_head list; | |
3abc48ae | 75 | dma_addr_t dma_handle; |
d22b8ed9 MW |
76 | }; |
77 | ||
78 | /* | |
79 | * TSI148 ASIC register structure overlays and bit field definitions. | |
80 | * | |
81 | * Note: Tsi148 Register Group (CRG) consists of the following | |
82 | * combination of registers: | |
83 | * PCFS - PCI Configuration Space Registers | |
84 | * LCSR - Local Control and Status Registers | |
85 | * GCSR - Global Control and Status Registers | |
86 | * CR/CSR - Subset of Configuration ROM / | |
87 | * Control and Status Registers | |
88 | */ | |
89 | ||
90 | ||
91 | /* | |
92 | * Command/Status Registers (CRG + $004) | |
93 | */ | |
94 | #define TSI148_PCFS_ID 0x0 | |
95 | #define TSI148_PCFS_CSR 0x4 | |
96 | #define TSI148_PCFS_CLASS 0x8 | |
97 | #define TSI148_PCFS_MISC0 0xC | |
98 | #define TSI148_PCFS_MBARL 0x10 | |
99 | #define TSI148_PCFS_MBARU 0x14 | |
100 | ||
101 | #define TSI148_PCFS_SUBID 0x28 | |
102 | ||
103 | #define TSI148_PCFS_CAPP 0x34 | |
104 | ||
105 | #define TSI148_PCFS_MISC1 0x3C | |
106 | ||
107 | #define TSI148_PCFS_XCAPP 0x40 | |
108 | #define TSI148_PCFS_XSTAT 0x44 | |
109 | ||
110 | /* | |
111 | * LCSR definitions | |
112 | */ | |
113 | ||
114 | /* | |
115 | * Outbound Translations | |
116 | */ | |
117 | #define TSI148_LCSR_OT0_OTSAU 0x100 | |
118 | #define TSI148_LCSR_OT0_OTSAL 0x104 | |
119 | #define TSI148_LCSR_OT0_OTEAU 0x108 | |
120 | #define TSI148_LCSR_OT0_OTEAL 0x10C | |
121 | #define TSI148_LCSR_OT0_OTOFU 0x110 | |
122 | #define TSI148_LCSR_OT0_OTOFL 0x114 | |
123 | #define TSI148_LCSR_OT0_OTBS 0x118 | |
124 | #define TSI148_LCSR_OT0_OTAT 0x11C | |
125 | ||
126 | #define TSI148_LCSR_OT1_OTSAU 0x120 | |
127 | #define TSI148_LCSR_OT1_OTSAL 0x124 | |
128 | #define TSI148_LCSR_OT1_OTEAU 0x128 | |
129 | #define TSI148_LCSR_OT1_OTEAL 0x12C | |
130 | #define TSI148_LCSR_OT1_OTOFU 0x130 | |
131 | #define TSI148_LCSR_OT1_OTOFL 0x134 | |
132 | #define TSI148_LCSR_OT1_OTBS 0x138 | |
133 | #define TSI148_LCSR_OT1_OTAT 0x13C | |
134 | ||
135 | #define TSI148_LCSR_OT2_OTSAU 0x140 | |
136 | #define TSI148_LCSR_OT2_OTSAL 0x144 | |
137 | #define TSI148_LCSR_OT2_OTEAU 0x148 | |
138 | #define TSI148_LCSR_OT2_OTEAL 0x14C | |
139 | #define TSI148_LCSR_OT2_OTOFU 0x150 | |
140 | #define TSI148_LCSR_OT2_OTOFL 0x154 | |
141 | #define TSI148_LCSR_OT2_OTBS 0x158 | |
142 | #define TSI148_LCSR_OT2_OTAT 0x15C | |
143 | ||
144 | #define TSI148_LCSR_OT3_OTSAU 0x160 | |
145 | #define TSI148_LCSR_OT3_OTSAL 0x164 | |
146 | #define TSI148_LCSR_OT3_OTEAU 0x168 | |
147 | #define TSI148_LCSR_OT3_OTEAL 0x16C | |
148 | #define TSI148_LCSR_OT3_OTOFU 0x170 | |
149 | #define TSI148_LCSR_OT3_OTOFL 0x174 | |
150 | #define TSI148_LCSR_OT3_OTBS 0x178 | |
151 | #define TSI148_LCSR_OT3_OTAT 0x17C | |
152 | ||
153 | #define TSI148_LCSR_OT4_OTSAU 0x180 | |
154 | #define TSI148_LCSR_OT4_OTSAL 0x184 | |
155 | #define TSI148_LCSR_OT4_OTEAU 0x188 | |
156 | #define TSI148_LCSR_OT4_OTEAL 0x18C | |
157 | #define TSI148_LCSR_OT4_OTOFU 0x190 | |
158 | #define TSI148_LCSR_OT4_OTOFL 0x194 | |
159 | #define TSI148_LCSR_OT4_OTBS 0x198 | |
160 | #define TSI148_LCSR_OT4_OTAT 0x19C | |
161 | ||
162 | #define TSI148_LCSR_OT5_OTSAU 0x1A0 | |
163 | #define TSI148_LCSR_OT5_OTSAL 0x1A4 | |
164 | #define TSI148_LCSR_OT5_OTEAU 0x1A8 | |
165 | #define TSI148_LCSR_OT5_OTEAL 0x1AC | |
166 | #define TSI148_LCSR_OT5_OTOFU 0x1B0 | |
167 | #define TSI148_LCSR_OT5_OTOFL 0x1B4 | |
168 | #define TSI148_LCSR_OT5_OTBS 0x1B8 | |
169 | #define TSI148_LCSR_OT5_OTAT 0x1BC | |
170 | ||
171 | #define TSI148_LCSR_OT6_OTSAU 0x1C0 | |
172 | #define TSI148_LCSR_OT6_OTSAL 0x1C4 | |
173 | #define TSI148_LCSR_OT6_OTEAU 0x1C8 | |
174 | #define TSI148_LCSR_OT6_OTEAL 0x1CC | |
175 | #define TSI148_LCSR_OT6_OTOFU 0x1D0 | |
176 | #define TSI148_LCSR_OT6_OTOFL 0x1D4 | |
177 | #define TSI148_LCSR_OT6_OTBS 0x1D8 | |
178 | #define TSI148_LCSR_OT6_OTAT 0x1DC | |
179 | ||
180 | #define TSI148_LCSR_OT7_OTSAU 0x1E0 | |
181 | #define TSI148_LCSR_OT7_OTSAL 0x1E4 | |
182 | #define TSI148_LCSR_OT7_OTEAU 0x1E8 | |
183 | #define TSI148_LCSR_OT7_OTEAL 0x1EC | |
184 | #define TSI148_LCSR_OT7_OTOFU 0x1F0 | |
185 | #define TSI148_LCSR_OT7_OTOFL 0x1F4 | |
186 | #define TSI148_LCSR_OT7_OTBS 0x1F8 | |
187 | #define TSI148_LCSR_OT7_OTAT 0x1FC | |
188 | ||
189 | #define TSI148_LCSR_OT0 0x100 | |
190 | #define TSI148_LCSR_OT1 0x120 | |
191 | #define TSI148_LCSR_OT2 0x140 | |
192 | #define TSI148_LCSR_OT3 0x160 | |
193 | #define TSI148_LCSR_OT4 0x180 | |
194 | #define TSI148_LCSR_OT5 0x1A0 | |
195 | #define TSI148_LCSR_OT6 0x1C0 | |
196 | #define TSI148_LCSR_OT7 0x1E0 | |
197 | ||
198 | static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1, | |
199 | TSI148_LCSR_OT2, TSI148_LCSR_OT3, | |
200 | TSI148_LCSR_OT4, TSI148_LCSR_OT5, | |
201 | TSI148_LCSR_OT6, TSI148_LCSR_OT7 }; | |
202 | ||
203 | #define TSI148_LCSR_OFFSET_OTSAU 0x0 | |
204 | #define TSI148_LCSR_OFFSET_OTSAL 0x4 | |
205 | #define TSI148_LCSR_OFFSET_OTEAU 0x8 | |
206 | #define TSI148_LCSR_OFFSET_OTEAL 0xC | |
207 | #define TSI148_LCSR_OFFSET_OTOFU 0x10 | |
208 | #define TSI148_LCSR_OFFSET_OTOFL 0x14 | |
209 | #define TSI148_LCSR_OFFSET_OTBS 0x18 | |
210 | #define TSI148_LCSR_OFFSET_OTAT 0x1C | |
211 | ||
212 | /* | |
25985edc | 213 | * VMEbus interrupt ack |
d22b8ed9 MW |
214 | * offset 200 |
215 | */ | |
216 | #define TSI148_LCSR_VIACK1 0x204 | |
217 | #define TSI148_LCSR_VIACK2 0x208 | |
218 | #define TSI148_LCSR_VIACK3 0x20C | |
219 | #define TSI148_LCSR_VIACK4 0x210 | |
220 | #define TSI148_LCSR_VIACK5 0x214 | |
221 | #define TSI148_LCSR_VIACK6 0x218 | |
222 | #define TSI148_LCSR_VIACK7 0x21C | |
223 | ||
224 | static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1, | |
225 | TSI148_LCSR_VIACK2, TSI148_LCSR_VIACK3, | |
226 | TSI148_LCSR_VIACK4, TSI148_LCSR_VIACK5, | |
227 | TSI148_LCSR_VIACK6, TSI148_LCSR_VIACK7 }; | |
228 | ||
229 | /* | |
230 | * RMW | |
231 | * offset 220 | |
232 | */ | |
233 | #define TSI148_LCSR_RMWAU 0x220 | |
234 | #define TSI148_LCSR_RMWAL 0x224 | |
235 | #define TSI148_LCSR_RMWEN 0x228 | |
236 | #define TSI148_LCSR_RMWC 0x22C | |
237 | #define TSI148_LCSR_RMWS 0x230 | |
238 | ||
239 | /* | |
240 | * VMEbus control | |
241 | * offset 234 | |
242 | */ | |
243 | #define TSI148_LCSR_VMCTRL 0x234 | |
244 | #define TSI148_LCSR_VCTRL 0x238 | |
245 | #define TSI148_LCSR_VSTAT 0x23C | |
246 | ||
247 | /* | |
248 | * PCI status | |
249 | * offset 240 | |
250 | */ | |
251 | #define TSI148_LCSR_PSTAT 0x240 | |
252 | ||
253 | /* | |
254 | * VME filter. | |
255 | * offset 250 | |
256 | */ | |
257 | #define TSI148_LCSR_VMEFL 0x250 | |
258 | ||
259 | /* | |
260 | * VME exception. | |
261 | * offset 260 | |
262 | */ | |
263 | #define TSI148_LCSR_VEAU 0x260 | |
264 | #define TSI148_LCSR_VEAL 0x264 | |
265 | #define TSI148_LCSR_VEAT 0x268 | |
266 | ||
267 | /* | |
268 | * PCI error | |
269 | * offset 270 | |
270 | */ | |
271 | #define TSI148_LCSR_EDPAU 0x270 | |
272 | #define TSI148_LCSR_EDPAL 0x274 | |
273 | #define TSI148_LCSR_EDPXA 0x278 | |
274 | #define TSI148_LCSR_EDPXS 0x27C | |
275 | #define TSI148_LCSR_EDPAT 0x280 | |
276 | ||
277 | /* | |
278 | * Inbound Translations | |
279 | * offset 300 | |
280 | */ | |
281 | #define TSI148_LCSR_IT0_ITSAU 0x300 | |
282 | #define TSI148_LCSR_IT0_ITSAL 0x304 | |
283 | #define TSI148_LCSR_IT0_ITEAU 0x308 | |
284 | #define TSI148_LCSR_IT0_ITEAL 0x30C | |
285 | #define TSI148_LCSR_IT0_ITOFU 0x310 | |
286 | #define TSI148_LCSR_IT0_ITOFL 0x314 | |
287 | #define TSI148_LCSR_IT0_ITAT 0x318 | |
288 | ||
289 | #define TSI148_LCSR_IT1_ITSAU 0x320 | |
290 | #define TSI148_LCSR_IT1_ITSAL 0x324 | |
291 | #define TSI148_LCSR_IT1_ITEAU 0x328 | |
292 | #define TSI148_LCSR_IT1_ITEAL 0x32C | |
293 | #define TSI148_LCSR_IT1_ITOFU 0x330 | |
294 | #define TSI148_LCSR_IT1_ITOFL 0x334 | |
295 | #define TSI148_LCSR_IT1_ITAT 0x338 | |
296 | ||
297 | #define TSI148_LCSR_IT2_ITSAU 0x340 | |
298 | #define TSI148_LCSR_IT2_ITSAL 0x344 | |
299 | #define TSI148_LCSR_IT2_ITEAU 0x348 | |
300 | #define TSI148_LCSR_IT2_ITEAL 0x34C | |
301 | #define TSI148_LCSR_IT2_ITOFU 0x350 | |
302 | #define TSI148_LCSR_IT2_ITOFL 0x354 | |
303 | #define TSI148_LCSR_IT2_ITAT 0x358 | |
304 | ||
305 | #define TSI148_LCSR_IT3_ITSAU 0x360 | |
306 | #define TSI148_LCSR_IT3_ITSAL 0x364 | |
307 | #define TSI148_LCSR_IT3_ITEAU 0x368 | |
308 | #define TSI148_LCSR_IT3_ITEAL 0x36C | |
309 | #define TSI148_LCSR_IT3_ITOFU 0x370 | |
310 | #define TSI148_LCSR_IT3_ITOFL 0x374 | |
311 | #define TSI148_LCSR_IT3_ITAT 0x378 | |
312 | ||
313 | #define TSI148_LCSR_IT4_ITSAU 0x380 | |
314 | #define TSI148_LCSR_IT4_ITSAL 0x384 | |
315 | #define TSI148_LCSR_IT4_ITEAU 0x388 | |
316 | #define TSI148_LCSR_IT4_ITEAL 0x38C | |
317 | #define TSI148_LCSR_IT4_ITOFU 0x390 | |
318 | #define TSI148_LCSR_IT4_ITOFL 0x394 | |
319 | #define TSI148_LCSR_IT4_ITAT 0x398 | |
320 | ||
321 | #define TSI148_LCSR_IT5_ITSAU 0x3A0 | |
322 | #define TSI148_LCSR_IT5_ITSAL 0x3A4 | |
323 | #define TSI148_LCSR_IT5_ITEAU 0x3A8 | |
324 | #define TSI148_LCSR_IT5_ITEAL 0x3AC | |
325 | #define TSI148_LCSR_IT5_ITOFU 0x3B0 | |
326 | #define TSI148_LCSR_IT5_ITOFL 0x3B4 | |
327 | #define TSI148_LCSR_IT5_ITAT 0x3B8 | |
328 | ||
329 | #define TSI148_LCSR_IT6_ITSAU 0x3C0 | |
330 | #define TSI148_LCSR_IT6_ITSAL 0x3C4 | |
331 | #define TSI148_LCSR_IT6_ITEAU 0x3C8 | |
332 | #define TSI148_LCSR_IT6_ITEAL 0x3CC | |
333 | #define TSI148_LCSR_IT6_ITOFU 0x3D0 | |
334 | #define TSI148_LCSR_IT6_ITOFL 0x3D4 | |
335 | #define TSI148_LCSR_IT6_ITAT 0x3D8 | |
336 | ||
337 | #define TSI148_LCSR_IT7_ITSAU 0x3E0 | |
338 | #define TSI148_LCSR_IT7_ITSAL 0x3E4 | |
339 | #define TSI148_LCSR_IT7_ITEAU 0x3E8 | |
340 | #define TSI148_LCSR_IT7_ITEAL 0x3EC | |
341 | #define TSI148_LCSR_IT7_ITOFU 0x3F0 | |
342 | #define TSI148_LCSR_IT7_ITOFL 0x3F4 | |
343 | #define TSI148_LCSR_IT7_ITAT 0x3F8 | |
344 | ||
345 | ||
346 | #define TSI148_LCSR_IT0 0x300 | |
347 | #define TSI148_LCSR_IT1 0x320 | |
348 | #define TSI148_LCSR_IT2 0x340 | |
349 | #define TSI148_LCSR_IT3 0x360 | |
350 | #define TSI148_LCSR_IT4 0x380 | |
351 | #define TSI148_LCSR_IT5 0x3A0 | |
352 | #define TSI148_LCSR_IT6 0x3C0 | |
353 | #define TSI148_LCSR_IT7 0x3E0 | |
354 | ||
355 | static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1, | |
356 | TSI148_LCSR_IT2, TSI148_LCSR_IT3, | |
357 | TSI148_LCSR_IT4, TSI148_LCSR_IT5, | |
358 | TSI148_LCSR_IT6, TSI148_LCSR_IT7 }; | |
359 | ||
360 | #define TSI148_LCSR_OFFSET_ITSAU 0x0 | |
361 | #define TSI148_LCSR_OFFSET_ITSAL 0x4 | |
362 | #define TSI148_LCSR_OFFSET_ITEAU 0x8 | |
363 | #define TSI148_LCSR_OFFSET_ITEAL 0xC | |
364 | #define TSI148_LCSR_OFFSET_ITOFU 0x10 | |
365 | #define TSI148_LCSR_OFFSET_ITOFL 0x14 | |
366 | #define TSI148_LCSR_OFFSET_ITAT 0x18 | |
367 | ||
368 | /* | |
369 | * Inbound Translation GCSR | |
370 | * offset 400 | |
371 | */ | |
372 | #define TSI148_LCSR_GBAU 0x400 | |
373 | #define TSI148_LCSR_GBAL 0x404 | |
374 | #define TSI148_LCSR_GCSRAT 0x408 | |
375 | ||
376 | /* | |
377 | * Inbound Translation CRG | |
378 | * offset 40C | |
379 | */ | |
380 | #define TSI148_LCSR_CBAU 0x40C | |
381 | #define TSI148_LCSR_CBAL 0x410 | |
382 | #define TSI148_LCSR_CSRAT 0x414 | |
383 | ||
384 | /* | |
385 | * Inbound Translation CR/CSR | |
386 | * CRG | |
387 | * offset 418 | |
388 | */ | |
389 | #define TSI148_LCSR_CROU 0x418 | |
390 | #define TSI148_LCSR_CROL 0x41C | |
391 | #define TSI148_LCSR_CRAT 0x420 | |
392 | ||
393 | /* | |
394 | * Inbound Translation Location Monitor | |
395 | * offset 424 | |
396 | */ | |
397 | #define TSI148_LCSR_LMBAU 0x424 | |
398 | #define TSI148_LCSR_LMBAL 0x428 | |
399 | #define TSI148_LCSR_LMAT 0x42C | |
400 | ||
401 | /* | |
402 | * VMEbus Interrupt Control. | |
403 | * offset 430 | |
404 | */ | |
405 | #define TSI148_LCSR_BCU 0x430 | |
406 | #define TSI148_LCSR_BCL 0x434 | |
407 | #define TSI148_LCSR_BPGTR 0x438 | |
408 | #define TSI148_LCSR_BPCTR 0x43C | |
409 | #define TSI148_LCSR_VICR 0x440 | |
410 | ||
411 | /* | |
412 | * Local Bus Interrupt Control. | |
413 | * offset 448 | |
414 | */ | |
415 | #define TSI148_LCSR_INTEN 0x448 | |
416 | #define TSI148_LCSR_INTEO 0x44C | |
417 | #define TSI148_LCSR_INTS 0x450 | |
418 | #define TSI148_LCSR_INTC 0x454 | |
419 | #define TSI148_LCSR_INTM1 0x458 | |
420 | #define TSI148_LCSR_INTM2 0x45C | |
421 | ||
422 | /* | |
423 | * DMA Controllers | |
424 | * offset 500 | |
425 | */ | |
426 | #define TSI148_LCSR_DCTL0 0x500 | |
427 | #define TSI148_LCSR_DSTA0 0x504 | |
428 | #define TSI148_LCSR_DCSAU0 0x508 | |
429 | #define TSI148_LCSR_DCSAL0 0x50C | |
430 | #define TSI148_LCSR_DCDAU0 0x510 | |
431 | #define TSI148_LCSR_DCDAL0 0x514 | |
432 | #define TSI148_LCSR_DCLAU0 0x518 | |
433 | #define TSI148_LCSR_DCLAL0 0x51C | |
434 | #define TSI148_LCSR_DSAU0 0x520 | |
435 | #define TSI148_LCSR_DSAL0 0x524 | |
436 | #define TSI148_LCSR_DDAU0 0x528 | |
437 | #define TSI148_LCSR_DDAL0 0x52C | |
438 | #define TSI148_LCSR_DSAT0 0x530 | |
439 | #define TSI148_LCSR_DDAT0 0x534 | |
440 | #define TSI148_LCSR_DNLAU0 0x538 | |
441 | #define TSI148_LCSR_DNLAL0 0x53C | |
442 | #define TSI148_LCSR_DCNT0 0x540 | |
443 | #define TSI148_LCSR_DDBS0 0x544 | |
444 | ||
445 | #define TSI148_LCSR_DCTL1 0x580 | |
446 | #define TSI148_LCSR_DSTA1 0x584 | |
447 | #define TSI148_LCSR_DCSAU1 0x588 | |
448 | #define TSI148_LCSR_DCSAL1 0x58C | |
449 | #define TSI148_LCSR_DCDAU1 0x590 | |
450 | #define TSI148_LCSR_DCDAL1 0x594 | |
451 | #define TSI148_LCSR_DCLAU1 0x598 | |
452 | #define TSI148_LCSR_DCLAL1 0x59C | |
453 | #define TSI148_LCSR_DSAU1 0x5A0 | |
454 | #define TSI148_LCSR_DSAL1 0x5A4 | |
455 | #define TSI148_LCSR_DDAU1 0x5A8 | |
456 | #define TSI148_LCSR_DDAL1 0x5AC | |
457 | #define TSI148_LCSR_DSAT1 0x5B0 | |
458 | #define TSI148_LCSR_DDAT1 0x5B4 | |
459 | #define TSI148_LCSR_DNLAU1 0x5B8 | |
460 | #define TSI148_LCSR_DNLAL1 0x5BC | |
461 | #define TSI148_LCSR_DCNT1 0x5C0 | |
462 | #define TSI148_LCSR_DDBS1 0x5C4 | |
463 | ||
464 | #define TSI148_LCSR_DMA0 0x500 | |
465 | #define TSI148_LCSR_DMA1 0x580 | |
466 | ||
467 | ||
468 | static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0, | |
469 | TSI148_LCSR_DMA1 }; | |
470 | ||
471 | #define TSI148_LCSR_OFFSET_DCTL 0x0 | |
472 | #define TSI148_LCSR_OFFSET_DSTA 0x4 | |
473 | #define TSI148_LCSR_OFFSET_DCSAU 0x8 | |
474 | #define TSI148_LCSR_OFFSET_DCSAL 0xC | |
475 | #define TSI148_LCSR_OFFSET_DCDAU 0x10 | |
476 | #define TSI148_LCSR_OFFSET_DCDAL 0x14 | |
477 | #define TSI148_LCSR_OFFSET_DCLAU 0x18 | |
478 | #define TSI148_LCSR_OFFSET_DCLAL 0x1C | |
479 | #define TSI148_LCSR_OFFSET_DSAU 0x20 | |
480 | #define TSI148_LCSR_OFFSET_DSAL 0x24 | |
481 | #define TSI148_LCSR_OFFSET_DDAU 0x28 | |
482 | #define TSI148_LCSR_OFFSET_DDAL 0x2C | |
483 | #define TSI148_LCSR_OFFSET_DSAT 0x30 | |
484 | #define TSI148_LCSR_OFFSET_DDAT 0x34 | |
485 | #define TSI148_LCSR_OFFSET_DNLAU 0x38 | |
486 | #define TSI148_LCSR_OFFSET_DNLAL 0x3C | |
487 | #define TSI148_LCSR_OFFSET_DCNT 0x40 | |
488 | #define TSI148_LCSR_OFFSET_DDBS 0x44 | |
489 | ||
490 | /* | |
491 | * GCSR Register Group | |
492 | */ | |
493 | ||
494 | /* | |
495 | * GCSR CRG | |
496 | * offset 00 600 - DEVI/VENI | |
497 | * offset 04 604 - CTRL/GA/REVID | |
498 | * offset 08 608 - Semaphore3/2/1/0 | |
499 | * offset 0C 60C - Seamphore7/6/5/4 | |
500 | */ | |
501 | #define TSI148_GCSR_ID 0x600 | |
502 | #define TSI148_GCSR_CSR 0x604 | |
503 | #define TSI148_GCSR_SEMA0 0x608 | |
504 | #define TSI148_GCSR_SEMA1 0x60C | |
505 | ||
506 | /* | |
507 | * Mail Box | |
508 | * GCSR CRG | |
509 | * offset 10 610 - Mailbox0 | |
510 | */ | |
511 | #define TSI148_GCSR_MBOX0 0x610 | |
512 | #define TSI148_GCSR_MBOX1 0x614 | |
513 | #define TSI148_GCSR_MBOX2 0x618 | |
514 | #define TSI148_GCSR_MBOX3 0x61C | |
515 | ||
516 | static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0, | |
517 | TSI148_GCSR_MBOX1, | |
518 | TSI148_GCSR_MBOX2, | |
519 | TSI148_GCSR_MBOX3 }; | |
520 | ||
521 | /* | |
522 | * CR/CSR | |
523 | */ | |
524 | ||
525 | /* | |
526 | * CR/CSR CRG | |
527 | * offset 7FFF4 FF4 - CSRBCR | |
528 | * offset 7FFF8 FF8 - CSRBSR | |
529 | * offset 7FFFC FFC - CBAR | |
530 | */ | |
531 | #define TSI148_CSRBCR 0xFF4 | |
532 | #define TSI148_CSRBSR 0xFF8 | |
533 | #define TSI148_CBAR 0xFFC | |
534 | ||
535 | ||
536 | ||
537 | ||
538 | /* | |
539 | * TSI148 Register Bit Definitions | |
540 | */ | |
541 | ||
542 | /* | |
543 | * PFCS Register Set | |
544 | */ | |
545 | #define TSI148_PCFS_CMMD_SERR (1<<8) /* SERR_L out pin ssys err */ | |
546 | #define TSI148_PCFS_CMMD_PERR (1<<6) /* PERR_L out pin parity */ | |
547 | #define TSI148_PCFS_CMMD_MSTR (1<<2) /* PCI bus master */ | |
548 | #define TSI148_PCFS_CMMD_MEMSP (1<<1) /* PCI mem space access */ | |
549 | #define TSI148_PCFS_CMMD_IOSP (1<<0) /* PCI I/O space enable */ | |
550 | ||
551 | #define TSI148_PCFS_STAT_RCPVE (1<<15) /* Detected Parity Error */ | |
552 | #define TSI148_PCFS_STAT_SIGSE (1<<14) /* Signalled System Error */ | |
553 | #define TSI148_PCFS_STAT_RCVMA (1<<13) /* Received Master Abort */ | |
554 | #define TSI148_PCFS_STAT_RCVTA (1<<12) /* Received Target Abort */ | |
555 | #define TSI148_PCFS_STAT_SIGTA (1<<11) /* Signalled Target Abort */ | |
556 | #define TSI148_PCFS_STAT_SELTIM (3<<9) /* DELSEL Timing */ | |
557 | #define TSI148_PCFS_STAT_DPAR (1<<8) /* Data Parity Err Reported */ | |
558 | #define TSI148_PCFS_STAT_FAST (1<<7) /* Fast back-to-back Cap */ | |
559 | #define TSI148_PCFS_STAT_P66M (1<<5) /* 66 MHz Capable */ | |
560 | #define TSI148_PCFS_STAT_CAPL (1<<4) /* Capab List - address $34 */ | |
561 | ||
562 | /* | |
563 | * Revision ID/Class Code Registers (CRG +$008) | |
564 | */ | |
565 | #define TSI148_PCFS_CLAS_M (0xFF<<24) /* Class ID */ | |
566 | #define TSI148_PCFS_SUBCLAS_M (0xFF<<16) /* Sub-Class ID */ | |
567 | #define TSI148_PCFS_PROGIF_M (0xFF<<8) /* Sub-Class ID */ | |
568 | #define TSI148_PCFS_REVID_M (0xFF<<0) /* Rev ID */ | |
569 | ||
570 | /* | |
571 | * Cache Line Size/ Master Latency Timer/ Header Type Registers (CRG + $00C) | |
572 | */ | |
573 | #define TSI148_PCFS_HEAD_M (0xFF<<16) /* Master Lat Timer */ | |
574 | #define TSI148_PCFS_MLAT_M (0xFF<<8) /* Master Lat Timer */ | |
575 | #define TSI148_PCFS_CLSZ_M (0xFF<<0) /* Cache Line Size */ | |
576 | ||
577 | /* | |
578 | * Memory Base Address Lower Reg (CRG + $010) | |
579 | */ | |
7946328f | 580 | #define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF<<12) /* Base Addr Lower Mask */ |
d22b8ed9 MW |
581 | #define TSI148_PCFS_MBARL_PRE (1<<3) /* Prefetch */ |
582 | #define TSI148_PCFS_MBARL_MTYPE_M (3<<1) /* Memory Type Mask */ | |
583 | #define TSI148_PCFS_MBARL_IOMEM (1<<0) /* I/O Space Indicator */ | |
584 | ||
585 | /* | |
586 | * Message Signaled Interrupt Capabilities Register (CRG + $040) | |
587 | */ | |
588 | #define TSI148_PCFS_MSICAP_64BAC (1<<7) /* 64-bit Address Capable */ | |
589 | #define TSI148_PCFS_MSICAP_MME_M (7<<4) /* Multiple Msg Enable Mask */ | |
590 | #define TSI148_PCFS_MSICAP_MMC_M (7<<1) /* Multiple Msg Capable Mask */ | |
591 | #define TSI148_PCFS_MSICAP_MSIEN (1<<0) /* Msg signaled INT Enable */ | |
592 | ||
593 | /* | |
594 | * Message Address Lower Register (CRG +$044) | |
595 | */ | |
596 | #define TSI148_PCFS_MSIAL_M (0x3FFFFFFF<<2) /* Mask */ | |
597 | ||
598 | /* | |
599 | * Message Data Register (CRG + 4C) | |
600 | */ | |
601 | #define TSI148_PCFS_MSIMD_M (0xFFFF<<0) /* Mask */ | |
602 | ||
603 | /* | |
604 | * PCI-X Capabilities Register (CRG + $050) | |
605 | */ | |
606 | #define TSI148_PCFS_PCIXCAP_MOST_M (7<<4) /* Max outstanding Split Tran */ | |
607 | #define TSI148_PCFS_PCIXCAP_MMRBC_M (3<<2) /* Max Mem Read byte cnt */ | |
608 | #define TSI148_PCFS_PCIXCAP_ERO (1<<1) /* Enable Relaxed Ordering */ | |
609 | #define TSI148_PCFS_PCIXCAP_DPERE (1<<0) /* Data Parity Recover Enable */ | |
610 | ||
611 | /* | |
612 | * PCI-X Status Register (CRG +$054) | |
613 | */ | |
25985edc | 614 | #define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29) /* Received Split Comp Error */ |
d22b8ed9 | 615 | #define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */ |
7946328f MW |
616 | #define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans |
617 | */ | |
d22b8ed9 MW |
618 | #define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */ |
619 | #define TSI148_PCFS_PCIXSTAT_DC (1<<20) /* Device Complexity */ | |
620 | #define TSI148_PCFS_PCIXSTAT_USC (1<<19) /* Unexpected Split comp */ | |
621 | #define TSI148_PCFS_PCIXSTAT_SCD (1<<18) /* Split completion discard */ | |
622 | #define TSI148_PCFS_PCIXSTAT_133C (1<<17) /* 133MHz capable */ | |
623 | #define TSI148_PCFS_PCIXSTAT_64D (1<<16) /* 64 bit device */ | |
624 | #define TSI148_PCFS_PCIXSTAT_BN_M (0xFF<<8) /* Bus number */ | |
625 | #define TSI148_PCFS_PCIXSTAT_DN_M (0x1F<<3) /* Device number */ | |
626 | #define TSI148_PCFS_PCIXSTAT_FN_M (7<<0) /* Function Number */ | |
627 | ||
628 | /* | |
629 | * LCSR Registers | |
630 | */ | |
631 | ||
632 | /* | |
633 | * Outbound Translation Starting Address Lower | |
634 | */ | |
635 | #define TSI148_LCSR_OTSAL_M (0xFFFF<<16) /* Mask */ | |
636 | ||
637 | /* | |
638 | * Outbound Translation Ending Address Lower | |
639 | */ | |
640 | #define TSI148_LCSR_OTEAL_M (0xFFFF<<16) /* Mask */ | |
641 | ||
642 | /* | |
643 | * Outbound Translation Offset Lower | |
644 | */ | |
645 | #define TSI148_LCSR_OTOFFL_M (0xFFFF<<16) /* Mask */ | |
646 | ||
647 | /* | |
648 | * Outbound Translation 2eSST Broadcast Select | |
649 | */ | |
650 | #define TSI148_LCSR_OTBS_M (0xFFFFF<<0) /* Mask */ | |
651 | ||
652 | /* | |
653 | * Outbound Translation Attribute | |
654 | */ | |
655 | #define TSI148_LCSR_OTAT_EN (1<<31) /* Window Enable */ | |
656 | #define TSI148_LCSR_OTAT_MRPFD (1<<18) /* Prefetch Disable */ | |
657 | ||
658 | #define TSI148_LCSR_OTAT_PFS_M (3<<16) /* Prefetch Size Mask */ | |
659 | #define TSI148_LCSR_OTAT_PFS_2 (0<<16) /* 2 Cache Lines P Size */ | |
660 | #define TSI148_LCSR_OTAT_PFS_4 (1<<16) /* 4 Cache Lines P Size */ | |
661 | #define TSI148_LCSR_OTAT_PFS_8 (2<<16) /* 8 Cache Lines P Size */ | |
662 | #define TSI148_LCSR_OTAT_PFS_16 (3<<16) /* 16 Cache Lines P Size */ | |
663 | ||
664 | #define TSI148_LCSR_OTAT_2eSSTM_M (7<<11) /* 2eSST Xfer Rate Mask */ | |
665 | #define TSI148_LCSR_OTAT_2eSSTM_160 (0<<11) /* 160MB/s 2eSST Xfer Rate */ | |
666 | #define TSI148_LCSR_OTAT_2eSSTM_267 (1<<11) /* 267MB/s 2eSST Xfer Rate */ | |
667 | #define TSI148_LCSR_OTAT_2eSSTM_320 (2<<11) /* 320MB/s 2eSST Xfer Rate */ | |
668 | ||
669 | #define TSI148_LCSR_OTAT_TM_M (7<<8) /* Xfer Protocol Mask */ | |
670 | #define TSI148_LCSR_OTAT_TM_SCT (0<<8) /* SCT Xfer Protocol */ | |
671 | #define TSI148_LCSR_OTAT_TM_BLT (1<<8) /* BLT Xfer Protocol */ | |
672 | #define TSI148_LCSR_OTAT_TM_MBLT (2<<8) /* MBLT Xfer Protocol */ | |
673 | #define TSI148_LCSR_OTAT_TM_2eVME (3<<8) /* 2eVME Xfer Protocol */ | |
674 | #define TSI148_LCSR_OTAT_TM_2eSST (4<<8) /* 2eSST Xfer Protocol */ | |
675 | #define TSI148_LCSR_OTAT_TM_2eSSTB (5<<8) /* 2eSST Bcast Xfer Protocol */ | |
676 | ||
677 | #define TSI148_LCSR_OTAT_DBW_M (3<<6) /* Max Data Width */ | |
678 | #define TSI148_LCSR_OTAT_DBW_16 (0<<6) /* 16-bit Data Width */ | |
679 | #define TSI148_LCSR_OTAT_DBW_32 (1<<6) /* 32-bit Data Width */ | |
680 | ||
681 | #define TSI148_LCSR_OTAT_SUP (1<<5) /* Supervisory Access */ | |
682 | #define TSI148_LCSR_OTAT_PGM (1<<4) /* Program Access */ | |
683 | ||
684 | #define TSI148_LCSR_OTAT_AMODE_M (0xf<<0) /* Address Mode Mask */ | |
685 | #define TSI148_LCSR_OTAT_AMODE_A16 (0<<0) /* A16 Address Space */ | |
686 | #define TSI148_LCSR_OTAT_AMODE_A24 (1<<0) /* A24 Address Space */ | |
687 | #define TSI148_LCSR_OTAT_AMODE_A32 (2<<0) /* A32 Address Space */ | |
688 | #define TSI148_LCSR_OTAT_AMODE_A64 (4<<0) /* A32 Address Space */ | |
689 | #define TSI148_LCSR_OTAT_AMODE_CRCSR (5<<0) /* CR/CSR Address Space */ | |
690 | #define TSI148_LCSR_OTAT_AMODE_USER1 (8<<0) /* User1 Address Space */ | |
691 | #define TSI148_LCSR_OTAT_AMODE_USER2 (9<<0) /* User2 Address Space */ | |
692 | #define TSI148_LCSR_OTAT_AMODE_USER3 (10<<0) /* User3 Address Space */ | |
693 | #define TSI148_LCSR_OTAT_AMODE_USER4 (11<<0) /* User4 Address Space */ | |
694 | ||
695 | /* | |
696 | * VME Master Control Register CRG+$234 | |
697 | */ | |
698 | #define TSI148_LCSR_VMCTRL_VSA (1<<27) /* VMEbus Stop Ack */ | |
699 | #define TSI148_LCSR_VMCTRL_VS (1<<26) /* VMEbus Stop */ | |
700 | #define TSI148_LCSR_VMCTRL_DHB (1<<25) /* Device Has Bus */ | |
701 | #define TSI148_LCSR_VMCTRL_DWB (1<<24) /* Device Wants Bus */ | |
702 | ||
703 | #define TSI148_LCSR_VMCTRL_RMWEN (1<<20) /* RMW Enable */ | |
704 | ||
7946328f MW |
705 | #define TSI148_LCSR_VMCTRL_ATO_M (7<<16) /* Master Access Time-out Mask |
706 | */ | |
d22b8ed9 MW |
707 | #define TSI148_LCSR_VMCTRL_ATO_32 (0<<16) /* 32 us */ |
708 | #define TSI148_LCSR_VMCTRL_ATO_128 (1<<16) /* 128 us */ | |
709 | #define TSI148_LCSR_VMCTRL_ATO_512 (2<<16) /* 512 us */ | |
710 | #define TSI148_LCSR_VMCTRL_ATO_2M (3<<16) /* 2 ms */ | |
711 | #define TSI148_LCSR_VMCTRL_ATO_8M (4<<16) /* 8 ms */ | |
712 | #define TSI148_LCSR_VMCTRL_ATO_32M (5<<16) /* 32 ms */ | |
713 | #define TSI148_LCSR_VMCTRL_ATO_128M (6<<16) /* 128 ms */ | |
714 | #define TSI148_LCSR_VMCTRL_ATO_DIS (7<<16) /* Disabled */ | |
715 | ||
716 | #define TSI148_LCSR_VMCTRL_VTOFF_M (7<<12) /* VMEbus Master Time off */ | |
717 | #define TSI148_LCSR_VMCTRL_VTOFF_0 (0<<12) /* 0us */ | |
718 | #define TSI148_LCSR_VMCTRL_VTOFF_1 (1<<12) /* 1us */ | |
719 | #define TSI148_LCSR_VMCTRL_VTOFF_2 (2<<12) /* 2us */ | |
720 | #define TSI148_LCSR_VMCTRL_VTOFF_4 (3<<12) /* 4us */ | |
721 | #define TSI148_LCSR_VMCTRL_VTOFF_8 (4<<12) /* 8us */ | |
722 | #define TSI148_LCSR_VMCTRL_VTOFF_16 (5<<12) /* 16us */ | |
723 | #define TSI148_LCSR_VMCTRL_VTOFF_32 (6<<12) /* 32us */ | |
724 | #define TSI148_LCSR_VMCTRL_VTOFF_64 (7<<12) /* 64us */ | |
725 | ||
726 | #define TSI148_LCSR_VMCTRL_VTON_M (7<<8) /* VMEbus Master Time On */ | |
727 | #define TSI148_LCSR_VMCTRL_VTON_4 (0<<8) /* 8us */ | |
728 | #define TSI148_LCSR_VMCTRL_VTON_8 (1<<8) /* 8us */ | |
729 | #define TSI148_LCSR_VMCTRL_VTON_16 (2<<8) /* 16us */ | |
730 | #define TSI148_LCSR_VMCTRL_VTON_32 (3<<8) /* 32us */ | |
731 | #define TSI148_LCSR_VMCTRL_VTON_64 (4<<8) /* 64us */ | |
732 | #define TSI148_LCSR_VMCTRL_VTON_128 (5<<8) /* 128us */ | |
733 | #define TSI148_LCSR_VMCTRL_VTON_256 (6<<8) /* 256us */ | |
734 | #define TSI148_LCSR_VMCTRL_VTON_512 (7<<8) /* 512us */ | |
735 | ||
7946328f MW |
736 | #define TSI148_LCSR_VMCTRL_VREL_M (3<<3) /* VMEbus Master Rel Mode Mask |
737 | */ | |
d22b8ed9 MW |
738 | #define TSI148_LCSR_VMCTRL_VREL_T_D (0<<3) /* Time on or Done */ |
739 | #define TSI148_LCSR_VMCTRL_VREL_T_R_D (1<<3) /* Time on and REQ or Done */ | |
740 | #define TSI148_LCSR_VMCTRL_VREL_T_B_D (2<<3) /* Time on and BCLR or Done */ | |
741 | #define TSI148_LCSR_VMCTRL_VREL_T_D_R (3<<3) /* Time on or Done and REQ */ | |
742 | ||
743 | #define TSI148_LCSR_VMCTRL_VFAIR (1<<2) /* VMEbus Master Fair Mode */ | |
7946328f MW |
744 | #define TSI148_LCSR_VMCTRL_VREQL_M (3<<0) /* VMEbus Master Req Level Mask |
745 | */ | |
d22b8ed9 MW |
746 | |
747 | /* | |
748 | * VMEbus Control Register CRG+$238 | |
749 | */ | |
750 | #define TSI148_LCSR_VCTRL_LRE (1<<31) /* Late Retry Enable */ | |
751 | ||
752 | #define TSI148_LCSR_VCTRL_DLT_M (0xF<<24) /* Deadlock Timer */ | |
753 | #define TSI148_LCSR_VCTRL_DLT_OFF (0<<24) /* Deadlock Timer Off */ | |
754 | #define TSI148_LCSR_VCTRL_DLT_16 (1<<24) /* 16 VCLKS */ | |
755 | #define TSI148_LCSR_VCTRL_DLT_32 (2<<24) /* 32 VCLKS */ | |
756 | #define TSI148_LCSR_VCTRL_DLT_64 (3<<24) /* 64 VCLKS */ | |
757 | #define TSI148_LCSR_VCTRL_DLT_128 (4<<24) /* 128 VCLKS */ | |
758 | #define TSI148_LCSR_VCTRL_DLT_256 (5<<24) /* 256 VCLKS */ | |
759 | #define TSI148_LCSR_VCTRL_DLT_512 (6<<24) /* 512 VCLKS */ | |
760 | #define TSI148_LCSR_VCTRL_DLT_1024 (7<<24) /* 1024 VCLKS */ | |
761 | #define TSI148_LCSR_VCTRL_DLT_2048 (8<<24) /* 2048 VCLKS */ | |
762 | #define TSI148_LCSR_VCTRL_DLT_4096 (9<<24) /* 4096 VCLKS */ | |
763 | #define TSI148_LCSR_VCTRL_DLT_8192 (0xA<<24) /* 8192 VCLKS */ | |
764 | #define TSI148_LCSR_VCTRL_DLT_16384 (0xB<<24) /* 16384 VCLKS */ | |
765 | #define TSI148_LCSR_VCTRL_DLT_32768 (0xC<<24) /* 32768 VCLKS */ | |
766 | ||
7946328f MW |
767 | #define TSI148_LCSR_VCTRL_NERBB (1<<20) /* No Early Release of Bus Busy |
768 | */ | |
d22b8ed9 MW |
769 | |
770 | #define TSI148_LCSR_VCTRL_SRESET (1<<17) /* System Reset */ | |
771 | #define TSI148_LCSR_VCTRL_LRESET (1<<16) /* Local Reset */ | |
772 | ||
773 | #define TSI148_LCSR_VCTRL_SFAILAI (1<<15) /* SYSFAIL Auto Slot ID */ | |
774 | #define TSI148_LCSR_VCTRL_BID_M (0x1F<<8) /* Broadcast ID Mask */ | |
775 | ||
776 | #define TSI148_LCSR_VCTRL_ATOEN (1<<7) /* Arbiter Time-out Enable */ | |
777 | #define TSI148_LCSR_VCTRL_ROBIN (1<<6) /* VMEbus Round Robin */ | |
778 | ||
7946328f MW |
779 | #define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask |
780 | */ | |
d22b8ed9 MW |
781 | #define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */ |
782 | #define TSI148_LCSR_VCTRL_GTO_16 (1<<0) /* 16 us */ | |
783 | #define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */ | |
784 | #define TSI148_LCSR_VCTRL_GTO_64 (3<<0) /* 64 us */ | |
785 | #define TSI148_LCSR_VCTRL_GTO_128 (4<<0) /* 128 us */ | |
786 | #define TSI148_LCSR_VCTRL_GTO_256 (5<<0) /* 256 us */ | |
787 | #define TSI148_LCSR_VCTRL_GTO_512 (6<<0) /* 512 us */ | |
788 | #define TSI148_LCSR_VCTRL_GTO_DIS (7<<0) /* Disabled */ | |
789 | ||
790 | /* | |
791 | * VMEbus Status Register CRG + $23C | |
792 | */ | |
793 | #define TSI148_LCSR_VSTAT_CPURST (1<<15) /* Clear power up reset */ | |
794 | #define TSI148_LCSR_VSTAT_BRDFL (1<<14) /* Board fail */ | |
795 | #define TSI148_LCSR_VSTAT_PURSTS (1<<12) /* Power up reset status */ | |
796 | #define TSI148_LCSR_VSTAT_BDFAILS (1<<11) /* Board Fail Status */ | |
797 | #define TSI148_LCSR_VSTAT_SYSFAILS (1<<10) /* System Fail Status */ | |
798 | #define TSI148_LCSR_VSTAT_ACFAILS (1<<9) /* AC fail status */ | |
799 | #define TSI148_LCSR_VSTAT_SCONS (1<<8) /* System Cont Status */ | |
800 | #define TSI148_LCSR_VSTAT_GAP (1<<5) /* Geographic Addr Parity */ | |
7946328f | 801 | #define TSI148_LCSR_VSTAT_GA_M (0x1F<<0) /* Geographic Addr Mask */ |
d22b8ed9 MW |
802 | |
803 | /* | |
804 | * PCI Configuration Status Register CRG+$240 | |
805 | */ | |
806 | #define TSI148_LCSR_PSTAT_REQ64S (1<<6) /* Request 64 status set */ | |
807 | #define TSI148_LCSR_PSTAT_M66ENS (1<<5) /* M66ENS 66Mhz enable */ | |
808 | #define TSI148_LCSR_PSTAT_FRAMES (1<<4) /* Frame Status */ | |
809 | #define TSI148_LCSR_PSTAT_IRDYS (1<<3) /* IRDY status */ | |
810 | #define TSI148_LCSR_PSTAT_DEVSELS (1<<2) /* DEVL status */ | |
811 | #define TSI148_LCSR_PSTAT_STOPS (1<<1) /* STOP status */ | |
812 | #define TSI148_LCSR_PSTAT_TRDYS (1<<0) /* TRDY status */ | |
813 | ||
814 | /* | |
815 | * VMEbus Exception Attributes Register CRG + $268 | |
816 | */ | |
817 | #define TSI148_LCSR_VEAT_VES (1<<31) /* Status */ | |
818 | #define TSI148_LCSR_VEAT_VEOF (1<<30) /* Overflow */ | |
819 | #define TSI148_LCSR_VEAT_VESCL (1<<29) /* Status Clear */ | |
820 | #define TSI148_LCSR_VEAT_2EOT (1<<21) /* 2e Odd Termination */ | |
821 | #define TSI148_LCSR_VEAT_2EST (1<<20) /* 2e Slave terminated */ | |
822 | #define TSI148_LCSR_VEAT_BERR (1<<19) /* Bus Error */ | |
823 | #define TSI148_LCSR_VEAT_LWORD (1<<18) /* LWORD_ signal state */ | |
824 | #define TSI148_LCSR_VEAT_WRITE (1<<17) /* WRITE_ signal state */ | |
825 | #define TSI148_LCSR_VEAT_IACK (1<<16) /* IACK_ signal state */ | |
826 | #define TSI148_LCSR_VEAT_DS1 (1<<15) /* DS1_ signal state */ | |
827 | #define TSI148_LCSR_VEAT_DS0 (1<<14) /* DS0_ signal state */ | |
828 | #define TSI148_LCSR_VEAT_AM_M (0x3F<<8) /* Address Mode Mask */ | |
829 | #define TSI148_LCSR_VEAT_XAM_M (0xFF<<0) /* Master AMode Mask */ | |
830 | ||
831 | ||
832 | /* | |
833 | * VMEbus PCI Error Diagnostics PCI/X Attributes Register CRG + $280 | |
834 | */ | |
835 | #define TSI148_LCSR_EDPAT_EDPCL (1<<29) | |
836 | ||
837 | /* | |
838 | * Inbound Translation Starting Address Lower | |
839 | */ | |
840 | #define TSI148_LCSR_ITSAL6432_M (0xFFFF<<16) /* Mask */ | |
841 | #define TSI148_LCSR_ITSAL24_M (0x00FFF<<12) /* Mask */ | |
842 | #define TSI148_LCSR_ITSAL16_M (0x0000FFF<<4) /* Mask */ | |
843 | ||
844 | /* | |
845 | * Inbound Translation Ending Address Lower | |
846 | */ | |
847 | #define TSI148_LCSR_ITEAL6432_M (0xFFFF<<16) /* Mask */ | |
848 | #define TSI148_LCSR_ITEAL24_M (0x00FFF<<12) /* Mask */ | |
849 | #define TSI148_LCSR_ITEAL16_M (0x0000FFF<<4) /* Mask */ | |
850 | ||
851 | /* | |
852 | * Inbound Translation Offset Lower | |
853 | */ | |
854 | #define TSI148_LCSR_ITOFFL6432_M (0xFFFF<<16) /* Mask */ | |
855 | #define TSI148_LCSR_ITOFFL24_M (0xFFFFF<<12) /* Mask */ | |
856 | #define TSI148_LCSR_ITOFFL16_M (0xFFFFFFF<<4) /* Mask */ | |
857 | ||
858 | /* | |
859 | * Inbound Translation Attribute | |
860 | */ | |
861 | #define TSI148_LCSR_ITAT_EN (1<<31) /* Window Enable */ | |
862 | #define TSI148_LCSR_ITAT_TH (1<<18) /* Prefetch Threshold */ | |
863 | ||
864 | #define TSI148_LCSR_ITAT_VFS_M (3<<16) /* Virtual FIFO Size Mask */ | |
865 | #define TSI148_LCSR_ITAT_VFS_64 (0<<16) /* 64 bytes Virtual FIFO Size */ | |
866 | #define TSI148_LCSR_ITAT_VFS_128 (1<<16) /* 128 bytes Virtual FIFO Sz */ | |
867 | #define TSI148_LCSR_ITAT_VFS_256 (2<<16) /* 256 bytes Virtual FIFO Sz */ | |
868 | #define TSI148_LCSR_ITAT_VFS_512 (3<<16) /* 512 bytes Virtual FIFO Sz */ | |
869 | ||
870 | #define TSI148_LCSR_ITAT_2eSSTM_M (7<<12) /* 2eSST Xfer Rate Mask */ | |
871 | #define TSI148_LCSR_ITAT_2eSSTM_160 (0<<12) /* 160MB/s 2eSST Xfer Rate */ | |
872 | #define TSI148_LCSR_ITAT_2eSSTM_267 (1<<12) /* 267MB/s 2eSST Xfer Rate */ | |
873 | #define TSI148_LCSR_ITAT_2eSSTM_320 (2<<12) /* 320MB/s 2eSST Xfer Rate */ | |
874 | ||
875 | #define TSI148_LCSR_ITAT_2eSSTB (1<<11) /* 2eSST Bcast Xfer Protocol */ | |
876 | #define TSI148_LCSR_ITAT_2eSST (1<<10) /* 2eSST Xfer Protocol */ | |
877 | #define TSI148_LCSR_ITAT_2eVME (1<<9) /* 2eVME Xfer Protocol */ | |
878 | #define TSI148_LCSR_ITAT_MBLT (1<<8) /* MBLT Xfer Protocol */ | |
879 | #define TSI148_LCSR_ITAT_BLT (1<<7) /* BLT Xfer Protocol */ | |
880 | ||
881 | #define TSI148_LCSR_ITAT_AS_M (7<<4) /* Address Space Mask */ | |
882 | #define TSI148_LCSR_ITAT_AS_A16 (0<<4) /* A16 Address Space */ | |
883 | #define TSI148_LCSR_ITAT_AS_A24 (1<<4) /* A24 Address Space */ | |
884 | #define TSI148_LCSR_ITAT_AS_A32 (2<<4) /* A32 Address Space */ | |
885 | #define TSI148_LCSR_ITAT_AS_A64 (4<<4) /* A64 Address Space */ | |
886 | ||
887 | #define TSI148_LCSR_ITAT_SUPR (1<<3) /* Supervisor Access */ | |
888 | #define TSI148_LCSR_ITAT_NPRIV (1<<2) /* Non-Priv (User) Access */ | |
889 | #define TSI148_LCSR_ITAT_PGM (1<<1) /* Program Access */ | |
890 | #define TSI148_LCSR_ITAT_DATA (1<<0) /* Data Access */ | |
891 | ||
892 | /* | |
893 | * GCSR Base Address Lower Address CRG +$404 | |
894 | */ | |
895 | #define TSI148_LCSR_GBAL_M (0x7FFFFFF<<5) /* Mask */ | |
896 | ||
897 | /* | |
898 | * GCSR Attribute Register CRG + $408 | |
899 | */ | |
900 | #define TSI148_LCSR_GCSRAT_EN (1<<7) /* Enable access to GCSR */ | |
901 | ||
902 | #define TSI148_LCSR_GCSRAT_AS_M (7<<4) /* Address Space Mask */ | |
903 | #define TSI148_LCSR_GCSRAT_AS_A16 (0<<4) /* Address Space 16 */ | |
904 | #define TSI148_LCSR_GCSRAT_AS_A24 (1<<4) /* Address Space 24 */ | |
905 | #define TSI148_LCSR_GCSRAT_AS_A32 (2<<4) /* Address Space 32 */ | |
906 | #define TSI148_LCSR_GCSRAT_AS_A64 (4<<4) /* Address Space 64 */ | |
907 | ||
908 | #define TSI148_LCSR_GCSRAT_SUPR (1<<3) /* Sup set -GCSR decoder */ | |
909 | #define TSI148_LCSR_GCSRAT_NPRIV (1<<2) /* Non-Privliged set - CGSR */ | |
910 | #define TSI148_LCSR_GCSRAT_PGM (1<<1) /* Program set - GCSR decoder */ | |
911 | #define TSI148_LCSR_GCSRAT_DATA (1<<0) /* DATA set GCSR decoder */ | |
912 | ||
913 | /* | |
914 | * CRG Base Address Lower Address CRG + $410 | |
915 | */ | |
916 | #define TSI148_LCSR_CBAL_M (0xFFFFF<<12) | |
917 | ||
918 | /* | |
919 | * CRG Attribute Register CRG + $414 | |
920 | */ | |
921 | #define TSI148_LCSR_CRGAT_EN (1<<7) /* Enable PRG Access */ | |
922 | ||
923 | #define TSI148_LCSR_CRGAT_AS_M (7<<4) /* Address Space */ | |
924 | #define TSI148_LCSR_CRGAT_AS_A16 (0<<4) /* Address Space 16 */ | |
925 | #define TSI148_LCSR_CRGAT_AS_A24 (1<<4) /* Address Space 24 */ | |
926 | #define TSI148_LCSR_CRGAT_AS_A32 (2<<4) /* Address Space 32 */ | |
927 | #define TSI148_LCSR_CRGAT_AS_A64 (4<<4) /* Address Space 64 */ | |
928 | ||
929 | #define TSI148_LCSR_CRGAT_SUPR (1<<3) /* Supervisor Access */ | |
930 | #define TSI148_LCSR_CRGAT_NPRIV (1<<2) /* Non-Privliged(User) Access */ | |
931 | #define TSI148_LCSR_CRGAT_PGM (1<<1) /* Program Access */ | |
932 | #define TSI148_LCSR_CRGAT_DATA (1<<0) /* Data Access */ | |
933 | ||
934 | /* | |
935 | * CR/CSR Offset Lower Register CRG + $41C | |
936 | */ | |
937 | #define TSI148_LCSR_CROL_M (0x1FFF<<19) /* Mask */ | |
938 | ||
939 | /* | |
940 | * CR/CSR Attribute register CRG + $420 | |
941 | */ | |
942 | #define TSI148_LCSR_CRAT_EN (1<<7) /* Enable access to CR/CSR */ | |
943 | ||
944 | /* | |
945 | * Location Monitor base address lower register CRG + $428 | |
946 | */ | |
947 | #define TSI148_LCSR_LMBAL_M (0x7FFFFFF<<5) /* Mask */ | |
948 | ||
949 | /* | |
950 | * Location Monitor Attribute Register CRG + $42C | |
951 | */ | |
952 | #define TSI148_LCSR_LMAT_EN (1<<7) /* Enable Location Monitor */ | |
953 | ||
954 | #define TSI148_LCSR_LMAT_AS_M (7<<4) /* Address Space MASK */ | |
955 | #define TSI148_LCSR_LMAT_AS_A16 (0<<4) /* A16 */ | |
956 | #define TSI148_LCSR_LMAT_AS_A24 (1<<4) /* A24 */ | |
957 | #define TSI148_LCSR_LMAT_AS_A32 (2<<4) /* A32 */ | |
958 | #define TSI148_LCSR_LMAT_AS_A64 (4<<4) /* A64 */ | |
959 | ||
960 | #define TSI148_LCSR_LMAT_SUPR (1<<3) /* Supervisor Access */ | |
961 | #define TSI148_LCSR_LMAT_NPRIV (1<<2) /* Non-Priv (User) Access */ | |
962 | #define TSI148_LCSR_LMAT_PGM (1<<1) /* Program Access */ | |
963 | #define TSI148_LCSR_LMAT_DATA (1<<0) /* Data Access */ | |
964 | ||
965 | /* | |
966 | * Broadcast Pulse Generator Timer Register CRG + $438 | |
967 | */ | |
968 | #define TSI148_LCSR_BPGTR_BPGT_M (0xFFFF<<0) /* Mask */ | |
969 | ||
970 | /* | |
971 | * Broadcast Programmable Clock Timer Register CRG + $43C | |
972 | */ | |
973 | #define TSI148_LCSR_BPCTR_BPCT_M (0xFFFFFF<<0) /* Mask */ | |
974 | ||
975 | /* | |
976 | * VMEbus Interrupt Control Register CRG + $43C | |
977 | */ | |
978 | #define TSI148_LCSR_VICR_CNTS_M (3<<22) /* Cntr Source MASK */ | |
979 | #define TSI148_LCSR_VICR_CNTS_DIS (1<<22) /* Cntr Disable */ | |
980 | #define TSI148_LCSR_VICR_CNTS_IRQ1 (2<<22) /* IRQ1 to Cntr */ | |
981 | #define TSI148_LCSR_VICR_CNTS_IRQ2 (3<<22) /* IRQ2 to Cntr */ | |
982 | ||
25985edc LDM |
983 | #define TSI148_LCSR_VICR_EDGIS_M (3<<20) /* Edge interrupt MASK */ |
984 | #define TSI148_LCSR_VICR_EDGIS_DIS (1<<20) /* Edge interrupt Disable */ | |
d22b8ed9 MW |
985 | #define TSI148_LCSR_VICR_EDGIS_IRQ1 (2<<20) /* IRQ1 to Edge */ |
986 | #define TSI148_LCSR_VICR_EDGIS_IRQ2 (3<<20) /* IRQ2 to Edge */ | |
987 | ||
988 | #define TSI148_LCSR_VICR_IRQIF_M (3<<18) /* IRQ1* Function MASK */ | |
989 | #define TSI148_LCSR_VICR_IRQIF_NORM (1<<18) /* Normal */ | |
990 | #define TSI148_LCSR_VICR_IRQIF_PULSE (2<<18) /* Pulse Generator */ | |
991 | #define TSI148_LCSR_VICR_IRQIF_PROG (3<<18) /* Programmable Clock */ | |
992 | #define TSI148_LCSR_VICR_IRQIF_1U (4<<18) /* 1us Clock */ | |
993 | ||
994 | #define TSI148_LCSR_VICR_IRQ2F_M (3<<16) /* IRQ2* Function MASK */ | |
995 | #define TSI148_LCSR_VICR_IRQ2F_NORM (1<<16) /* Normal */ | |
996 | #define TSI148_LCSR_VICR_IRQ2F_PULSE (2<<16) /* Pulse Generator */ | |
997 | #define TSI148_LCSR_VICR_IRQ2F_PROG (3<<16) /* Programmable Clock */ | |
998 | #define TSI148_LCSR_VICR_IRQ2F_1U (4<<16) /* 1us Clock */ | |
999 | ||
1000 | #define TSI148_LCSR_VICR_BIP (1<<15) /* Broadcast Interrupt Pulse */ | |
1001 | ||
1002 | #define TSI148_LCSR_VICR_IRQC (1<<12) /* VMEbus IRQ Clear */ | |
1003 | #define TSI148_LCSR_VICR_IRQS (1<<11) /* VMEbus IRQ Status */ | |
1004 | ||
1005 | #define TSI148_LCSR_VICR_IRQL_M (7<<8) /* VMEbus SW IRQ Level Mask */ | |
1006 | #define TSI148_LCSR_VICR_IRQL_1 (1<<8) /* VMEbus SW IRQ Level 1 */ | |
1007 | #define TSI148_LCSR_VICR_IRQL_2 (2<<8) /* VMEbus SW IRQ Level 2 */ | |
1008 | #define TSI148_LCSR_VICR_IRQL_3 (3<<8) /* VMEbus SW IRQ Level 3 */ | |
1009 | #define TSI148_LCSR_VICR_IRQL_4 (4<<8) /* VMEbus SW IRQ Level 4 */ | |
1010 | #define TSI148_LCSR_VICR_IRQL_5 (5<<8) /* VMEbus SW IRQ Level 5 */ | |
1011 | #define TSI148_LCSR_VICR_IRQL_6 (6<<8) /* VMEbus SW IRQ Level 6 */ | |
1012 | #define TSI148_LCSR_VICR_IRQL_7 (7<<8) /* VMEbus SW IRQ Level 7 */ | |
1013 | ||
1014 | static const int TSI148_LCSR_VICR_IRQL[8] = { 0, TSI148_LCSR_VICR_IRQL_1, | |
1015 | TSI148_LCSR_VICR_IRQL_2, TSI148_LCSR_VICR_IRQL_3, | |
1016 | TSI148_LCSR_VICR_IRQL_4, TSI148_LCSR_VICR_IRQL_5, | |
1017 | TSI148_LCSR_VICR_IRQL_6, TSI148_LCSR_VICR_IRQL_7 }; | |
1018 | ||
1019 | #define TSI148_LCSR_VICR_STID_M (0xFF<<0) /* Status/ID Mask */ | |
1020 | ||
1021 | /* | |
1022 | * Interrupt Enable Register CRG + $440 | |
1023 | */ | |
1024 | #define TSI148_LCSR_INTEN_DMA1EN (1<<25) /* DMAC 1 */ | |
1025 | #define TSI148_LCSR_INTEN_DMA0EN (1<<24) /* DMAC 0 */ | |
1026 | #define TSI148_LCSR_INTEN_LM3EN (1<<23) /* Location Monitor 3 */ | |
1027 | #define TSI148_LCSR_INTEN_LM2EN (1<<22) /* Location Monitor 2 */ | |
1028 | #define TSI148_LCSR_INTEN_LM1EN (1<<21) /* Location Monitor 1 */ | |
1029 | #define TSI148_LCSR_INTEN_LM0EN (1<<20) /* Location Monitor 0 */ | |
1030 | #define TSI148_LCSR_INTEN_MB3EN (1<<19) /* Mail Box 3 */ | |
1031 | #define TSI148_LCSR_INTEN_MB2EN (1<<18) /* Mail Box 2 */ | |
1032 | #define TSI148_LCSR_INTEN_MB1EN (1<<17) /* Mail Box 1 */ | |
1033 | #define TSI148_LCSR_INTEN_MB0EN (1<<16) /* Mail Box 0 */ | |
1034 | #define TSI148_LCSR_INTEN_PERREN (1<<13) /* PCI/X Error */ | |
1035 | #define TSI148_LCSR_INTEN_VERREN (1<<12) /* VMEbus Error */ | |
1036 | #define TSI148_LCSR_INTEN_VIEEN (1<<11) /* VMEbus IRQ Edge */ | |
1037 | #define TSI148_LCSR_INTEN_IACKEN (1<<10) /* IACK */ | |
1038 | #define TSI148_LCSR_INTEN_SYSFLEN (1<<9) /* System Fail */ | |
1039 | #define TSI148_LCSR_INTEN_ACFLEN (1<<8) /* AC Fail */ | |
1040 | #define TSI148_LCSR_INTEN_IRQ7EN (1<<7) /* IRQ7 */ | |
1041 | #define TSI148_LCSR_INTEN_IRQ6EN (1<<6) /* IRQ6 */ | |
1042 | #define TSI148_LCSR_INTEN_IRQ5EN (1<<5) /* IRQ5 */ | |
1043 | #define TSI148_LCSR_INTEN_IRQ4EN (1<<4) /* IRQ4 */ | |
1044 | #define TSI148_LCSR_INTEN_IRQ3EN (1<<3) /* IRQ3 */ | |
1045 | #define TSI148_LCSR_INTEN_IRQ2EN (1<<2) /* IRQ2 */ | |
1046 | #define TSI148_LCSR_INTEN_IRQ1EN (1<<1) /* IRQ1 */ | |
1047 | ||
1048 | static const int TSI148_LCSR_INTEN_LMEN[4] = { TSI148_LCSR_INTEN_LM0EN, | |
1049 | TSI148_LCSR_INTEN_LM1EN, | |
1050 | TSI148_LCSR_INTEN_LM2EN, | |
1051 | TSI148_LCSR_INTEN_LM3EN }; | |
1052 | ||
1053 | static const int TSI148_LCSR_INTEN_IRQEN[7] = { TSI148_LCSR_INTEN_IRQ1EN, | |
1054 | TSI148_LCSR_INTEN_IRQ2EN, | |
1055 | TSI148_LCSR_INTEN_IRQ3EN, | |
1056 | TSI148_LCSR_INTEN_IRQ4EN, | |
1057 | TSI148_LCSR_INTEN_IRQ5EN, | |
1058 | TSI148_LCSR_INTEN_IRQ6EN, | |
1059 | TSI148_LCSR_INTEN_IRQ7EN }; | |
1060 | ||
1061 | /* | |
1062 | * Interrupt Enable Out Register CRG + $444 | |
1063 | */ | |
1064 | #define TSI148_LCSR_INTEO_DMA1EO (1<<25) /* DMAC 1 */ | |
1065 | #define TSI148_LCSR_INTEO_DMA0EO (1<<24) /* DMAC 0 */ | |
1066 | #define TSI148_LCSR_INTEO_LM3EO (1<<23) /* Loc Monitor 3 */ | |
1067 | #define TSI148_LCSR_INTEO_LM2EO (1<<22) /* Loc Monitor 2 */ | |
1068 | #define TSI148_LCSR_INTEO_LM1EO (1<<21) /* Loc Monitor 1 */ | |
1069 | #define TSI148_LCSR_INTEO_LM0EO (1<<20) /* Location Monitor 0 */ | |
1070 | #define TSI148_LCSR_INTEO_MB3EO (1<<19) /* Mail Box 3 */ | |
1071 | #define TSI148_LCSR_INTEO_MB2EO (1<<18) /* Mail Box 2 */ | |
1072 | #define TSI148_LCSR_INTEO_MB1EO (1<<17) /* Mail Box 1 */ | |
1073 | #define TSI148_LCSR_INTEO_MB0EO (1<<16) /* Mail Box 0 */ | |
1074 | #define TSI148_LCSR_INTEO_PERREO (1<<13) /* PCI/X Error */ | |
1075 | #define TSI148_LCSR_INTEO_VERREO (1<<12) /* VMEbus Error */ | |
1076 | #define TSI148_LCSR_INTEO_VIEEO (1<<11) /* VMEbus IRQ Edge */ | |
1077 | #define TSI148_LCSR_INTEO_IACKEO (1<<10) /* IACK */ | |
1078 | #define TSI148_LCSR_INTEO_SYSFLEO (1<<9) /* System Fail */ | |
1079 | #define TSI148_LCSR_INTEO_ACFLEO (1<<8) /* AC Fail */ | |
1080 | #define TSI148_LCSR_INTEO_IRQ7EO (1<<7) /* IRQ7 */ | |
1081 | #define TSI148_LCSR_INTEO_IRQ6EO (1<<6) /* IRQ6 */ | |
1082 | #define TSI148_LCSR_INTEO_IRQ5EO (1<<5) /* IRQ5 */ | |
1083 | #define TSI148_LCSR_INTEO_IRQ4EO (1<<4) /* IRQ4 */ | |
1084 | #define TSI148_LCSR_INTEO_IRQ3EO (1<<3) /* IRQ3 */ | |
1085 | #define TSI148_LCSR_INTEO_IRQ2EO (1<<2) /* IRQ2 */ | |
1086 | #define TSI148_LCSR_INTEO_IRQ1EO (1<<1) /* IRQ1 */ | |
1087 | ||
1088 | static const int TSI148_LCSR_INTEO_LMEO[4] = { TSI148_LCSR_INTEO_LM0EO, | |
1089 | TSI148_LCSR_INTEO_LM1EO, | |
1090 | TSI148_LCSR_INTEO_LM2EO, | |
1091 | TSI148_LCSR_INTEO_LM3EO }; | |
1092 | ||
1093 | static const int TSI148_LCSR_INTEO_IRQEO[7] = { TSI148_LCSR_INTEO_IRQ1EO, | |
1094 | TSI148_LCSR_INTEO_IRQ2EO, | |
1095 | TSI148_LCSR_INTEO_IRQ3EO, | |
1096 | TSI148_LCSR_INTEO_IRQ4EO, | |
1097 | TSI148_LCSR_INTEO_IRQ5EO, | |
1098 | TSI148_LCSR_INTEO_IRQ6EO, | |
1099 | TSI148_LCSR_INTEO_IRQ7EO }; | |
1100 | ||
1101 | /* | |
1102 | * Interrupt Status Register CRG + $448 | |
1103 | */ | |
1104 | #define TSI148_LCSR_INTS_DMA1S (1<<25) /* DMA 1 */ | |
1105 | #define TSI148_LCSR_INTS_DMA0S (1<<24) /* DMA 0 */ | |
1106 | #define TSI148_LCSR_INTS_LM3S (1<<23) /* Location Monitor 3 */ | |
1107 | #define TSI148_LCSR_INTS_LM2S (1<<22) /* Location Monitor 2 */ | |
1108 | #define TSI148_LCSR_INTS_LM1S (1<<21) /* Location Monitor 1 */ | |
1109 | #define TSI148_LCSR_INTS_LM0S (1<<20) /* Location Monitor 0 */ | |
1110 | #define TSI148_LCSR_INTS_MB3S (1<<19) /* Mail Box 3 */ | |
1111 | #define TSI148_LCSR_INTS_MB2S (1<<18) /* Mail Box 2 */ | |
1112 | #define TSI148_LCSR_INTS_MB1S (1<<17) /* Mail Box 1 */ | |
1113 | #define TSI148_LCSR_INTS_MB0S (1<<16) /* Mail Box 0 */ | |
1114 | #define TSI148_LCSR_INTS_PERRS (1<<13) /* PCI/X Error */ | |
1115 | #define TSI148_LCSR_INTS_VERRS (1<<12) /* VMEbus Error */ | |
1116 | #define TSI148_LCSR_INTS_VIES (1<<11) /* VMEbus IRQ Edge */ | |
1117 | #define TSI148_LCSR_INTS_IACKS (1<<10) /* IACK */ | |
1118 | #define TSI148_LCSR_INTS_SYSFLS (1<<9) /* System Fail */ | |
1119 | #define TSI148_LCSR_INTS_ACFLS (1<<8) /* AC Fail */ | |
1120 | #define TSI148_LCSR_INTS_IRQ7S (1<<7) /* IRQ7 */ | |
1121 | #define TSI148_LCSR_INTS_IRQ6S (1<<6) /* IRQ6 */ | |
1122 | #define TSI148_LCSR_INTS_IRQ5S (1<<5) /* IRQ5 */ | |
1123 | #define TSI148_LCSR_INTS_IRQ4S (1<<4) /* IRQ4 */ | |
1124 | #define TSI148_LCSR_INTS_IRQ3S (1<<3) /* IRQ3 */ | |
1125 | #define TSI148_LCSR_INTS_IRQ2S (1<<2) /* IRQ2 */ | |
1126 | #define TSI148_LCSR_INTS_IRQ1S (1<<1) /* IRQ1 */ | |
1127 | ||
1128 | static const int TSI148_LCSR_INTS_LMS[4] = { TSI148_LCSR_INTS_LM0S, | |
1129 | TSI148_LCSR_INTS_LM1S, | |
1130 | TSI148_LCSR_INTS_LM2S, | |
1131 | TSI148_LCSR_INTS_LM3S }; | |
1132 | ||
1133 | static const int TSI148_LCSR_INTS_MBS[4] = { TSI148_LCSR_INTS_MB0S, | |
1134 | TSI148_LCSR_INTS_MB1S, | |
1135 | TSI148_LCSR_INTS_MB2S, | |
1136 | TSI148_LCSR_INTS_MB3S }; | |
1137 | ||
1138 | /* | |
1139 | * Interrupt Clear Register CRG + $44C | |
1140 | */ | |
1141 | #define TSI148_LCSR_INTC_DMA1C (1<<25) /* DMA 1 */ | |
1142 | #define TSI148_LCSR_INTC_DMA0C (1<<24) /* DMA 0 */ | |
1143 | #define TSI148_LCSR_INTC_LM3C (1<<23) /* Location Monitor 3 */ | |
1144 | #define TSI148_LCSR_INTC_LM2C (1<<22) /* Location Monitor 2 */ | |
1145 | #define TSI148_LCSR_INTC_LM1C (1<<21) /* Location Monitor 1 */ | |
1146 | #define TSI148_LCSR_INTC_LM0C (1<<20) /* Location Monitor 0 */ | |
1147 | #define TSI148_LCSR_INTC_MB3C (1<<19) /* Mail Box 3 */ | |
1148 | #define TSI148_LCSR_INTC_MB2C (1<<18) /* Mail Box 2 */ | |
1149 | #define TSI148_LCSR_INTC_MB1C (1<<17) /* Mail Box 1 */ | |
1150 | #define TSI148_LCSR_INTC_MB0C (1<<16) /* Mail Box 0 */ | |
1151 | #define TSI148_LCSR_INTC_PERRC (1<<13) /* VMEbus Error */ | |
1152 | #define TSI148_LCSR_INTC_VERRC (1<<12) /* VMEbus Access Time-out */ | |
1153 | #define TSI148_LCSR_INTC_VIEC (1<<11) /* VMEbus IRQ Edge */ | |
1154 | #define TSI148_LCSR_INTC_IACKC (1<<10) /* IACK */ | |
1155 | #define TSI148_LCSR_INTC_SYSFLC (1<<9) /* System Fail */ | |
1156 | #define TSI148_LCSR_INTC_ACFLC (1<<8) /* AC Fail */ | |
1157 | ||
1158 | static const int TSI148_LCSR_INTC_LMC[4] = { TSI148_LCSR_INTC_LM0C, | |
1159 | TSI148_LCSR_INTC_LM1C, | |
1160 | TSI148_LCSR_INTC_LM2C, | |
1161 | TSI148_LCSR_INTC_LM3C }; | |
1162 | ||
1163 | static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C, | |
1164 | TSI148_LCSR_INTC_MB1C, | |
1165 | TSI148_LCSR_INTC_MB2C, | |
1166 | TSI148_LCSR_INTC_MB3C }; | |
1167 | ||
1168 | /* | |
1169 | * Interrupt Map Register 1 CRG + $458 | |
1170 | */ | |
1171 | #define TSI148_LCSR_INTM1_DMA1M_M (3<<18) /* DMA 1 */ | |
1172 | #define TSI148_LCSR_INTM1_DMA0M_M (3<<16) /* DMA 0 */ | |
1173 | #define TSI148_LCSR_INTM1_LM3M_M (3<<14) /* Location Monitor 3 */ | |
1174 | #define TSI148_LCSR_INTM1_LM2M_M (3<<12) /* Location Monitor 2 */ | |
1175 | #define TSI148_LCSR_INTM1_LM1M_M (3<<10) /* Location Monitor 1 */ | |
1176 | #define TSI148_LCSR_INTM1_LM0M_M (3<<8) /* Location Monitor 0 */ | |
1177 | #define TSI148_LCSR_INTM1_MB3M_M (3<<6) /* Mail Box 3 */ | |
1178 | #define TSI148_LCSR_INTM1_MB2M_M (3<<4) /* Mail Box 2 */ | |
1179 | #define TSI148_LCSR_INTM1_MB1M_M (3<<2) /* Mail Box 1 */ | |
1180 | #define TSI148_LCSR_INTM1_MB0M_M (3<<0) /* Mail Box 0 */ | |
1181 | ||
1182 | /* | |
1183 | * Interrupt Map Register 2 CRG + $45C | |
1184 | */ | |
1185 | #define TSI148_LCSR_INTM2_PERRM_M (3<<26) /* PCI Bus Error */ | |
1186 | #define TSI148_LCSR_INTM2_VERRM_M (3<<24) /* VMEbus Error */ | |
1187 | #define TSI148_LCSR_INTM2_VIEM_M (3<<22) /* VMEbus IRQ Edge */ | |
1188 | #define TSI148_LCSR_INTM2_IACKM_M (3<<20) /* IACK */ | |
1189 | #define TSI148_LCSR_INTM2_SYSFLM_M (3<<18) /* System Fail */ | |
1190 | #define TSI148_LCSR_INTM2_ACFLM_M (3<<16) /* AC Fail */ | |
1191 | #define TSI148_LCSR_INTM2_IRQ7M_M (3<<14) /* IRQ7 */ | |
1192 | #define TSI148_LCSR_INTM2_IRQ6M_M (3<<12) /* IRQ6 */ | |
1193 | #define TSI148_LCSR_INTM2_IRQ5M_M (3<<10) /* IRQ5 */ | |
1194 | #define TSI148_LCSR_INTM2_IRQ4M_M (3<<8) /* IRQ4 */ | |
1195 | #define TSI148_LCSR_INTM2_IRQ3M_M (3<<6) /* IRQ3 */ | |
1196 | #define TSI148_LCSR_INTM2_IRQ2M_M (3<<4) /* IRQ2 */ | |
1197 | #define TSI148_LCSR_INTM2_IRQ1M_M (3<<2) /* IRQ1 */ | |
1198 | ||
1199 | /* | |
1200 | * DMA Control (0-1) Registers CRG + $500 | |
1201 | */ | |
1202 | #define TSI148_LCSR_DCTL_ABT (1<<27) /* Abort */ | |
1203 | #define TSI148_LCSR_DCTL_PAU (1<<26) /* Pause */ | |
1204 | #define TSI148_LCSR_DCTL_DGO (1<<25) /* DMA Go */ | |
1205 | ||
1206 | #define TSI148_LCSR_DCTL_MOD (1<<23) /* Mode */ | |
1207 | ||
1208 | #define TSI148_LCSR_DCTL_VBKS_M (7<<12) /* VMEbus block Size MASK */ | |
1209 | #define TSI148_LCSR_DCTL_VBKS_32 (0<<12) /* VMEbus block Size 32 */ | |
1210 | #define TSI148_LCSR_DCTL_VBKS_64 (1<<12) /* VMEbus block Size 64 */ | |
1211 | #define TSI148_LCSR_DCTL_VBKS_128 (2<<12) /* VMEbus block Size 128 */ | |
1212 | #define TSI148_LCSR_DCTL_VBKS_256 (3<<12) /* VMEbus block Size 256 */ | |
1213 | #define TSI148_LCSR_DCTL_VBKS_512 (4<<12) /* VMEbus block Size 512 */ | |
1214 | #define TSI148_LCSR_DCTL_VBKS_1024 (5<<12) /* VMEbus block Size 1024 */ | |
1215 | #define TSI148_LCSR_DCTL_VBKS_2048 (6<<12) /* VMEbus block Size 2048 */ | |
1216 | #define TSI148_LCSR_DCTL_VBKS_4096 (7<<12) /* VMEbus block Size 4096 */ | |
1217 | ||
1218 | #define TSI148_LCSR_DCTL_VBOT_M (7<<8) /* VMEbus back-off MASK */ | |
1219 | #define TSI148_LCSR_DCTL_VBOT_0 (0<<8) /* VMEbus back-off 0us */ | |
1220 | #define TSI148_LCSR_DCTL_VBOT_1 (1<<8) /* VMEbus back-off 1us */ | |
1221 | #define TSI148_LCSR_DCTL_VBOT_2 (2<<8) /* VMEbus back-off 2us */ | |
1222 | #define TSI148_LCSR_DCTL_VBOT_4 (3<<8) /* VMEbus back-off 4us */ | |
1223 | #define TSI148_LCSR_DCTL_VBOT_8 (4<<8) /* VMEbus back-off 8us */ | |
1224 | #define TSI148_LCSR_DCTL_VBOT_16 (5<<8) /* VMEbus back-off 16us */ | |
1225 | #define TSI148_LCSR_DCTL_VBOT_32 (6<<8) /* VMEbus back-off 32us */ | |
1226 | #define TSI148_LCSR_DCTL_VBOT_64 (7<<8) /* VMEbus back-off 64us */ | |
1227 | ||
1228 | #define TSI148_LCSR_DCTL_PBKS_M (7<<4) /* PCI block size MASK */ | |
1229 | #define TSI148_LCSR_DCTL_PBKS_32 (0<<4) /* PCI block size 32 bytes */ | |
1230 | #define TSI148_LCSR_DCTL_PBKS_64 (1<<4) /* PCI block size 64 bytes */ | |
1231 | #define TSI148_LCSR_DCTL_PBKS_128 (2<<4) /* PCI block size 128 bytes */ | |
1232 | #define TSI148_LCSR_DCTL_PBKS_256 (3<<4) /* PCI block size 256 bytes */ | |
1233 | #define TSI148_LCSR_DCTL_PBKS_512 (4<<4) /* PCI block size 512 bytes */ | |
1234 | #define TSI148_LCSR_DCTL_PBKS_1024 (5<<4) /* PCI block size 1024 bytes */ | |
1235 | #define TSI148_LCSR_DCTL_PBKS_2048 (6<<4) /* PCI block size 2048 bytes */ | |
1236 | #define TSI148_LCSR_DCTL_PBKS_4096 (7<<4) /* PCI block size 4096 bytes */ | |
1237 | ||
1238 | #define TSI148_LCSR_DCTL_PBOT_M (7<<0) /* PCI back off MASK */ | |
1239 | #define TSI148_LCSR_DCTL_PBOT_0 (0<<0) /* PCI back off 0us */ | |
1240 | #define TSI148_LCSR_DCTL_PBOT_1 (1<<0) /* PCI back off 1us */ | |
1241 | #define TSI148_LCSR_DCTL_PBOT_2 (2<<0) /* PCI back off 2us */ | |
1242 | #define TSI148_LCSR_DCTL_PBOT_4 (3<<0) /* PCI back off 3us */ | |
1243 | #define TSI148_LCSR_DCTL_PBOT_8 (4<<0) /* PCI back off 4us */ | |
1244 | #define TSI148_LCSR_DCTL_PBOT_16 (5<<0) /* PCI back off 8us */ | |
1245 | #define TSI148_LCSR_DCTL_PBOT_32 (6<<0) /* PCI back off 16us */ | |
1246 | #define TSI148_LCSR_DCTL_PBOT_64 (7<<0) /* PCI back off 32us */ | |
1247 | ||
1248 | /* | |
1249 | * DMA Status Registers (0-1) CRG + $504 | |
1250 | */ | |
1251 | #define TSI148_LCSR_DSTA_SMA (1<<31) /* PCI Signalled Master Abt */ | |
1252 | #define TSI148_LCSR_DSTA_RTA (1<<30) /* PCI Received Target Abt */ | |
1253 | #define TSI148_LCSR_DSTA_MRC (1<<29) /* PCI Max Retry Count */ | |
1254 | #define TSI148_LCSR_DSTA_VBE (1<<28) /* VMEbus error */ | |
1255 | #define TSI148_LCSR_DSTA_ABT (1<<27) /* Abort */ | |
1256 | #define TSI148_LCSR_DSTA_PAU (1<<26) /* Pause */ | |
1257 | #define TSI148_LCSR_DSTA_DON (1<<25) /* Done */ | |
1258 | #define TSI148_LCSR_DSTA_BSY (1<<24) /* Busy */ | |
1259 | ||
1260 | /* | |
1261 | * DMA Current Link Address Lower (0-1) | |
1262 | */ | |
1263 | #define TSI148_LCSR_DCLAL_M (0x3FFFFFF<<6) /* Mask */ | |
1264 | ||
1265 | /* | |
1266 | * DMA Source Attribute (0-1) Reg | |
1267 | */ | |
1268 | #define TSI148_LCSR_DSAT_TYP_M (3<<28) /* Source Bus Type */ | |
1269 | #define TSI148_LCSR_DSAT_TYP_PCI (0<<28) /* PCI Bus */ | |
1270 | #define TSI148_LCSR_DSAT_TYP_VME (1<<28) /* VMEbus */ | |
1271 | #define TSI148_LCSR_DSAT_TYP_PAT (2<<28) /* Data Pattern */ | |
1272 | ||
1273 | #define TSI148_LCSR_DSAT_PSZ (1<<25) /* Pattern Size */ | |
1274 | #define TSI148_LCSR_DSAT_NIN (1<<24) /* No Increment */ | |
1275 | ||
1276 | #define TSI148_LCSR_DSAT_2eSSTM_M (3<<11) /* 2eSST Trans Rate Mask */ | |
1277 | #define TSI148_LCSR_DSAT_2eSSTM_160 (0<<11) /* 160 MB/s */ | |
1278 | #define TSI148_LCSR_DSAT_2eSSTM_267 (1<<11) /* 267 MB/s */ | |
1279 | #define TSI148_LCSR_DSAT_2eSSTM_320 (2<<11) /* 320 MB/s */ | |
1280 | ||
1281 | #define TSI148_LCSR_DSAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */ | |
1282 | #define TSI148_LCSR_DSAT_TM_SCT (0<<8) /* SCT */ | |
1283 | #define TSI148_LCSR_DSAT_TM_BLT (1<<8) /* BLT */ | |
1284 | #define TSI148_LCSR_DSAT_TM_MBLT (2<<8) /* MBLT */ | |
1285 | #define TSI148_LCSR_DSAT_TM_2eVME (3<<8) /* 2eVME */ | |
1286 | #define TSI148_LCSR_DSAT_TM_2eSST (4<<8) /* 2eSST */ | |
1287 | #define TSI148_LCSR_DSAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */ | |
1288 | ||
1289 | #define TSI148_LCSR_DSAT_DBW_M (3<<6) /* Max Data Width MASK */ | |
1290 | #define TSI148_LCSR_DSAT_DBW_16 (0<<6) /* 16 Bits */ | |
1291 | #define TSI148_LCSR_DSAT_DBW_32 (1<<6) /* 32 Bits */ | |
1292 | ||
1293 | #define TSI148_LCSR_DSAT_SUP (1<<5) /* Supervisory Mode */ | |
1294 | #define TSI148_LCSR_DSAT_PGM (1<<4) /* Program Mode */ | |
1295 | ||
1296 | #define TSI148_LCSR_DSAT_AMODE_M (0xf<<0) /* Address Space Mask */ | |
1297 | #define TSI148_LCSR_DSAT_AMODE_A16 (0<<0) /* A16 */ | |
1298 | #define TSI148_LCSR_DSAT_AMODE_A24 (1<<0) /* A24 */ | |
1299 | #define TSI148_LCSR_DSAT_AMODE_A32 (2<<0) /* A32 */ | |
1300 | #define TSI148_LCSR_DSAT_AMODE_A64 (4<<0) /* A64 */ | |
1301 | #define TSI148_LCSR_DSAT_AMODE_CRCSR (5<<0) /* CR/CSR */ | |
1302 | #define TSI148_LCSR_DSAT_AMODE_USER1 (8<<0) /* User1 */ | |
1303 | #define TSI148_LCSR_DSAT_AMODE_USER2 (9<<0) /* User2 */ | |
1304 | #define TSI148_LCSR_DSAT_AMODE_USER3 (0xa<<0) /* User3 */ | |
1305 | #define TSI148_LCSR_DSAT_AMODE_USER4 (0xb<<0) /* User4 */ | |
1306 | ||
1307 | /* | |
1308 | * DMA Destination Attribute Registers (0-1) | |
1309 | */ | |
1310 | #define TSI148_LCSR_DDAT_TYP_PCI (0<<28) /* Destination PCI Bus */ | |
1311 | #define TSI148_LCSR_DDAT_TYP_VME (1<<28) /* Destination VMEbus */ | |
1312 | ||
1313 | #define TSI148_LCSR_DDAT_2eSSTM_M (3<<11) /* 2eSST Transfer Rate Mask */ | |
1314 | #define TSI148_LCSR_DDAT_2eSSTM_160 (0<<11) /* 160 MB/s */ | |
1315 | #define TSI148_LCSR_DDAT_2eSSTM_267 (1<<11) /* 267 MB/s */ | |
1316 | #define TSI148_LCSR_DDAT_2eSSTM_320 (2<<11) /* 320 MB/s */ | |
1317 | ||
1318 | #define TSI148_LCSR_DDAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */ | |
1319 | #define TSI148_LCSR_DDAT_TM_SCT (0<<8) /* SCT */ | |
1320 | #define TSI148_LCSR_DDAT_TM_BLT (1<<8) /* BLT */ | |
1321 | #define TSI148_LCSR_DDAT_TM_MBLT (2<<8) /* MBLT */ | |
1322 | #define TSI148_LCSR_DDAT_TM_2eVME (3<<8) /* 2eVME */ | |
1323 | #define TSI148_LCSR_DDAT_TM_2eSST (4<<8) /* 2eSST */ | |
1324 | #define TSI148_LCSR_DDAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */ | |
1325 | ||
1326 | #define TSI148_LCSR_DDAT_DBW_M (3<<6) /* Max Data Width MASK */ | |
1327 | #define TSI148_LCSR_DDAT_DBW_16 (0<<6) /* 16 Bits */ | |
1328 | #define TSI148_LCSR_DDAT_DBW_32 (1<<6) /* 32 Bits */ | |
1329 | ||
1330 | #define TSI148_LCSR_DDAT_SUP (1<<5) /* Supervisory/User Access */ | |
1331 | #define TSI148_LCSR_DDAT_PGM (1<<4) /* Program/Data Access */ | |
1332 | ||
1333 | #define TSI148_LCSR_DDAT_AMODE_M (0xf<<0) /* Address Space Mask */ | |
1334 | #define TSI148_LCSR_DDAT_AMODE_A16 (0<<0) /* A16 */ | |
1335 | #define TSI148_LCSR_DDAT_AMODE_A24 (1<<0) /* A24 */ | |
1336 | #define TSI148_LCSR_DDAT_AMODE_A32 (2<<0) /* A32 */ | |
1337 | #define TSI148_LCSR_DDAT_AMODE_A64 (4<<0) /* A64 */ | |
1338 | #define TSI148_LCSR_DDAT_AMODE_CRCSR (5<<0) /* CRC/SR */ | |
1339 | #define TSI148_LCSR_DDAT_AMODE_USER1 (8<<0) /* User1 */ | |
1340 | #define TSI148_LCSR_DDAT_AMODE_USER2 (9<<0) /* User2 */ | |
1341 | #define TSI148_LCSR_DDAT_AMODE_USER3 (0xa<<0) /* User3 */ | |
1342 | #define TSI148_LCSR_DDAT_AMODE_USER4 (0xb<<0) /* User4 */ | |
1343 | ||
1344 | /* | |
1345 | * DMA Next Link Address Lower | |
1346 | */ | |
1347 | #define TSI148_LCSR_DNLAL_DNLAL_M (0x3FFFFFF<<6) /* Address Mask */ | |
7946328f | 1348 | #define TSI148_LCSR_DNLAL_LLA (1<<0) /* Last Link Address Indicator */ |
d22b8ed9 MW |
1349 | |
1350 | /* | |
1351 | * DMA 2eSST Broadcast Select | |
1352 | */ | |
1353 | #define TSI148_LCSR_DBS_M (0x1FFFFF<<0) /* Mask */ | |
1354 | ||
1355 | /* | |
1356 | * GCSR Register Group | |
1357 | */ | |
1358 | ||
1359 | /* | |
1360 | * GCSR Control and Status Register CRG + $604 | |
1361 | */ | |
1362 | #define TSI148_GCSR_GCTRL_LRST (1<<15) /* Local Reset */ | |
1363 | #define TSI148_GCSR_GCTRL_SFAILEN (1<<14) /* System Fail enable */ | |
1364 | #define TSI148_GCSR_GCTRL_BDFAILS (1<<13) /* Board Fail Status */ | |
1365 | #define TSI148_GCSR_GCTRL_SCON (1<<12) /* System Copntroller */ | |
1366 | #define TSI148_GCSR_GCTRL_MEN (1<<11) /* Module Enable (READY) */ | |
1367 | ||
1368 | #define TSI148_GCSR_GCTRL_LMI3S (1<<7) /* Loc Monitor 3 Int Status */ | |
1369 | #define TSI148_GCSR_GCTRL_LMI2S (1<<6) /* Loc Monitor 2 Int Status */ | |
1370 | #define TSI148_GCSR_GCTRL_LMI1S (1<<5) /* Loc Monitor 1 Int Status */ | |
1371 | #define TSI148_GCSR_GCTRL_LMI0S (1<<4) /* Loc Monitor 0 Int Status */ | |
1372 | #define TSI148_GCSR_GCTRL_MBI3S (1<<3) /* Mail box 3 Int Status */ | |
1373 | #define TSI148_GCSR_GCTRL_MBI2S (1<<2) /* Mail box 2 Int Status */ | |
1374 | #define TSI148_GCSR_GCTRL_MBI1S (1<<1) /* Mail box 1 Int Status */ | |
1375 | #define TSI148_GCSR_GCTRL_MBI0S (1<<0) /* Mail box 0 Int Status */ | |
1376 | ||
1377 | #define TSI148_GCSR_GAP (1<<5) /* Geographic Addr Parity */ | |
7946328f | 1378 | #define TSI148_GCSR_GA_M (0x1F<<0) /* Geographic Address Mask */ |
d22b8ed9 MW |
1379 | |
1380 | /* | |
1381 | * CR/CSR Register Group | |
1382 | */ | |
1383 | ||
1384 | /* | |
1385 | * CR/CSR Bit Clear Register CRG + $FF4 | |
1386 | */ | |
1387 | #define TSI148_CRCSR_CSRBCR_LRSTC (1<<7) /* Local Reset Clear */ | |
1388 | #define TSI148_CRCSR_CSRBCR_SFAILC (1<<6) /* System Fail Enable Clear */ | |
1389 | #define TSI148_CRCSR_CSRBCR_BDFAILS (1<<5) /* Board Fail Status */ | |
1390 | #define TSI148_CRCSR_CSRBCR_MENC (1<<4) /* Module Enable Clear */ | |
1391 | #define TSI148_CRCSR_CSRBCR_BERRSC (1<<3) /* Bus Error Status Clear */ | |
1392 | ||
1393 | /* | |
1394 | * CR/CSR Bit Set Register CRG+$FF8 | |
1395 | */ | |
1396 | #define TSI148_CRCSR_CSRBSR_LISTS (1<<7) /* Local Reset Clear */ | |
1397 | #define TSI148_CRCSR_CSRBSR_SFAILS (1<<6) /* System Fail Enable Clear */ | |
1398 | #define TSI148_CRCSR_CSRBSR_BDFAILS (1<<5) /* Board Fail Status */ | |
1399 | #define TSI148_CRCSR_CSRBSR_MENS (1<<4) /* Module Enable Clear */ | |
1400 | #define TSI148_CRCSR_CSRBSR_BERRS (1<<3) /* Bus Error Status Clear */ | |
1401 | ||
1402 | /* | |
1403 | * CR/CSR Base Address Register CRG + FFC | |
1404 | */ | |
1405 | #define TSI148_CRCSR_CBAR_M (0x1F<<3) /* Mask */ | |
1406 | ||
1407 | #endif /* TSI148_H */ |