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d22b8ed9 MW |
1 | /* |
2 | * Support for the Tundra TSI148 VME-PCI Bridge Chip | |
3 | * | |
66bd8db5 MW |
4 | * Author: Martyn Welch <martyn.welch@ge.com> |
5 | * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. | |
d22b8ed9 MW |
6 | * |
7 | * Based on work by Tom Armistead and Ajit Prem | |
8 | * Copyright 2004 Motorola Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | ||
d22b8ed9 MW |
16 | #include <linux/module.h> |
17 | #include <linux/moduleparam.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/proc_fs.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/poll.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/spinlock.h> | |
6af783c8 | 27 | #include <linux/sched.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
7946328f MW |
29 | #include <linux/time.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/uaccess.h> | |
ac1a4f2c | 32 | #include <linux/byteorder/generic.h> |
db3b9e99 | 33 | #include <linux/vme.h> |
d22b8ed9 | 34 | |
d22b8ed9 MW |
35 | #include "../vme_bridge.h" |
36 | #include "vme_tsi148.h" | |
37 | ||
d22b8ed9 MW |
38 | static int tsi148_probe(struct pci_dev *, const struct pci_device_id *); |
39 | static void tsi148_remove(struct pci_dev *); | |
d22b8ed9 MW |
40 | |
41 | ||
29848ac9 | 42 | /* Module parameter */ |
90ab5ee9 | 43 | static bool err_chk; |
638f199d | 44 | static int geoid; |
d22b8ed9 | 45 | |
584721ca | 46 | static const char driver_name[] = "vme_tsi148"; |
d22b8ed9 | 47 | |
c3a09c18 | 48 | static const struct pci_device_id tsi148_ids[] = { |
d22b8ed9 MW |
49 | { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) }, |
50 | { }, | |
51 | }; | |
52 | ||
53 | static struct pci_driver tsi148_driver = { | |
54 | .name = driver_name, | |
55 | .id_table = tsi148_ids, | |
56 | .probe = tsi148_probe, | |
57 | .remove = tsi148_remove, | |
58 | }; | |
59 | ||
60 | static void reg_join(unsigned int high, unsigned int low, | |
61 | unsigned long long *variable) | |
62 | { | |
63 | *variable = (unsigned long long)high << 32; | |
64 | *variable |= (unsigned long long)low; | |
65 | } | |
66 | ||
67 | static void reg_split(unsigned long long variable, unsigned int *high, | |
68 | unsigned int *low) | |
69 | { | |
70 | *low = (unsigned int)variable & 0xFFFFFFFF; | |
71 | *high = (unsigned int)(variable >> 32); | |
72 | } | |
73 | ||
74 | /* | |
75 | * Wakes up DMA queue. | |
76 | */ | |
29848ac9 MW |
77 | static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge, |
78 | int channel_mask) | |
d22b8ed9 MW |
79 | { |
80 | u32 serviced = 0; | |
81 | ||
82 | if (channel_mask & TSI148_LCSR_INTS_DMA0S) { | |
886953e9 | 83 | wake_up(&bridge->dma_queue[0]); |
d22b8ed9 MW |
84 | serviced |= TSI148_LCSR_INTC_DMA0C; |
85 | } | |
86 | if (channel_mask & TSI148_LCSR_INTS_DMA1S) { | |
886953e9 | 87 | wake_up(&bridge->dma_queue[1]); |
d22b8ed9 MW |
88 | serviced |= TSI148_LCSR_INTC_DMA1C; |
89 | } | |
90 | ||
91 | return serviced; | |
92 | } | |
93 | ||
94 | /* | |
95 | * Wake up location monitor queue | |
96 | */ | |
29848ac9 | 97 | static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat) |
d22b8ed9 MW |
98 | { |
99 | int i; | |
100 | u32 serviced = 0; | |
101 | ||
102 | for (i = 0; i < 4; i++) { | |
7946328f | 103 | if (stat & TSI148_LCSR_INTS_LMS[i]) { |
d22b8ed9 | 104 | /* We only enable interrupts if the callback is set */ |
29848ac9 | 105 | bridge->lm_callback[i](i); |
d22b8ed9 MW |
106 | serviced |= TSI148_LCSR_INTC_LMC[i]; |
107 | } | |
108 | } | |
109 | ||
110 | return serviced; | |
111 | } | |
112 | ||
113 | /* | |
114 | * Wake up mail box queue. | |
115 | * | |
116 | * XXX This functionality is not exposed up though API. | |
117 | */ | |
48d9356e | 118 | static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat) |
d22b8ed9 MW |
119 | { |
120 | int i; | |
121 | u32 val; | |
122 | u32 serviced = 0; | |
48d9356e MW |
123 | struct tsi148_driver *bridge; |
124 | ||
125 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
126 | |
127 | for (i = 0; i < 4; i++) { | |
7946328f | 128 | if (stat & TSI148_LCSR_INTS_MBS[i]) { |
29848ac9 | 129 | val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); |
48d9356e MW |
130 | dev_err(tsi148_bridge->parent, "VME Mailbox %d received" |
131 | ": 0x%x\n", i, val); | |
d22b8ed9 MW |
132 | serviced |= TSI148_LCSR_INTC_MBC[i]; |
133 | } | |
134 | } | |
135 | ||
136 | return serviced; | |
137 | } | |
138 | ||
139 | /* | |
140 | * Display error & status message when PERR (PCI) exception interrupt occurs. | |
141 | */ | |
48d9356e | 142 | static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge) |
d22b8ed9 | 143 | { |
48d9356e MW |
144 | struct tsi148_driver *bridge; |
145 | ||
146 | bridge = tsi148_bridge->driver_priv; | |
147 | ||
148 | dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, " | |
149 | "attributes: %08x\n", | |
29848ac9 MW |
150 | ioread32be(bridge->base + TSI148_LCSR_EDPAU), |
151 | ioread32be(bridge->base + TSI148_LCSR_EDPAL), | |
48d9356e MW |
152 | ioread32be(bridge->base + TSI148_LCSR_EDPAT)); |
153 | ||
154 | dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split " | |
155 | "completion reg: %08x\n", | |
29848ac9 | 156 | ioread32be(bridge->base + TSI148_LCSR_EDPXA), |
48d9356e | 157 | ioread32be(bridge->base + TSI148_LCSR_EDPXS)); |
d22b8ed9 | 158 | |
29848ac9 | 159 | iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); |
d22b8ed9 MW |
160 | |
161 | return TSI148_LCSR_INTC_PERRC; | |
162 | } | |
163 | ||
164 | /* | |
165 | * Save address and status when VME error interrupt occurs. | |
166 | */ | |
29848ac9 | 167 | static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge) |
d22b8ed9 MW |
168 | { |
169 | unsigned int error_addr_high, error_addr_low; | |
170 | unsigned long long error_addr; | |
171 | u32 error_attrib; | |
472f16f3 | 172 | int error_am; |
29848ac9 MW |
173 | struct tsi148_driver *bridge; |
174 | ||
175 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 176 | |
29848ac9 MW |
177 | error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); |
178 | error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); | |
179 | error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); | |
472f16f3 | 180 | error_am = (error_attrib & TSI148_LCSR_VEAT_AM_M) >> 8; |
d22b8ed9 MW |
181 | |
182 | reg_join(error_addr_high, error_addr_low, &error_addr); | |
183 | ||
184 | /* Check for exception register overflow (we have lost error data) */ | |
7946328f | 185 | if (error_attrib & TSI148_LCSR_VEAT_VEOF) { |
48d9356e MW |
186 | dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow " |
187 | "Occurred\n"); | |
d22b8ed9 MW |
188 | } |
189 | ||
e2c6393f | 190 | if (err_chk) |
472f16f3 | 191 | vme_bus_error_handler(tsi148_bridge, error_addr, error_am); |
e2c6393f | 192 | else |
e31c51e4 MW |
193 | dev_err(tsi148_bridge->parent, |
194 | "VME Bus Error at address: 0x%llx, attributes: %08x\n", | |
195 | error_addr, error_attrib); | |
d22b8ed9 MW |
196 | |
197 | /* Clear Status */ | |
29848ac9 | 198 | iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT); |
d22b8ed9 MW |
199 | |
200 | return TSI148_LCSR_INTC_VERRC; | |
201 | } | |
202 | ||
203 | /* | |
204 | * Wake up IACK queue. | |
205 | */ | |
29848ac9 | 206 | static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge) |
d22b8ed9 | 207 | { |
886953e9 | 208 | wake_up(&bridge->iack_queue); |
d22b8ed9 MW |
209 | |
210 | return TSI148_LCSR_INTC_IACKC; | |
211 | } | |
212 | ||
213 | /* | |
214 | * Calling VME bus interrupt callback if provided. | |
215 | */ | |
29848ac9 MW |
216 | static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge, |
217 | u32 stat) | |
d22b8ed9 MW |
218 | { |
219 | int vec, i, serviced = 0; | |
29848ac9 MW |
220 | struct tsi148_driver *bridge; |
221 | ||
222 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
223 | |
224 | for (i = 7; i > 0; i--) { | |
225 | if (stat & (1 << i)) { | |
226 | /* | |
7946328f MW |
227 | * Note: Even though the registers are defined as |
228 | * 32-bits in the spec, we only want to issue 8-bit | |
229 | * IACK cycles on the bus, read from offset 3. | |
d22b8ed9 | 230 | */ |
29848ac9 | 231 | vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3); |
d22b8ed9 | 232 | |
c813f592 | 233 | vme_irq_handler(tsi148_bridge, i, vec); |
d22b8ed9 MW |
234 | |
235 | serviced |= (1 << i); | |
236 | } | |
237 | } | |
238 | ||
239 | return serviced; | |
240 | } | |
241 | ||
242 | /* | |
243 | * Top level interrupt handler. Clears appropriate interrupt status bits and | |
244 | * then calls appropriate sub handler(s). | |
245 | */ | |
29848ac9 | 246 | static irqreturn_t tsi148_irqhandler(int irq, void *ptr) |
d22b8ed9 MW |
247 | { |
248 | u32 stat, enable, serviced = 0; | |
29848ac9 MW |
249 | struct vme_bridge *tsi148_bridge; |
250 | struct tsi148_driver *bridge; | |
251 | ||
252 | tsi148_bridge = ptr; | |
253 | ||
254 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
255 | |
256 | /* Determine which interrupts are unmasked and set */ | |
29848ac9 MW |
257 | enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
258 | stat = ioread32be(bridge->base + TSI148_LCSR_INTS); | |
d22b8ed9 MW |
259 | |
260 | /* Only look at unmasked interrupts */ | |
261 | stat &= enable; | |
262 | ||
7946328f | 263 | if (unlikely(!stat)) |
d22b8ed9 | 264 | return IRQ_NONE; |
d22b8ed9 MW |
265 | |
266 | /* Call subhandlers as appropriate */ | |
267 | /* DMA irqs */ | |
268 | if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S)) | |
29848ac9 | 269 | serviced |= tsi148_DMA_irqhandler(bridge, stat); |
d22b8ed9 MW |
270 | |
271 | /* Location monitor irqs */ | |
272 | if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S | | |
273 | TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S)) | |
29848ac9 | 274 | serviced |= tsi148_LM_irqhandler(bridge, stat); |
d22b8ed9 MW |
275 | |
276 | /* Mail box irqs */ | |
277 | if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S | | |
278 | TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S)) | |
48d9356e | 279 | serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat); |
d22b8ed9 MW |
280 | |
281 | /* PCI bus error */ | |
282 | if (stat & TSI148_LCSR_INTS_PERRS) | |
48d9356e | 283 | serviced |= tsi148_PERR_irqhandler(tsi148_bridge); |
d22b8ed9 MW |
284 | |
285 | /* VME bus error */ | |
286 | if (stat & TSI148_LCSR_INTS_VERRS) | |
29848ac9 | 287 | serviced |= tsi148_VERR_irqhandler(tsi148_bridge); |
d22b8ed9 MW |
288 | |
289 | /* IACK irq */ | |
290 | if (stat & TSI148_LCSR_INTS_IACKS) | |
29848ac9 | 291 | serviced |= tsi148_IACK_irqhandler(bridge); |
d22b8ed9 MW |
292 | |
293 | /* VME bus irqs */ | |
294 | if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S | | |
295 | TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S | | |
296 | TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S | | |
297 | TSI148_LCSR_INTS_IRQ1S)) | |
29848ac9 | 298 | serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat); |
d22b8ed9 MW |
299 | |
300 | /* Clear serviced interrupts */ | |
29848ac9 | 301 | iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC); |
d22b8ed9 MW |
302 | |
303 | return IRQ_HANDLED; | |
304 | } | |
305 | ||
29848ac9 | 306 | static int tsi148_irq_init(struct vme_bridge *tsi148_bridge) |
d22b8ed9 MW |
307 | { |
308 | int result; | |
309 | unsigned int tmp; | |
310 | struct pci_dev *pdev; | |
29848ac9 MW |
311 | struct tsi148_driver *bridge; |
312 | ||
177581fa | 313 | pdev = to_pci_dev(tsi148_bridge->parent); |
d22b8ed9 | 314 | |
29848ac9 | 315 | bridge = tsi148_bridge->driver_priv; |
d22b8ed9 | 316 | |
d22b8ed9 MW |
317 | result = request_irq(pdev->irq, |
318 | tsi148_irqhandler, | |
319 | IRQF_SHARED, | |
29848ac9 | 320 | driver_name, tsi148_bridge); |
d22b8ed9 | 321 | if (result) { |
48d9356e MW |
322 | dev_err(tsi148_bridge->parent, "Can't get assigned pci irq " |
323 | "vector %02X\n", pdev->irq); | |
d22b8ed9 MW |
324 | return result; |
325 | } | |
326 | ||
327 | /* Enable and unmask interrupts */ | |
328 | tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO | | |
329 | TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO | | |
330 | TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO | | |
331 | TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO | | |
332 | TSI148_LCSR_INTEO_IACKEO; | |
333 | ||
29848ac9 | 334 | /* This leaves the following interrupts masked. |
d22b8ed9 MW |
335 | * TSI148_LCSR_INTEO_VIEEO |
336 | * TSI148_LCSR_INTEO_SYSFLEO | |
337 | * TSI148_LCSR_INTEO_ACFLEO | |
338 | */ | |
339 | ||
340 | /* Don't enable Location Monitor interrupts here - they will be | |
341 | * enabled when the location monitors are properly configured and | |
342 | * a callback has been attached. | |
343 | * TSI148_LCSR_INTEO_LM0EO | |
344 | * TSI148_LCSR_INTEO_LM1EO | |
345 | * TSI148_LCSR_INTEO_LM2EO | |
346 | * TSI148_LCSR_INTEO_LM3EO | |
347 | */ | |
348 | ||
349 | /* Don't enable VME interrupts until we add a handler, else the board | |
350 | * will respond to it and we don't want that unless it knows how to | |
351 | * properly deal with it. | |
352 | * TSI148_LCSR_INTEO_IRQ7EO | |
353 | * TSI148_LCSR_INTEO_IRQ6EO | |
354 | * TSI148_LCSR_INTEO_IRQ5EO | |
355 | * TSI148_LCSR_INTEO_IRQ4EO | |
356 | * TSI148_LCSR_INTEO_IRQ3EO | |
357 | * TSI148_LCSR_INTEO_IRQ2EO | |
358 | * TSI148_LCSR_INTEO_IRQ1EO | |
359 | */ | |
360 | ||
361 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); | |
362 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); | |
363 | ||
364 | return 0; | |
365 | } | |
366 | ||
a82ad05e EC |
367 | static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge, |
368 | struct pci_dev *pdev) | |
d22b8ed9 | 369 | { |
a82ad05e EC |
370 | struct tsi148_driver *bridge = tsi148_bridge->driver_priv; |
371 | ||
d22b8ed9 | 372 | /* Turn off interrupts */ |
29848ac9 MW |
373 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO); |
374 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN); | |
d22b8ed9 MW |
375 | |
376 | /* Clear all interrupts */ | |
29848ac9 | 377 | iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC); |
d22b8ed9 MW |
378 | |
379 | /* Detach interrupt handler */ | |
a82ad05e | 380 | free_irq(pdev->irq, tsi148_bridge); |
d22b8ed9 MW |
381 | } |
382 | ||
383 | /* | |
384 | * Check to see if an IACk has been received, return true (1) or false (0). | |
385 | */ | |
5ade6c4d | 386 | static int tsi148_iack_received(struct tsi148_driver *bridge) |
d22b8ed9 MW |
387 | { |
388 | u32 tmp; | |
389 | ||
29848ac9 | 390 | tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); |
d22b8ed9 MW |
391 | |
392 | if (tmp & TSI148_LCSR_VICR_IRQS) | |
393 | return 0; | |
394 | else | |
395 | return 1; | |
396 | } | |
397 | ||
398 | /* | |
c813f592 | 399 | * Configure VME interrupt |
d22b8ed9 | 400 | */ |
5ade6c4d | 401 | static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level, |
29848ac9 | 402 | int state, int sync) |
d22b8ed9 | 403 | { |
75155020 | 404 | struct pci_dev *pdev; |
c813f592 | 405 | u32 tmp; |
29848ac9 MW |
406 | struct tsi148_driver *bridge; |
407 | ||
408 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 409 | |
c813f592 MW |
410 | /* We need to do the ordering differently for enabling and disabling */ |
411 | if (state == 0) { | |
29848ac9 | 412 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
d22b8ed9 | 413 | tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1]; |
29848ac9 | 414 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); |
df455175 | 415 | |
29848ac9 | 416 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
df455175 | 417 | tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1]; |
29848ac9 | 418 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
75155020 | 419 | |
c813f592 | 420 | if (sync != 0) { |
177581fa | 421 | pdev = to_pci_dev(tsi148_bridge->parent); |
c813f592 MW |
422 | synchronize_irq(pdev->irq); |
423 | } | |
424 | } else { | |
29848ac9 | 425 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
c813f592 | 426 | tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1]; |
29848ac9 | 427 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
df455175 | 428 | |
29848ac9 | 429 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
c813f592 | 430 | tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1]; |
29848ac9 | 431 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); |
c813f592 | 432 | } |
d22b8ed9 MW |
433 | } |
434 | ||
435 | /* | |
436 | * Generate a VME bus interrupt at the requested level & vector. Wait for | |
437 | * interrupt to be acked. | |
d22b8ed9 | 438 | */ |
5ade6c4d EC |
439 | static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, |
440 | int statid) | |
d22b8ed9 MW |
441 | { |
442 | u32 tmp; | |
29848ac9 MW |
443 | struct tsi148_driver *bridge; |
444 | ||
445 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 446 | |
886953e9 | 447 | mutex_lock(&bridge->vme_int); |
d22b8ed9 MW |
448 | |
449 | /* Read VICR register */ | |
29848ac9 | 450 | tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); |
d22b8ed9 MW |
451 | |
452 | /* Set Status/ID */ | |
453 | tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) | | |
454 | (statid & TSI148_LCSR_VICR_STID_M); | |
29848ac9 | 455 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); |
d22b8ed9 MW |
456 | |
457 | /* Assert VMEbus IRQ */ | |
458 | tmp = tmp | TSI148_LCSR_VICR_IRQL[level]; | |
29848ac9 | 459 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); |
d22b8ed9 MW |
460 | |
461 | /* XXX Consider implementing a timeout? */ | |
29848ac9 MW |
462 | wait_event_interruptible(bridge->iack_queue, |
463 | tsi148_iack_received(bridge)); | |
d22b8ed9 | 464 | |
886953e9 | 465 | mutex_unlock(&bridge->vme_int); |
d22b8ed9 MW |
466 | |
467 | return 0; | |
468 | } | |
469 | ||
d22b8ed9 MW |
470 | /* |
471 | * Initialize a slave window with the requested attributes. | |
472 | */ | |
5ade6c4d | 473 | static int tsi148_slave_set(struct vme_slave_resource *image, int enabled, |
d22b8ed9 | 474 | unsigned long long vme_base, unsigned long long size, |
6af04b06 | 475 | dma_addr_t pci_base, u32 aspace, u32 cycle) |
d22b8ed9 MW |
476 | { |
477 | unsigned int i, addr = 0, granularity = 0; | |
478 | unsigned int temp_ctl = 0; | |
479 | unsigned int vme_base_low, vme_base_high; | |
480 | unsigned int vme_bound_low, vme_bound_high; | |
481 | unsigned int pci_offset_low, pci_offset_high; | |
482 | unsigned long long vme_bound, pci_offset; | |
48d9356e | 483 | struct vme_bridge *tsi148_bridge; |
29848ac9 MW |
484 | struct tsi148_driver *bridge; |
485 | ||
48d9356e MW |
486 | tsi148_bridge = image->parent; |
487 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 488 | |
d22b8ed9 MW |
489 | i = image->number; |
490 | ||
491 | switch (aspace) { | |
492 | case VME_A16: | |
493 | granularity = 0x10; | |
494 | addr |= TSI148_LCSR_ITAT_AS_A16; | |
495 | break; | |
496 | case VME_A24: | |
497 | granularity = 0x1000; | |
498 | addr |= TSI148_LCSR_ITAT_AS_A24; | |
499 | break; | |
500 | case VME_A32: | |
501 | granularity = 0x10000; | |
502 | addr |= TSI148_LCSR_ITAT_AS_A32; | |
503 | break; | |
504 | case VME_A64: | |
505 | granularity = 0x10000; | |
506 | addr |= TSI148_LCSR_ITAT_AS_A64; | |
507 | break; | |
d22b8ed9 | 508 | default: |
48d9356e | 509 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
d22b8ed9 MW |
510 | return -EINVAL; |
511 | break; | |
512 | } | |
513 | ||
514 | /* Convert 64-bit variables to 2x 32-bit variables */ | |
515 | reg_split(vme_base, &vme_base_high, &vme_base_low); | |
516 | ||
517 | /* | |
518 | * Bound address is a valid address for the window, adjust | |
519 | * accordingly | |
520 | */ | |
521 | vme_bound = vme_base + size - granularity; | |
522 | reg_split(vme_bound, &vme_bound_high, &vme_bound_low); | |
523 | pci_offset = (unsigned long long)pci_base - vme_base; | |
524 | reg_split(pci_offset, &pci_offset_high, &pci_offset_low); | |
525 | ||
526 | if (vme_base_low & (granularity - 1)) { | |
48d9356e | 527 | dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n"); |
d22b8ed9 MW |
528 | return -EINVAL; |
529 | } | |
530 | if (vme_bound_low & (granularity - 1)) { | |
48d9356e | 531 | dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n"); |
d22b8ed9 MW |
532 | return -EINVAL; |
533 | } | |
534 | if (pci_offset_low & (granularity - 1)) { | |
48d9356e MW |
535 | dev_err(tsi148_bridge->parent, "Invalid PCI Offset " |
536 | "alignment\n"); | |
d22b8ed9 MW |
537 | return -EINVAL; |
538 | } | |
539 | ||
d22b8ed9 | 540 | /* Disable while we are mucking around */ |
29848ac9 | 541 | temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
542 | TSI148_LCSR_OFFSET_ITAT); |
543 | temp_ctl &= ~TSI148_LCSR_ITAT_EN; | |
29848ac9 | 544 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
545 | TSI148_LCSR_OFFSET_ITAT); |
546 | ||
547 | /* Setup mapping */ | |
29848ac9 | 548 | iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 549 | TSI148_LCSR_OFFSET_ITSAU); |
29848ac9 | 550 | iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 551 | TSI148_LCSR_OFFSET_ITSAL); |
29848ac9 | 552 | iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 553 | TSI148_LCSR_OFFSET_ITEAU); |
29848ac9 | 554 | iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 555 | TSI148_LCSR_OFFSET_ITEAL); |
29848ac9 | 556 | iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 557 | TSI148_LCSR_OFFSET_ITOFU); |
29848ac9 | 558 | iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
559 | TSI148_LCSR_OFFSET_ITOFL); |
560 | ||
d22b8ed9 MW |
561 | /* Setup 2eSST speeds */ |
562 | temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M; | |
563 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { | |
564 | case VME_2eSST160: | |
565 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160; | |
566 | break; | |
567 | case VME_2eSST267: | |
568 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267; | |
569 | break; | |
570 | case VME_2eSST320: | |
571 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320; | |
572 | break; | |
573 | } | |
574 | ||
575 | /* Setup cycle types */ | |
576 | temp_ctl &= ~(0x1F << 7); | |
577 | if (cycle & VME_BLT) | |
578 | temp_ctl |= TSI148_LCSR_ITAT_BLT; | |
579 | if (cycle & VME_MBLT) | |
580 | temp_ctl |= TSI148_LCSR_ITAT_MBLT; | |
581 | if (cycle & VME_2eVME) | |
582 | temp_ctl |= TSI148_LCSR_ITAT_2eVME; | |
583 | if (cycle & VME_2eSST) | |
584 | temp_ctl |= TSI148_LCSR_ITAT_2eSST; | |
585 | if (cycle & VME_2eSSTB) | |
586 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTB; | |
587 | ||
588 | /* Setup address space */ | |
589 | temp_ctl &= ~TSI148_LCSR_ITAT_AS_M; | |
590 | temp_ctl |= addr; | |
591 | ||
592 | temp_ctl &= ~0xF; | |
593 | if (cycle & VME_SUPER) | |
594 | temp_ctl |= TSI148_LCSR_ITAT_SUPR ; | |
595 | if (cycle & VME_USER) | |
596 | temp_ctl |= TSI148_LCSR_ITAT_NPRIV; | |
597 | if (cycle & VME_PROG) | |
598 | temp_ctl |= TSI148_LCSR_ITAT_PGM; | |
599 | if (cycle & VME_DATA) | |
600 | temp_ctl |= TSI148_LCSR_ITAT_DATA; | |
601 | ||
602 | /* Write ctl reg without enable */ | |
29848ac9 | 603 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
604 | TSI148_LCSR_OFFSET_ITAT); |
605 | ||
606 | if (enabled) | |
607 | temp_ctl |= TSI148_LCSR_ITAT_EN; | |
608 | ||
29848ac9 | 609 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
610 | TSI148_LCSR_OFFSET_ITAT); |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
615 | /* | |
616 | * Get slave window configuration. | |
d22b8ed9 | 617 | */ |
5ade6c4d | 618 | static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled, |
d22b8ed9 | 619 | unsigned long long *vme_base, unsigned long long *size, |
6af04b06 | 620 | dma_addr_t *pci_base, u32 *aspace, u32 *cycle) |
d22b8ed9 MW |
621 | { |
622 | unsigned int i, granularity = 0, ctl = 0; | |
623 | unsigned int vme_base_low, vme_base_high; | |
624 | unsigned int vme_bound_low, vme_bound_high; | |
625 | unsigned int pci_offset_low, pci_offset_high; | |
626 | unsigned long long vme_bound, pci_offset; | |
29848ac9 | 627 | struct tsi148_driver *bridge; |
d22b8ed9 | 628 | |
29848ac9 | 629 | bridge = image->parent->driver_priv; |
d22b8ed9 MW |
630 | |
631 | i = image->number; | |
632 | ||
633 | /* Read registers */ | |
29848ac9 | 634 | ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
635 | TSI148_LCSR_OFFSET_ITAT); |
636 | ||
29848ac9 | 637 | vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 638 | TSI148_LCSR_OFFSET_ITSAU); |
29848ac9 | 639 | vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 640 | TSI148_LCSR_OFFSET_ITSAL); |
29848ac9 | 641 | vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 642 | TSI148_LCSR_OFFSET_ITEAU); |
29848ac9 | 643 | vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 644 | TSI148_LCSR_OFFSET_ITEAL); |
29848ac9 | 645 | pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 646 | TSI148_LCSR_OFFSET_ITOFU); |
29848ac9 | 647 | pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
648 | TSI148_LCSR_OFFSET_ITOFL); |
649 | ||
650 | /* Convert 64-bit variables to 2x 32-bit variables */ | |
651 | reg_join(vme_base_high, vme_base_low, vme_base); | |
652 | reg_join(vme_bound_high, vme_bound_low, &vme_bound); | |
653 | reg_join(pci_offset_high, pci_offset_low, &pci_offset); | |
654 | ||
098ced8f | 655 | *pci_base = (dma_addr_t)(*vme_base + pci_offset); |
d22b8ed9 MW |
656 | |
657 | *enabled = 0; | |
658 | *aspace = 0; | |
659 | *cycle = 0; | |
660 | ||
661 | if (ctl & TSI148_LCSR_ITAT_EN) | |
662 | *enabled = 1; | |
663 | ||
664 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) { | |
665 | granularity = 0x10; | |
666 | *aspace |= VME_A16; | |
667 | } | |
668 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) { | |
669 | granularity = 0x1000; | |
670 | *aspace |= VME_A24; | |
671 | } | |
672 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) { | |
673 | granularity = 0x10000; | |
674 | *aspace |= VME_A32; | |
675 | } | |
676 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) { | |
677 | granularity = 0x10000; | |
678 | *aspace |= VME_A64; | |
679 | } | |
680 | ||
681 | /* Need granularity before we set the size */ | |
682 | *size = (unsigned long long)((vme_bound - *vme_base) + granularity); | |
683 | ||
684 | ||
685 | if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160) | |
686 | *cycle |= VME_2eSST160; | |
687 | if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267) | |
688 | *cycle |= VME_2eSST267; | |
689 | if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320) | |
690 | *cycle |= VME_2eSST320; | |
691 | ||
692 | if (ctl & TSI148_LCSR_ITAT_BLT) | |
693 | *cycle |= VME_BLT; | |
694 | if (ctl & TSI148_LCSR_ITAT_MBLT) | |
695 | *cycle |= VME_MBLT; | |
696 | if (ctl & TSI148_LCSR_ITAT_2eVME) | |
697 | *cycle |= VME_2eVME; | |
698 | if (ctl & TSI148_LCSR_ITAT_2eSST) | |
699 | *cycle |= VME_2eSST; | |
700 | if (ctl & TSI148_LCSR_ITAT_2eSSTB) | |
701 | *cycle |= VME_2eSSTB; | |
702 | ||
703 | if (ctl & TSI148_LCSR_ITAT_SUPR) | |
704 | *cycle |= VME_SUPER; | |
705 | if (ctl & TSI148_LCSR_ITAT_NPRIV) | |
706 | *cycle |= VME_USER; | |
707 | if (ctl & TSI148_LCSR_ITAT_PGM) | |
708 | *cycle |= VME_PROG; | |
709 | if (ctl & TSI148_LCSR_ITAT_DATA) | |
710 | *cycle |= VME_DATA; | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
715 | /* | |
716 | * Allocate and map PCI Resource | |
717 | */ | |
718 | static int tsi148_alloc_resource(struct vme_master_resource *image, | |
719 | unsigned long long size) | |
720 | { | |
721 | unsigned long long existing_size; | |
722 | int retval = 0; | |
723 | struct pci_dev *pdev; | |
29848ac9 MW |
724 | struct vme_bridge *tsi148_bridge; |
725 | ||
726 | tsi148_bridge = image->parent; | |
d22b8ed9 | 727 | |
177581fa | 728 | pdev = to_pci_dev(tsi148_bridge->parent); |
d22b8ed9 | 729 | |
8fafb476 MW |
730 | existing_size = (unsigned long long)(image->bus_resource.end - |
731 | image->bus_resource.start); | |
d22b8ed9 MW |
732 | |
733 | /* If the existing size is OK, return */ | |
59c22904 | 734 | if ((size != 0) && (existing_size == (size - 1))) |
d22b8ed9 MW |
735 | return 0; |
736 | ||
737 | if (existing_size != 0) { | |
738 | iounmap(image->kern_base); | |
739 | image->kern_base = NULL; | |
794a8946 | 740 | kfree(image->bus_resource.name); |
886953e9 EC |
741 | release_resource(&image->bus_resource); |
742 | memset(&image->bus_resource, 0, sizeof(struct resource)); | |
d22b8ed9 MW |
743 | } |
744 | ||
59c22904 | 745 | /* Exit here if size is zero */ |
7946328f | 746 | if (size == 0) |
59c22904 | 747 | return 0; |
59c22904 | 748 | |
8fafb476 | 749 | if (image->bus_resource.name == NULL) { |
0aa3f139 | 750 | image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC); |
8fafb476 | 751 | if (image->bus_resource.name == NULL) { |
48d9356e MW |
752 | dev_err(tsi148_bridge->parent, "Unable to allocate " |
753 | "memory for resource name\n"); | |
d22b8ed9 MW |
754 | retval = -ENOMEM; |
755 | goto err_name; | |
756 | } | |
757 | } | |
758 | ||
8fafb476 | 759 | sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name, |
d22b8ed9 MW |
760 | image->number); |
761 | ||
8fafb476 MW |
762 | image->bus_resource.start = 0; |
763 | image->bus_resource.end = (unsigned long)size; | |
764 | image->bus_resource.flags = IORESOURCE_MEM; | |
d22b8ed9 MW |
765 | |
766 | retval = pci_bus_alloc_resource(pdev->bus, | |
da5ae8a9 | 767 | &image->bus_resource, size, 0x10000, PCIBIOS_MIN_MEM, |
d22b8ed9 MW |
768 | 0, NULL, NULL); |
769 | if (retval) { | |
48d9356e MW |
770 | dev_err(tsi148_bridge->parent, "Failed to allocate mem " |
771 | "resource for window %d size 0x%lx start 0x%lx\n", | |
d22b8ed9 | 772 | image->number, (unsigned long)size, |
8fafb476 | 773 | (unsigned long)image->bus_resource.start); |
d22b8ed9 MW |
774 | goto err_resource; |
775 | } | |
776 | ||
777 | image->kern_base = ioremap_nocache( | |
8fafb476 | 778 | image->bus_resource.start, size); |
d22b8ed9 | 779 | if (image->kern_base == NULL) { |
48d9356e | 780 | dev_err(tsi148_bridge->parent, "Failed to remap resource\n"); |
d22b8ed9 MW |
781 | retval = -ENOMEM; |
782 | goto err_remap; | |
783 | } | |
784 | ||
785 | return 0; | |
786 | ||
d22b8ed9 | 787 | err_remap: |
886953e9 | 788 | release_resource(&image->bus_resource); |
d22b8ed9 | 789 | err_resource: |
8fafb476 | 790 | kfree(image->bus_resource.name); |
886953e9 | 791 | memset(&image->bus_resource, 0, sizeof(struct resource)); |
d22b8ed9 MW |
792 | err_name: |
793 | return retval; | |
794 | } | |
795 | ||
796 | /* | |
797 | * Free and unmap PCI Resource | |
798 | */ | |
799 | static void tsi148_free_resource(struct vme_master_resource *image) | |
800 | { | |
801 | iounmap(image->kern_base); | |
802 | image->kern_base = NULL; | |
886953e9 | 803 | release_resource(&image->bus_resource); |
8fafb476 | 804 | kfree(image->bus_resource.name); |
886953e9 | 805 | memset(&image->bus_resource, 0, sizeof(struct resource)); |
d22b8ed9 MW |
806 | } |
807 | ||
808 | /* | |
809 | * Set the attributes of an outbound window. | |
810 | */ | |
5ade6c4d | 811 | static int tsi148_master_set(struct vme_master_resource *image, int enabled, |
6af04b06 MW |
812 | unsigned long long vme_base, unsigned long long size, u32 aspace, |
813 | u32 cycle, u32 dwidth) | |
d22b8ed9 MW |
814 | { |
815 | int retval = 0; | |
816 | unsigned int i; | |
817 | unsigned int temp_ctl = 0; | |
818 | unsigned int pci_base_low, pci_base_high; | |
819 | unsigned int pci_bound_low, pci_bound_high; | |
820 | unsigned int vme_offset_low, vme_offset_high; | |
821 | unsigned long long pci_bound, vme_offset, pci_base; | |
48d9356e | 822 | struct vme_bridge *tsi148_bridge; |
29848ac9 | 823 | struct tsi148_driver *bridge; |
226572b1 JS |
824 | struct pci_bus_region region; |
825 | struct pci_dev *pdev; | |
29848ac9 | 826 | |
48d9356e MW |
827 | tsi148_bridge = image->parent; |
828 | ||
829 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 830 | |
177581fa | 831 | pdev = to_pci_dev(tsi148_bridge->parent); |
226572b1 | 832 | |
d22b8ed9 MW |
833 | /* Verify input data */ |
834 | if (vme_base & 0xFFFF) { | |
48d9356e MW |
835 | dev_err(tsi148_bridge->parent, "Invalid VME Window " |
836 | "alignment\n"); | |
d22b8ed9 MW |
837 | retval = -EINVAL; |
838 | goto err_window; | |
839 | } | |
59c22904 MW |
840 | |
841 | if ((size == 0) && (enabled != 0)) { | |
48d9356e MW |
842 | dev_err(tsi148_bridge->parent, "Size must be non-zero for " |
843 | "enabled windows\n"); | |
d22b8ed9 MW |
844 | retval = -EINVAL; |
845 | goto err_window; | |
846 | } | |
847 | ||
886953e9 | 848 | spin_lock(&image->lock); |
d22b8ed9 MW |
849 | |
850 | /* Let's allocate the resource here rather than further up the stack as | |
25985edc | 851 | * it avoids pushing loads of bus dependent stuff up the stack. If size |
59c22904 | 852 | * is zero, any existing resource will be freed. |
d22b8ed9 MW |
853 | */ |
854 | retval = tsi148_alloc_resource(image, size); | |
855 | if (retval) { | |
886953e9 | 856 | spin_unlock(&image->lock); |
48d9356e | 857 | dev_err(tsi148_bridge->parent, "Unable to allocate memory for " |
59c22904 | 858 | "resource\n"); |
d22b8ed9 MW |
859 | goto err_res; |
860 | } | |
861 | ||
59c22904 MW |
862 | if (size == 0) { |
863 | pci_base = 0; | |
864 | pci_bound = 0; | |
865 | vme_offset = 0; | |
866 | } else { | |
226572b1 JS |
867 | pcibios_resource_to_bus(pdev->bus, ®ion, |
868 | &image->bus_resource); | |
869 | pci_base = region.start; | |
59c22904 MW |
870 | |
871 | /* | |
872 | * Bound address is a valid address for the window, adjust | |
873 | * according to window granularity. | |
874 | */ | |
875 | pci_bound = pci_base + (size - 0x10000); | |
876 | vme_offset = vme_base - pci_base; | |
877 | } | |
d22b8ed9 MW |
878 | |
879 | /* Convert 64-bit variables to 2x 32-bit variables */ | |
880 | reg_split(pci_base, &pci_base_high, &pci_base_low); | |
881 | reg_split(pci_bound, &pci_bound_high, &pci_bound_low); | |
882 | reg_split(vme_offset, &vme_offset_high, &vme_offset_low); | |
883 | ||
884 | if (pci_base_low & 0xFFFF) { | |
886953e9 | 885 | spin_unlock(&image->lock); |
48d9356e | 886 | dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n"); |
d22b8ed9 MW |
887 | retval = -EINVAL; |
888 | goto err_gran; | |
889 | } | |
890 | if (pci_bound_low & 0xFFFF) { | |
886953e9 | 891 | spin_unlock(&image->lock); |
48d9356e | 892 | dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n"); |
d22b8ed9 MW |
893 | retval = -EINVAL; |
894 | goto err_gran; | |
895 | } | |
896 | if (vme_offset_low & 0xFFFF) { | |
886953e9 | 897 | spin_unlock(&image->lock); |
48d9356e MW |
898 | dev_err(tsi148_bridge->parent, "Invalid VME Offset " |
899 | "alignment\n"); | |
d22b8ed9 MW |
900 | retval = -EINVAL; |
901 | goto err_gran; | |
902 | } | |
903 | ||
904 | i = image->number; | |
905 | ||
906 | /* Disable while we are mucking around */ | |
29848ac9 | 907 | temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
908 | TSI148_LCSR_OFFSET_OTAT); |
909 | temp_ctl &= ~TSI148_LCSR_OTAT_EN; | |
29848ac9 | 910 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
911 | TSI148_LCSR_OFFSET_OTAT); |
912 | ||
d22b8ed9 MW |
913 | /* Setup 2eSST speeds */ |
914 | temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M; | |
915 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { | |
916 | case VME_2eSST160: | |
917 | temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160; | |
918 | break; | |
919 | case VME_2eSST267: | |
920 | temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267; | |
921 | break; | |
922 | case VME_2eSST320: | |
923 | temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320; | |
924 | break; | |
925 | } | |
926 | ||
927 | /* Setup cycle types */ | |
928 | if (cycle & VME_BLT) { | |
929 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; | |
930 | temp_ctl |= TSI148_LCSR_OTAT_TM_BLT; | |
931 | } | |
932 | if (cycle & VME_MBLT) { | |
933 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; | |
934 | temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT; | |
935 | } | |
936 | if (cycle & VME_2eVME) { | |
937 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; | |
938 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME; | |
939 | } | |
940 | if (cycle & VME_2eSST) { | |
941 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; | |
942 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST; | |
943 | } | |
944 | if (cycle & VME_2eSSTB) { | |
48d9356e MW |
945 | dev_warn(tsi148_bridge->parent, "Currently not setting " |
946 | "Broadcast Select Registers\n"); | |
d22b8ed9 MW |
947 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; |
948 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB; | |
949 | } | |
950 | ||
951 | /* Setup data width */ | |
952 | temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M; | |
953 | switch (dwidth) { | |
954 | case VME_D16: | |
955 | temp_ctl |= TSI148_LCSR_OTAT_DBW_16; | |
956 | break; | |
957 | case VME_D32: | |
958 | temp_ctl |= TSI148_LCSR_OTAT_DBW_32; | |
959 | break; | |
960 | default: | |
886953e9 | 961 | spin_unlock(&image->lock); |
48d9356e | 962 | dev_err(tsi148_bridge->parent, "Invalid data width\n"); |
d22b8ed9 MW |
963 | retval = -EINVAL; |
964 | goto err_dwidth; | |
965 | } | |
966 | ||
967 | /* Setup address space */ | |
968 | temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M; | |
969 | switch (aspace) { | |
970 | case VME_A16: | |
971 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16; | |
972 | break; | |
973 | case VME_A24: | |
974 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24; | |
975 | break; | |
976 | case VME_A32: | |
977 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32; | |
978 | break; | |
979 | case VME_A64: | |
980 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64; | |
981 | break; | |
982 | case VME_CRCSR: | |
983 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR; | |
984 | break; | |
985 | case VME_USER1: | |
986 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1; | |
987 | break; | |
988 | case VME_USER2: | |
989 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2; | |
990 | break; | |
991 | case VME_USER3: | |
992 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3; | |
993 | break; | |
994 | case VME_USER4: | |
995 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4; | |
996 | break; | |
997 | default: | |
886953e9 | 998 | spin_unlock(&image->lock); |
48d9356e | 999 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
d22b8ed9 MW |
1000 | retval = -EINVAL; |
1001 | goto err_aspace; | |
1002 | break; | |
1003 | } | |
1004 | ||
1005 | temp_ctl &= ~(3<<4); | |
1006 | if (cycle & VME_SUPER) | |
1007 | temp_ctl |= TSI148_LCSR_OTAT_SUP; | |
1008 | if (cycle & VME_PROG) | |
1009 | temp_ctl |= TSI148_LCSR_OTAT_PGM; | |
1010 | ||
1011 | /* Setup mapping */ | |
29848ac9 | 1012 | iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1013 | TSI148_LCSR_OFFSET_OTSAU); |
29848ac9 | 1014 | iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1015 | TSI148_LCSR_OFFSET_OTSAL); |
29848ac9 | 1016 | iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1017 | TSI148_LCSR_OFFSET_OTEAU); |
29848ac9 | 1018 | iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1019 | TSI148_LCSR_OFFSET_OTEAL); |
29848ac9 | 1020 | iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1021 | TSI148_LCSR_OFFSET_OTOFU); |
29848ac9 | 1022 | iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1023 | TSI148_LCSR_OFFSET_OTOFL); |
1024 | ||
d22b8ed9 | 1025 | /* Write ctl reg without enable */ |
29848ac9 | 1026 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1027 | TSI148_LCSR_OFFSET_OTAT); |
1028 | ||
1029 | if (enabled) | |
1030 | temp_ctl |= TSI148_LCSR_OTAT_EN; | |
1031 | ||
29848ac9 | 1032 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1033 | TSI148_LCSR_OFFSET_OTAT); |
1034 | ||
886953e9 | 1035 | spin_unlock(&image->lock); |
d22b8ed9 MW |
1036 | return 0; |
1037 | ||
1038 | err_aspace: | |
1039 | err_dwidth: | |
1040 | err_gran: | |
1041 | tsi148_free_resource(image); | |
1042 | err_res: | |
1043 | err_window: | |
1044 | return retval; | |
1045 | ||
1046 | } | |
1047 | ||
1048 | /* | |
1049 | * Set the attributes of an outbound window. | |
1050 | * | |
1051 | * XXX Not parsing prefetch information. | |
1052 | */ | |
5ade6c4d | 1053 | static int __tsi148_master_get(struct vme_master_resource *image, int *enabled, |
6af04b06 MW |
1054 | unsigned long long *vme_base, unsigned long long *size, u32 *aspace, |
1055 | u32 *cycle, u32 *dwidth) | |
d22b8ed9 MW |
1056 | { |
1057 | unsigned int i, ctl; | |
1058 | unsigned int pci_base_low, pci_base_high; | |
1059 | unsigned int pci_bound_low, pci_bound_high; | |
1060 | unsigned int vme_offset_low, vme_offset_high; | |
1061 | ||
1062 | unsigned long long pci_base, pci_bound, vme_offset; | |
29848ac9 MW |
1063 | struct tsi148_driver *bridge; |
1064 | ||
1065 | bridge = image->parent->driver_priv; | |
d22b8ed9 MW |
1066 | |
1067 | i = image->number; | |
1068 | ||
29848ac9 | 1069 | ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1070 | TSI148_LCSR_OFFSET_OTAT); |
1071 | ||
29848ac9 | 1072 | pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1073 | TSI148_LCSR_OFFSET_OTSAU); |
29848ac9 | 1074 | pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1075 | TSI148_LCSR_OFFSET_OTSAL); |
29848ac9 | 1076 | pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1077 | TSI148_LCSR_OFFSET_OTEAU); |
29848ac9 | 1078 | pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1079 | TSI148_LCSR_OFFSET_OTEAL); |
29848ac9 | 1080 | vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1081 | TSI148_LCSR_OFFSET_OTOFU); |
29848ac9 | 1082 | vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1083 | TSI148_LCSR_OFFSET_OTOFL); |
1084 | ||
1085 | /* Convert 64-bit variables to 2x 32-bit variables */ | |
1086 | reg_join(pci_base_high, pci_base_low, &pci_base); | |
1087 | reg_join(pci_bound_high, pci_bound_low, &pci_bound); | |
1088 | reg_join(vme_offset_high, vme_offset_low, &vme_offset); | |
1089 | ||
1090 | *vme_base = pci_base + vme_offset; | |
1091 | *size = (unsigned long long)(pci_bound - pci_base) + 0x10000; | |
1092 | ||
1093 | *enabled = 0; | |
1094 | *aspace = 0; | |
1095 | *cycle = 0; | |
1096 | *dwidth = 0; | |
1097 | ||
1098 | if (ctl & TSI148_LCSR_OTAT_EN) | |
1099 | *enabled = 1; | |
1100 | ||
1101 | /* Setup address space */ | |
1102 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16) | |
1103 | *aspace |= VME_A16; | |
1104 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24) | |
1105 | *aspace |= VME_A24; | |
1106 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32) | |
1107 | *aspace |= VME_A32; | |
1108 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64) | |
1109 | *aspace |= VME_A64; | |
1110 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR) | |
1111 | *aspace |= VME_CRCSR; | |
1112 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1) | |
1113 | *aspace |= VME_USER1; | |
1114 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2) | |
1115 | *aspace |= VME_USER2; | |
1116 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3) | |
1117 | *aspace |= VME_USER3; | |
1118 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4) | |
1119 | *aspace |= VME_USER4; | |
1120 | ||
1121 | /* Setup 2eSST speeds */ | |
1122 | if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160) | |
1123 | *cycle |= VME_2eSST160; | |
1124 | if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267) | |
1125 | *cycle |= VME_2eSST267; | |
1126 | if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320) | |
1127 | *cycle |= VME_2eSST320; | |
1128 | ||
1129 | /* Setup cycle types */ | |
7946328f | 1130 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT) |
d22b8ed9 | 1131 | *cycle |= VME_SCT; |
7946328f | 1132 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT) |
d22b8ed9 | 1133 | *cycle |= VME_BLT; |
7946328f | 1134 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT) |
d22b8ed9 | 1135 | *cycle |= VME_MBLT; |
7946328f | 1136 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME) |
d22b8ed9 | 1137 | *cycle |= VME_2eVME; |
7946328f | 1138 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST) |
d22b8ed9 | 1139 | *cycle |= VME_2eSST; |
7946328f | 1140 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB) |
d22b8ed9 MW |
1141 | *cycle |= VME_2eSSTB; |
1142 | ||
1143 | if (ctl & TSI148_LCSR_OTAT_SUP) | |
1144 | *cycle |= VME_SUPER; | |
1145 | else | |
1146 | *cycle |= VME_USER; | |
1147 | ||
1148 | if (ctl & TSI148_LCSR_OTAT_PGM) | |
1149 | *cycle |= VME_PROG; | |
1150 | else | |
1151 | *cycle |= VME_DATA; | |
1152 | ||
1153 | /* Setup data width */ | |
1154 | if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16) | |
1155 | *dwidth = VME_D16; | |
1156 | if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32) | |
1157 | *dwidth = VME_D32; | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | ||
5ade6c4d | 1163 | static int tsi148_master_get(struct vme_master_resource *image, int *enabled, |
6af04b06 MW |
1164 | unsigned long long *vme_base, unsigned long long *size, u32 *aspace, |
1165 | u32 *cycle, u32 *dwidth) | |
d22b8ed9 MW |
1166 | { |
1167 | int retval; | |
1168 | ||
886953e9 | 1169 | spin_lock(&image->lock); |
d22b8ed9 MW |
1170 | |
1171 | retval = __tsi148_master_get(image, enabled, vme_base, size, aspace, | |
1172 | cycle, dwidth); | |
1173 | ||
886953e9 | 1174 | spin_unlock(&image->lock); |
d22b8ed9 MW |
1175 | |
1176 | return retval; | |
1177 | } | |
1178 | ||
5ade6c4d | 1179 | static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf, |
d22b8ed9 MW |
1180 | size_t count, loff_t offset) |
1181 | { | |
1182 | int retval, enabled; | |
1183 | unsigned long long vme_base, size; | |
6af04b06 | 1184 | u32 aspace, cycle, dwidth; |
d3337eb1 | 1185 | struct vme_error_handler *handler = NULL; |
29848ac9 | 1186 | struct vme_bridge *tsi148_bridge; |
4e8764d9 | 1187 | void __iomem *addr = image->kern_base + offset; |
363e2e6f MW |
1188 | unsigned int done = 0; |
1189 | unsigned int count32; | |
29848ac9 MW |
1190 | |
1191 | tsi148_bridge = image->parent; | |
d22b8ed9 | 1192 | |
886953e9 | 1193 | spin_lock(&image->lock); |
d22b8ed9 | 1194 | |
0b049662 DK |
1195 | if (err_chk) { |
1196 | __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, | |
1197 | &cycle, &dwidth); | |
1198 | handler = vme_register_error_handler(tsi148_bridge, aspace, | |
1199 | vme_base + offset, count); | |
1200 | if (!handler) { | |
1201 | spin_unlock(&image->lock); | |
1202 | return -ENOMEM; | |
1203 | } | |
1204 | } | |
1205 | ||
363e2e6f | 1206 | /* The following code handles VME address alignment. We cannot use |
a2a720e1 MW |
1207 | * memcpy_xxx here because it may cut data transfers in to 8-bit |
1208 | * cycles when D16 or D32 cycles are required on the VME bus. | |
363e2e6f MW |
1209 | * On the other hand, the bridge itself assures that the maximum data |
1210 | * cycle configured for the transfer is used and splits it | |
1211 | * automatically for non-aligned addresses, so we don't want the | |
1212 | * overhead of needlessly forcing small transfers for the entire cycle. | |
1213 | */ | |
1214 | if ((uintptr_t)addr & 0x1) { | |
1215 | *(u8 *)buf = ioread8(addr); | |
1216 | done += 1; | |
1217 | if (done == count) | |
1218 | goto out; | |
1219 | } | |
f0342e66 | 1220 | if ((uintptr_t)(addr + done) & 0x2) { |
363e2e6f MW |
1221 | if ((count - done) < 2) { |
1222 | *(u8 *)(buf + done) = ioread8(addr + done); | |
1223 | done += 1; | |
1224 | goto out; | |
1225 | } else { | |
1226 | *(u16 *)(buf + done) = ioread16(addr + done); | |
1227 | done += 2; | |
1228 | } | |
1229 | } | |
1230 | ||
1231 | count32 = (count - done) & ~0x3; | |
a2a720e1 MW |
1232 | while (done < count32) { |
1233 | *(u32 *)(buf + done) = ioread32(addr + done); | |
1234 | done += 4; | |
363e2e6f MW |
1235 | } |
1236 | ||
1237 | if ((count - done) & 0x2) { | |
1238 | *(u16 *)(buf + done) = ioread16(addr + done); | |
1239 | done += 2; | |
1240 | } | |
1241 | if ((count - done) & 0x1) { | |
1242 | *(u8 *)(buf + done) = ioread8(addr + done); | |
1243 | done += 1; | |
1244 | } | |
1245 | ||
1246 | out: | |
d22b8ed9 MW |
1247 | retval = count; |
1248 | ||
0b049662 DK |
1249 | if (err_chk) { |
1250 | if (handler->num_errors) { | |
1251 | dev_err(image->parent->parent, | |
1252 | "First VME read error detected an at address 0x%llx\n", | |
1253 | handler->first_error); | |
1254 | retval = handler->first_error - (vme_base + offset); | |
1255 | } | |
1256 | vme_unregister_error_handler(handler); | |
d22b8ed9 MW |
1257 | } |
1258 | ||
886953e9 | 1259 | spin_unlock(&image->lock); |
d22b8ed9 MW |
1260 | |
1261 | return retval; | |
1262 | } | |
1263 | ||
1264 | ||
5ade6c4d | 1265 | static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, |
d22b8ed9 MW |
1266 | size_t count, loff_t offset) |
1267 | { | |
1268 | int retval = 0, enabled; | |
1269 | unsigned long long vme_base, size; | |
6af04b06 | 1270 | u32 aspace, cycle, dwidth; |
4e8764d9 | 1271 | void __iomem *addr = image->kern_base + offset; |
363e2e6f MW |
1272 | unsigned int done = 0; |
1273 | unsigned int count32; | |
d22b8ed9 | 1274 | |
d3337eb1 | 1275 | struct vme_error_handler *handler = NULL; |
29848ac9 MW |
1276 | struct vme_bridge *tsi148_bridge; |
1277 | struct tsi148_driver *bridge; | |
1278 | ||
1279 | tsi148_bridge = image->parent; | |
1280 | ||
1281 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 1282 | |
886953e9 | 1283 | spin_lock(&image->lock); |
d22b8ed9 | 1284 | |
0b049662 DK |
1285 | if (err_chk) { |
1286 | __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, | |
1287 | &cycle, &dwidth); | |
1288 | handler = vme_register_error_handler(tsi148_bridge, aspace, | |
1289 | vme_base + offset, count); | |
1290 | if (!handler) { | |
1291 | spin_unlock(&image->lock); | |
1292 | return -ENOMEM; | |
1293 | } | |
1294 | } | |
1295 | ||
363e2e6f | 1296 | /* Here we apply for the same strategy we do in master_read |
a2a720e1 | 1297 | * function in order to assure the correct cycles. |
363e2e6f MW |
1298 | */ |
1299 | if ((uintptr_t)addr & 0x1) { | |
1300 | iowrite8(*(u8 *)buf, addr); | |
1301 | done += 1; | |
1302 | if (done == count) | |
1303 | goto out; | |
1304 | } | |
f0342e66 | 1305 | if ((uintptr_t)(addr + done) & 0x2) { |
363e2e6f MW |
1306 | if ((count - done) < 2) { |
1307 | iowrite8(*(u8 *)(buf + done), addr + done); | |
1308 | done += 1; | |
1309 | goto out; | |
1310 | } else { | |
1311 | iowrite16(*(u16 *)(buf + done), addr + done); | |
1312 | done += 2; | |
1313 | } | |
1314 | } | |
1315 | ||
1316 | count32 = (count - done) & ~0x3; | |
a2a720e1 MW |
1317 | while (done < count32) { |
1318 | iowrite32(*(u32 *)(buf + done), addr + done); | |
1319 | done += 4; | |
363e2e6f MW |
1320 | } |
1321 | ||
1322 | if ((count - done) & 0x2) { | |
1323 | iowrite16(*(u16 *)(buf + done), addr + done); | |
1324 | done += 2; | |
1325 | } | |
1326 | if ((count - done) & 0x1) { | |
1327 | iowrite8(*(u8 *)(buf + done), addr + done); | |
1328 | done += 1; | |
1329 | } | |
1330 | ||
1331 | out: | |
d22b8ed9 MW |
1332 | retval = count; |
1333 | ||
1334 | /* | |
1335 | * Writes are posted. We need to do a read on the VME bus to flush out | |
25985edc | 1336 | * all of the writes before we check for errors. We can't guarantee |
d22b8ed9 MW |
1337 | * that reading the data we have just written is safe. It is believed |
1338 | * that there isn't any read, write re-ordering, so we can read any | |
1339 | * location in VME space, so lets read the Device ID from the tsi148's | |
1340 | * own registers as mapped into CR/CSR space. | |
1341 | * | |
1342 | * We check for saved errors in the written address range/space. | |
1343 | */ | |
1344 | ||
0b049662 DK |
1345 | if (err_chk) { |
1346 | ioread16(bridge->flush_image->kern_base + 0x7F000); | |
d22b8ed9 | 1347 | |
0b049662 DK |
1348 | if (handler->num_errors) { |
1349 | dev_warn(tsi148_bridge->parent, | |
1350 | "First VME write error detected an at address 0x%llx\n", | |
1351 | handler->first_error); | |
1352 | retval = handler->first_error - (vme_base + offset); | |
1353 | } | |
1354 | vme_unregister_error_handler(handler); | |
d22b8ed9 MW |
1355 | } |
1356 | ||
886953e9 | 1357 | spin_unlock(&image->lock); |
d22b8ed9 MW |
1358 | |
1359 | return retval; | |
1360 | } | |
1361 | ||
1362 | /* | |
1363 | * Perform an RMW cycle on the VME bus. | |
1364 | * | |
1365 | * Requires a previously configured master window, returns final value. | |
1366 | */ | |
5ade6c4d | 1367 | static unsigned int tsi148_master_rmw(struct vme_master_resource *image, |
d22b8ed9 MW |
1368 | unsigned int mask, unsigned int compare, unsigned int swap, |
1369 | loff_t offset) | |
1370 | { | |
1371 | unsigned long long pci_addr; | |
1372 | unsigned int pci_addr_high, pci_addr_low; | |
1373 | u32 tmp, result; | |
1374 | int i; | |
29848ac9 | 1375 | struct tsi148_driver *bridge; |
d22b8ed9 | 1376 | |
29848ac9 | 1377 | bridge = image->parent->driver_priv; |
d22b8ed9 MW |
1378 | |
1379 | /* Find the PCI address that maps to the desired VME address */ | |
1380 | i = image->number; | |
1381 | ||
1382 | /* Locking as we can only do one of these at a time */ | |
886953e9 | 1383 | mutex_lock(&bridge->vme_rmw); |
d22b8ed9 MW |
1384 | |
1385 | /* Lock image */ | |
886953e9 | 1386 | spin_lock(&image->lock); |
d22b8ed9 | 1387 | |
29848ac9 | 1388 | pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1389 | TSI148_LCSR_OFFSET_OTSAU); |
29848ac9 | 1390 | pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1391 | TSI148_LCSR_OFFSET_OTSAL); |
1392 | ||
1393 | reg_join(pci_addr_high, pci_addr_low, &pci_addr); | |
1394 | reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low); | |
1395 | ||
1396 | /* Configure registers */ | |
29848ac9 MW |
1397 | iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN); |
1398 | iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC); | |
1399 | iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS); | |
1400 | iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU); | |
1401 | iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL); | |
d22b8ed9 MW |
1402 | |
1403 | /* Enable RMW */ | |
29848ac9 | 1404 | tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); |
d22b8ed9 | 1405 | tmp |= TSI148_LCSR_VMCTRL_RMWEN; |
29848ac9 | 1406 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); |
d22b8ed9 MW |
1407 | |
1408 | /* Kick process off with a read to the required address. */ | |
1409 | result = ioread32be(image->kern_base + offset); | |
1410 | ||
1411 | /* Disable RMW */ | |
29848ac9 | 1412 | tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); |
d22b8ed9 | 1413 | tmp &= ~TSI148_LCSR_VMCTRL_RMWEN; |
29848ac9 | 1414 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); |
d22b8ed9 | 1415 | |
886953e9 | 1416 | spin_unlock(&image->lock); |
d22b8ed9 | 1417 | |
886953e9 | 1418 | mutex_unlock(&bridge->vme_rmw); |
d22b8ed9 MW |
1419 | |
1420 | return result; | |
1421 | } | |
1422 | ||
ac1a4f2c | 1423 | static int tsi148_dma_set_vme_src_attributes(struct device *dev, __be32 *attr, |
6af04b06 | 1424 | u32 aspace, u32 cycle, u32 dwidth) |
d22b8ed9 | 1425 | { |
ac1a4f2c MW |
1426 | u32 val; |
1427 | ||
1428 | val = be32_to_cpu(*attr); | |
1429 | ||
d22b8ed9 MW |
1430 | /* Setup 2eSST speeds */ |
1431 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { | |
1432 | case VME_2eSST160: | |
ac1a4f2c | 1433 | val |= TSI148_LCSR_DSAT_2eSSTM_160; |
d22b8ed9 MW |
1434 | break; |
1435 | case VME_2eSST267: | |
ac1a4f2c | 1436 | val |= TSI148_LCSR_DSAT_2eSSTM_267; |
d22b8ed9 MW |
1437 | break; |
1438 | case VME_2eSST320: | |
ac1a4f2c | 1439 | val |= TSI148_LCSR_DSAT_2eSSTM_320; |
d22b8ed9 MW |
1440 | break; |
1441 | } | |
1442 | ||
1443 | /* Setup cycle types */ | |
7946328f | 1444 | if (cycle & VME_SCT) |
ac1a4f2c | 1445 | val |= TSI148_LCSR_DSAT_TM_SCT; |
7946328f MW |
1446 | |
1447 | if (cycle & VME_BLT) | |
ac1a4f2c | 1448 | val |= TSI148_LCSR_DSAT_TM_BLT; |
7946328f MW |
1449 | |
1450 | if (cycle & VME_MBLT) | |
ac1a4f2c | 1451 | val |= TSI148_LCSR_DSAT_TM_MBLT; |
7946328f MW |
1452 | |
1453 | if (cycle & VME_2eVME) | |
ac1a4f2c | 1454 | val |= TSI148_LCSR_DSAT_TM_2eVME; |
7946328f MW |
1455 | |
1456 | if (cycle & VME_2eSST) | |
ac1a4f2c | 1457 | val |= TSI148_LCSR_DSAT_TM_2eSST; |
7946328f | 1458 | |
d22b8ed9 | 1459 | if (cycle & VME_2eSSTB) { |
48d9356e MW |
1460 | dev_err(dev, "Currently not setting Broadcast Select " |
1461 | "Registers\n"); | |
ac1a4f2c | 1462 | val |= TSI148_LCSR_DSAT_TM_2eSSTB; |
d22b8ed9 MW |
1463 | } |
1464 | ||
1465 | /* Setup data width */ | |
1466 | switch (dwidth) { | |
1467 | case VME_D16: | |
ac1a4f2c | 1468 | val |= TSI148_LCSR_DSAT_DBW_16; |
d22b8ed9 MW |
1469 | break; |
1470 | case VME_D32: | |
ac1a4f2c | 1471 | val |= TSI148_LCSR_DSAT_DBW_32; |
d22b8ed9 MW |
1472 | break; |
1473 | default: | |
48d9356e | 1474 | dev_err(dev, "Invalid data width\n"); |
d22b8ed9 MW |
1475 | return -EINVAL; |
1476 | } | |
1477 | ||
1478 | /* Setup address space */ | |
1479 | switch (aspace) { | |
1480 | case VME_A16: | |
ac1a4f2c | 1481 | val |= TSI148_LCSR_DSAT_AMODE_A16; |
d22b8ed9 MW |
1482 | break; |
1483 | case VME_A24: | |
ac1a4f2c | 1484 | val |= TSI148_LCSR_DSAT_AMODE_A24; |
d22b8ed9 MW |
1485 | break; |
1486 | case VME_A32: | |
ac1a4f2c | 1487 | val |= TSI148_LCSR_DSAT_AMODE_A32; |
d22b8ed9 MW |
1488 | break; |
1489 | case VME_A64: | |
ac1a4f2c | 1490 | val |= TSI148_LCSR_DSAT_AMODE_A64; |
d22b8ed9 MW |
1491 | break; |
1492 | case VME_CRCSR: | |
ac1a4f2c | 1493 | val |= TSI148_LCSR_DSAT_AMODE_CRCSR; |
d22b8ed9 MW |
1494 | break; |
1495 | case VME_USER1: | |
ac1a4f2c | 1496 | val |= TSI148_LCSR_DSAT_AMODE_USER1; |
d22b8ed9 MW |
1497 | break; |
1498 | case VME_USER2: | |
ac1a4f2c | 1499 | val |= TSI148_LCSR_DSAT_AMODE_USER2; |
d22b8ed9 MW |
1500 | break; |
1501 | case VME_USER3: | |
ac1a4f2c | 1502 | val |= TSI148_LCSR_DSAT_AMODE_USER3; |
d22b8ed9 MW |
1503 | break; |
1504 | case VME_USER4: | |
ac1a4f2c | 1505 | val |= TSI148_LCSR_DSAT_AMODE_USER4; |
d22b8ed9 MW |
1506 | break; |
1507 | default: | |
48d9356e | 1508 | dev_err(dev, "Invalid address space\n"); |
d22b8ed9 MW |
1509 | return -EINVAL; |
1510 | break; | |
1511 | } | |
1512 | ||
1513 | if (cycle & VME_SUPER) | |
ac1a4f2c | 1514 | val |= TSI148_LCSR_DSAT_SUP; |
d22b8ed9 | 1515 | if (cycle & VME_PROG) |
ac1a4f2c MW |
1516 | val |= TSI148_LCSR_DSAT_PGM; |
1517 | ||
1518 | *attr = cpu_to_be32(val); | |
d22b8ed9 MW |
1519 | |
1520 | return 0; | |
1521 | } | |
1522 | ||
ac1a4f2c | 1523 | static int tsi148_dma_set_vme_dest_attributes(struct device *dev, __be32 *attr, |
6af04b06 | 1524 | u32 aspace, u32 cycle, u32 dwidth) |
d22b8ed9 | 1525 | { |
ac1a4f2c MW |
1526 | u32 val; |
1527 | ||
1528 | val = be32_to_cpu(*attr); | |
1529 | ||
d22b8ed9 MW |
1530 | /* Setup 2eSST speeds */ |
1531 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { | |
1532 | case VME_2eSST160: | |
ac1a4f2c | 1533 | val |= TSI148_LCSR_DDAT_2eSSTM_160; |
d22b8ed9 MW |
1534 | break; |
1535 | case VME_2eSST267: | |
ac1a4f2c | 1536 | val |= TSI148_LCSR_DDAT_2eSSTM_267; |
d22b8ed9 MW |
1537 | break; |
1538 | case VME_2eSST320: | |
ac1a4f2c | 1539 | val |= TSI148_LCSR_DDAT_2eSSTM_320; |
d22b8ed9 MW |
1540 | break; |
1541 | } | |
1542 | ||
1543 | /* Setup cycle types */ | |
7946328f | 1544 | if (cycle & VME_SCT) |
ac1a4f2c | 1545 | val |= TSI148_LCSR_DDAT_TM_SCT; |
7946328f MW |
1546 | |
1547 | if (cycle & VME_BLT) | |
ac1a4f2c | 1548 | val |= TSI148_LCSR_DDAT_TM_BLT; |
7946328f MW |
1549 | |
1550 | if (cycle & VME_MBLT) | |
ac1a4f2c | 1551 | val |= TSI148_LCSR_DDAT_TM_MBLT; |
7946328f MW |
1552 | |
1553 | if (cycle & VME_2eVME) | |
ac1a4f2c | 1554 | val |= TSI148_LCSR_DDAT_TM_2eVME; |
7946328f MW |
1555 | |
1556 | if (cycle & VME_2eSST) | |
ac1a4f2c | 1557 | val |= TSI148_LCSR_DDAT_TM_2eSST; |
7946328f | 1558 | |
d22b8ed9 | 1559 | if (cycle & VME_2eSSTB) { |
48d9356e MW |
1560 | dev_err(dev, "Currently not setting Broadcast Select " |
1561 | "Registers\n"); | |
ac1a4f2c | 1562 | val |= TSI148_LCSR_DDAT_TM_2eSSTB; |
d22b8ed9 MW |
1563 | } |
1564 | ||
1565 | /* Setup data width */ | |
1566 | switch (dwidth) { | |
1567 | case VME_D16: | |
ac1a4f2c | 1568 | val |= TSI148_LCSR_DDAT_DBW_16; |
d22b8ed9 MW |
1569 | break; |
1570 | case VME_D32: | |
ac1a4f2c | 1571 | val |= TSI148_LCSR_DDAT_DBW_32; |
d22b8ed9 MW |
1572 | break; |
1573 | default: | |
48d9356e | 1574 | dev_err(dev, "Invalid data width\n"); |
d22b8ed9 MW |
1575 | return -EINVAL; |
1576 | } | |
1577 | ||
1578 | /* Setup address space */ | |
1579 | switch (aspace) { | |
1580 | case VME_A16: | |
ac1a4f2c | 1581 | val |= TSI148_LCSR_DDAT_AMODE_A16; |
d22b8ed9 MW |
1582 | break; |
1583 | case VME_A24: | |
ac1a4f2c | 1584 | val |= TSI148_LCSR_DDAT_AMODE_A24; |
d22b8ed9 MW |
1585 | break; |
1586 | case VME_A32: | |
ac1a4f2c | 1587 | val |= TSI148_LCSR_DDAT_AMODE_A32; |
d22b8ed9 MW |
1588 | break; |
1589 | case VME_A64: | |
ac1a4f2c | 1590 | val |= TSI148_LCSR_DDAT_AMODE_A64; |
d22b8ed9 MW |
1591 | break; |
1592 | case VME_CRCSR: | |
ac1a4f2c | 1593 | val |= TSI148_LCSR_DDAT_AMODE_CRCSR; |
d22b8ed9 MW |
1594 | break; |
1595 | case VME_USER1: | |
ac1a4f2c | 1596 | val |= TSI148_LCSR_DDAT_AMODE_USER1; |
d22b8ed9 MW |
1597 | break; |
1598 | case VME_USER2: | |
ac1a4f2c | 1599 | val |= TSI148_LCSR_DDAT_AMODE_USER2; |
d22b8ed9 MW |
1600 | break; |
1601 | case VME_USER3: | |
ac1a4f2c | 1602 | val |= TSI148_LCSR_DDAT_AMODE_USER3; |
d22b8ed9 MW |
1603 | break; |
1604 | case VME_USER4: | |
ac1a4f2c | 1605 | val |= TSI148_LCSR_DDAT_AMODE_USER4; |
d22b8ed9 MW |
1606 | break; |
1607 | default: | |
48d9356e | 1608 | dev_err(dev, "Invalid address space\n"); |
d22b8ed9 MW |
1609 | return -EINVAL; |
1610 | break; | |
1611 | } | |
1612 | ||
1613 | if (cycle & VME_SUPER) | |
ac1a4f2c | 1614 | val |= TSI148_LCSR_DDAT_SUP; |
d22b8ed9 | 1615 | if (cycle & VME_PROG) |
ac1a4f2c MW |
1616 | val |= TSI148_LCSR_DDAT_PGM; |
1617 | ||
1618 | *attr = cpu_to_be32(val); | |
d22b8ed9 MW |
1619 | |
1620 | return 0; | |
1621 | } | |
1622 | ||
1623 | /* | |
1624 | * Add a link list descriptor to the list | |
ac1a4f2c MW |
1625 | * |
1626 | * Note: DMA engine expects the DMA descriptor to be big endian. | |
d22b8ed9 | 1627 | */ |
5ade6c4d EC |
1628 | static int tsi148_dma_list_add(struct vme_dma_list *list, |
1629 | struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count) | |
d22b8ed9 MW |
1630 | { |
1631 | struct tsi148_dma_entry *entry, *prev; | |
ac1a4f2c | 1632 | u32 address_high, address_low, val; |
d22b8ed9 MW |
1633 | struct vme_dma_pattern *pattern_attr; |
1634 | struct vme_dma_pci *pci_attr; | |
1635 | struct vme_dma_vme *vme_attr; | |
d22b8ed9 | 1636 | int retval = 0; |
48d9356e MW |
1637 | struct vme_bridge *tsi148_bridge; |
1638 | ||
1639 | tsi148_bridge = list->parent->parent; | |
d22b8ed9 | 1640 | |
bb9ea89e | 1641 | /* Descriptor must be aligned on 64-bit boundaries */ |
7946328f | 1642 | entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL); |
d22b8ed9 | 1643 | if (entry == NULL) { |
48d9356e MW |
1644 | dev_err(tsi148_bridge->parent, "Failed to allocate memory for " |
1645 | "dma resource structure\n"); | |
d22b8ed9 MW |
1646 | retval = -ENOMEM; |
1647 | goto err_mem; | |
1648 | } | |
1649 | ||
1650 | /* Test descriptor alignment */ | |
886953e9 | 1651 | if ((unsigned long)&entry->descriptor & 0x7) { |
48d9356e MW |
1652 | dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 " |
1653 | "byte boundary as required: %p\n", | |
886953e9 | 1654 | &entry->descriptor); |
d22b8ed9 MW |
1655 | retval = -EINVAL; |
1656 | goto err_align; | |
1657 | } | |
1658 | ||
1659 | /* Given we are going to fill out the structure, we probably don't | |
1660 | * need to zero it, but better safe than sorry for now. | |
1661 | */ | |
886953e9 | 1662 | memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor)); |
d22b8ed9 MW |
1663 | |
1664 | /* Fill out source part */ | |
1665 | switch (src->type) { | |
1666 | case VME_DMA_PATTERN: | |
c4d82fbb | 1667 | pattern_attr = src->private; |
d22b8ed9 | 1668 | |
ac1a4f2c MW |
1669 | entry->descriptor.dsal = cpu_to_be32(pattern_attr->pattern); |
1670 | ||
1671 | val = TSI148_LCSR_DSAT_TYP_PAT; | |
1672 | ||
d22b8ed9 | 1673 | /* Default behaviour is 32 bit pattern */ |
7946328f | 1674 | if (pattern_attr->type & VME_DMA_PATTERN_BYTE) |
ac1a4f2c | 1675 | val |= TSI148_LCSR_DSAT_PSZ; |
7946328f | 1676 | |
d22b8ed9 | 1677 | /* It seems that the default behaviour is to increment */ |
7946328f | 1678 | if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) |
ac1a4f2c MW |
1679 | val |= TSI148_LCSR_DSAT_NIN; |
1680 | entry->descriptor.dsat = cpu_to_be32(val); | |
d22b8ed9 MW |
1681 | break; |
1682 | case VME_DMA_PCI: | |
c4d82fbb | 1683 | pci_attr = src->private; |
d22b8ed9 MW |
1684 | |
1685 | reg_split((unsigned long long)pci_attr->address, &address_high, | |
1686 | &address_low); | |
ac1a4f2c MW |
1687 | entry->descriptor.dsau = cpu_to_be32(address_high); |
1688 | entry->descriptor.dsal = cpu_to_be32(address_low); | |
1689 | entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_PCI); | |
d22b8ed9 MW |
1690 | break; |
1691 | case VME_DMA_VME: | |
c4d82fbb | 1692 | vme_attr = src->private; |
d22b8ed9 MW |
1693 | |
1694 | reg_split((unsigned long long)vme_attr->address, &address_high, | |
1695 | &address_low); | |
ac1a4f2c MW |
1696 | entry->descriptor.dsau = cpu_to_be32(address_high); |
1697 | entry->descriptor.dsal = cpu_to_be32(address_low); | |
1698 | entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_VME); | |
d22b8ed9 MW |
1699 | |
1700 | retval = tsi148_dma_set_vme_src_attributes( | |
886953e9 | 1701 | tsi148_bridge->parent, &entry->descriptor.dsat, |
48d9356e | 1702 | vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); |
7946328f | 1703 | if (retval < 0) |
d22b8ed9 MW |
1704 | goto err_source; |
1705 | break; | |
1706 | default: | |
48d9356e | 1707 | dev_err(tsi148_bridge->parent, "Invalid source type\n"); |
d22b8ed9 MW |
1708 | retval = -EINVAL; |
1709 | goto err_source; | |
1710 | break; | |
1711 | } | |
1712 | ||
1713 | /* Assume last link - this will be over-written by adding another */ | |
ac1a4f2c MW |
1714 | entry->descriptor.dnlau = cpu_to_be32(0); |
1715 | entry->descriptor.dnlal = cpu_to_be32(TSI148_LCSR_DNLAL_LLA); | |
d22b8ed9 MW |
1716 | |
1717 | /* Fill out destination part */ | |
1718 | switch (dest->type) { | |
1719 | case VME_DMA_PCI: | |
c4d82fbb | 1720 | pci_attr = dest->private; |
d22b8ed9 MW |
1721 | |
1722 | reg_split((unsigned long long)pci_attr->address, &address_high, | |
1723 | &address_low); | |
ac1a4f2c MW |
1724 | entry->descriptor.ddau = cpu_to_be32(address_high); |
1725 | entry->descriptor.ddal = cpu_to_be32(address_low); | |
1726 | entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_PCI); | |
d22b8ed9 MW |
1727 | break; |
1728 | case VME_DMA_VME: | |
c4d82fbb | 1729 | vme_attr = dest->private; |
d22b8ed9 MW |
1730 | |
1731 | reg_split((unsigned long long)vme_attr->address, &address_high, | |
1732 | &address_low); | |
ac1a4f2c MW |
1733 | entry->descriptor.ddau = cpu_to_be32(address_high); |
1734 | entry->descriptor.ddal = cpu_to_be32(address_low); | |
1735 | entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_VME); | |
d22b8ed9 MW |
1736 | |
1737 | retval = tsi148_dma_set_vme_dest_attributes( | |
886953e9 | 1738 | tsi148_bridge->parent, &entry->descriptor.ddat, |
48d9356e | 1739 | vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); |
7946328f | 1740 | if (retval < 0) |
d22b8ed9 MW |
1741 | goto err_dest; |
1742 | break; | |
1743 | default: | |
48d9356e | 1744 | dev_err(tsi148_bridge->parent, "Invalid destination type\n"); |
d22b8ed9 MW |
1745 | retval = -EINVAL; |
1746 | goto err_dest; | |
1747 | break; | |
1748 | } | |
1749 | ||
1750 | /* Fill out count */ | |
ac1a4f2c | 1751 | entry->descriptor.dcnt = cpu_to_be32((u32)count); |
d22b8ed9 MW |
1752 | |
1753 | /* Add to list */ | |
886953e9 | 1754 | list_add_tail(&entry->list, &list->entries); |
d22b8ed9 | 1755 | |
b2383c90 DK |
1756 | entry->dma_handle = dma_map_single(tsi148_bridge->parent, |
1757 | &entry->descriptor, | |
1758 | sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE); | |
1759 | if (dma_mapping_error(tsi148_bridge->parent, entry->dma_handle)) { | |
1760 | dev_err(tsi148_bridge->parent, "DMA mapping error\n"); | |
1761 | retval = -EINVAL; | |
1762 | goto err_dma; | |
1763 | } | |
1764 | ||
d22b8ed9 | 1765 | /* Fill out previous descriptors "Next Address" */ |
886953e9 | 1766 | if (entry->list.prev != &list->entries) { |
ac1a4f2c MW |
1767 | reg_split((unsigned long long)entry->dma_handle, &address_high, |
1768 | &address_low); | |
b2383c90 DK |
1769 | prev = list_entry(entry->list.prev, struct tsi148_dma_entry, |
1770 | list); | |
f656eaee DK |
1771 | prev->descriptor.dnlau = cpu_to_be32(address_high); |
1772 | prev->descriptor.dnlal = cpu_to_be32(address_low); | |
ac1a4f2c | 1773 | |
d22b8ed9 MW |
1774 | } |
1775 | ||
1776 | return 0; | |
1777 | ||
b2383c90 | 1778 | err_dma: |
d22b8ed9 MW |
1779 | err_dest: |
1780 | err_source: | |
1781 | err_align: | |
1782 | kfree(entry); | |
1783 | err_mem: | |
1784 | return retval; | |
1785 | } | |
1786 | ||
1787 | /* | |
1788 | * Check to see if the provided DMA channel is busy. | |
1789 | */ | |
29848ac9 | 1790 | static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel) |
d22b8ed9 MW |
1791 | { |
1792 | u32 tmp; | |
29848ac9 MW |
1793 | struct tsi148_driver *bridge; |
1794 | ||
1795 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 1796 | |
29848ac9 | 1797 | tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + |
d22b8ed9 MW |
1798 | TSI148_LCSR_OFFSET_DSTA); |
1799 | ||
1800 | if (tmp & TSI148_LCSR_DSTA_BSY) | |
1801 | return 0; | |
1802 | else | |
1803 | return 1; | |
1804 | ||
1805 | } | |
1806 | ||
1807 | /* | |
1808 | * Execute a previously generated link list | |
1809 | * | |
1810 | * XXX Need to provide control register configuration. | |
1811 | */ | |
5ade6c4d | 1812 | static int tsi148_dma_list_exec(struct vme_dma_list *list) |
d22b8ed9 MW |
1813 | { |
1814 | struct vme_dma_resource *ctrlr; | |
75c66b6d | 1815 | int channel, retval; |
d22b8ed9 | 1816 | struct tsi148_dma_entry *entry; |
d22b8ed9 MW |
1817 | u32 bus_addr_high, bus_addr_low; |
1818 | u32 val, dctlreg = 0; | |
48d9356e | 1819 | struct vme_bridge *tsi148_bridge; |
29848ac9 | 1820 | struct tsi148_driver *bridge; |
d22b8ed9 MW |
1821 | |
1822 | ctrlr = list->parent; | |
1823 | ||
48d9356e MW |
1824 | tsi148_bridge = ctrlr->parent; |
1825 | ||
1826 | bridge = tsi148_bridge->driver_priv; | |
29848ac9 | 1827 | |
886953e9 | 1828 | mutex_lock(&ctrlr->mtx); |
d22b8ed9 MW |
1829 | |
1830 | channel = ctrlr->number; | |
1831 | ||
886953e9 | 1832 | if (!list_empty(&ctrlr->running)) { |
d22b8ed9 MW |
1833 | /* |
1834 | * XXX We have an active DMA transfer and currently haven't | |
1835 | * sorted out the mechanism for "pending" DMA transfers. | |
1836 | * Return busy. | |
1837 | */ | |
1838 | /* Need to add to pending here */ | |
886953e9 | 1839 | mutex_unlock(&ctrlr->mtx); |
d22b8ed9 MW |
1840 | return -EBUSY; |
1841 | } else { | |
886953e9 | 1842 | list_add(&list->list, &ctrlr->running); |
d22b8ed9 | 1843 | } |
d22b8ed9 MW |
1844 | |
1845 | /* Get first bus address and write into registers */ | |
886953e9 | 1846 | entry = list_first_entry(&list->entries, struct tsi148_dma_entry, |
d22b8ed9 MW |
1847 | list); |
1848 | ||
886953e9 | 1849 | mutex_unlock(&ctrlr->mtx); |
d22b8ed9 | 1850 | |
3abc48ae | 1851 | reg_split(entry->dma_handle, &bus_addr_high, &bus_addr_low); |
d22b8ed9 | 1852 | |
29848ac9 | 1853 | iowrite32be(bus_addr_high, bridge->base + |
d22b8ed9 | 1854 | TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU); |
29848ac9 | 1855 | iowrite32be(bus_addr_low, bridge->base + |
d22b8ed9 MW |
1856 | TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL); |
1857 | ||
ac1a4f2c MW |
1858 | dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + |
1859 | TSI148_LCSR_OFFSET_DCTL); | |
1860 | ||
d22b8ed9 | 1861 | /* Start the operation */ |
29848ac9 | 1862 | iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base + |
d22b8ed9 MW |
1863 | TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); |
1864 | ||
75c66b6d | 1865 | retval = wait_event_interruptible(bridge->dma_queue[channel], |
29848ac9 | 1866 | tsi148_dma_busy(ctrlr->parent, channel)); |
ac1a4f2c | 1867 | |
75c66b6d DK |
1868 | if (retval) { |
1869 | iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base + | |
1870 | TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); | |
1871 | /* Wait for the operation to abort */ | |
1872 | wait_event(bridge->dma_queue[channel], | |
1873 | tsi148_dma_busy(ctrlr->parent, channel)); | |
1874 | retval = -EINTR; | |
1875 | goto exit; | |
1876 | } | |
1877 | ||
d22b8ed9 MW |
1878 | /* |
1879 | * Read status register, this register is valid until we kick off a | |
1880 | * new transfer. | |
1881 | */ | |
29848ac9 | 1882 | val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + |
d22b8ed9 MW |
1883 | TSI148_LCSR_OFFSET_DSTA); |
1884 | ||
1885 | if (val & TSI148_LCSR_DSTA_VBE) { | |
48d9356e | 1886 | dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val); |
d22b8ed9 MW |
1887 | retval = -EIO; |
1888 | } | |
1889 | ||
75c66b6d | 1890 | exit: |
d22b8ed9 | 1891 | /* Remove list from running list */ |
886953e9 EC |
1892 | mutex_lock(&ctrlr->mtx); |
1893 | list_del(&list->list); | |
1894 | mutex_unlock(&ctrlr->mtx); | |
d22b8ed9 MW |
1895 | |
1896 | return retval; | |
1897 | } | |
1898 | ||
1899 | /* | |
1900 | * Clean up a previously generated link list | |
1901 | * | |
1902 | * We have a separate function, don't assume that the chain can't be reused. | |
1903 | */ | |
5ade6c4d | 1904 | static int tsi148_dma_list_empty(struct vme_dma_list *list) |
d22b8ed9 MW |
1905 | { |
1906 | struct list_head *pos, *temp; | |
7946328f | 1907 | struct tsi148_dma_entry *entry; |
d22b8ed9 | 1908 | |
3abc48ae MW |
1909 | struct vme_bridge *tsi148_bridge = list->parent->parent; |
1910 | ||
d22b8ed9 | 1911 | /* detach and free each entry */ |
886953e9 | 1912 | list_for_each_safe(pos, temp, &list->entries) { |
d22b8ed9 MW |
1913 | list_del(pos); |
1914 | entry = list_entry(pos, struct tsi148_dma_entry, list); | |
3abc48ae MW |
1915 | |
1916 | dma_unmap_single(tsi148_bridge->parent, entry->dma_handle, | |
1917 | sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE); | |
d22b8ed9 MW |
1918 | kfree(entry); |
1919 | } | |
1920 | ||
7946328f | 1921 | return 0; |
d22b8ed9 MW |
1922 | } |
1923 | ||
1924 | /* | |
1925 | * All 4 location monitors reside at the same base - this is therefore a | |
1926 | * system wide configuration. | |
1927 | * | |
1928 | * This does not enable the LM monitor - that should be done when the first | |
1929 | * callback is attached and disabled when the last callback is removed. | |
1930 | */ | |
5ade6c4d | 1931 | static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, |
6af04b06 | 1932 | u32 aspace, u32 cycle) |
d22b8ed9 MW |
1933 | { |
1934 | u32 lm_base_high, lm_base_low, lm_ctl = 0; | |
1935 | int i; | |
48d9356e | 1936 | struct vme_bridge *tsi148_bridge; |
29848ac9 MW |
1937 | struct tsi148_driver *bridge; |
1938 | ||
48d9356e MW |
1939 | tsi148_bridge = lm->parent; |
1940 | ||
1941 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 1942 | |
886953e9 | 1943 | mutex_lock(&lm->mtx); |
d22b8ed9 MW |
1944 | |
1945 | /* If we already have a callback attached, we can't move it! */ | |
42fb5031 | 1946 | for (i = 0; i < lm->monitors; i++) { |
29848ac9 | 1947 | if (bridge->lm_callback[i] != NULL) { |
886953e9 | 1948 | mutex_unlock(&lm->mtx); |
48d9356e MW |
1949 | dev_err(tsi148_bridge->parent, "Location monitor " |
1950 | "callback attached, can't reset\n"); | |
d22b8ed9 MW |
1951 | return -EBUSY; |
1952 | } | |
1953 | } | |
1954 | ||
1955 | switch (aspace) { | |
1956 | case VME_A16: | |
1957 | lm_ctl |= TSI148_LCSR_LMAT_AS_A16; | |
1958 | break; | |
1959 | case VME_A24: | |
1960 | lm_ctl |= TSI148_LCSR_LMAT_AS_A24; | |
1961 | break; | |
1962 | case VME_A32: | |
1963 | lm_ctl |= TSI148_LCSR_LMAT_AS_A32; | |
1964 | break; | |
1965 | case VME_A64: | |
1966 | lm_ctl |= TSI148_LCSR_LMAT_AS_A64; | |
1967 | break; | |
1968 | default: | |
886953e9 | 1969 | mutex_unlock(&lm->mtx); |
48d9356e | 1970 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
d22b8ed9 MW |
1971 | return -EINVAL; |
1972 | break; | |
1973 | } | |
1974 | ||
1975 | if (cycle & VME_SUPER) | |
1976 | lm_ctl |= TSI148_LCSR_LMAT_SUPR ; | |
1977 | if (cycle & VME_USER) | |
1978 | lm_ctl |= TSI148_LCSR_LMAT_NPRIV; | |
1979 | if (cycle & VME_PROG) | |
1980 | lm_ctl |= TSI148_LCSR_LMAT_PGM; | |
1981 | if (cycle & VME_DATA) | |
1982 | lm_ctl |= TSI148_LCSR_LMAT_DATA; | |
1983 | ||
1984 | reg_split(lm_base, &lm_base_high, &lm_base_low); | |
1985 | ||
29848ac9 MW |
1986 | iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU); |
1987 | iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL); | |
1988 | iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); | |
d22b8ed9 | 1989 | |
886953e9 | 1990 | mutex_unlock(&lm->mtx); |
d22b8ed9 MW |
1991 | |
1992 | return 0; | |
1993 | } | |
1994 | ||
1995 | /* Get configuration of the callback monitor and return whether it is enabled | |
1996 | * or disabled. | |
1997 | */ | |
5ade6c4d | 1998 | static int tsi148_lm_get(struct vme_lm_resource *lm, |
6af04b06 | 1999 | unsigned long long *lm_base, u32 *aspace, u32 *cycle) |
d22b8ed9 MW |
2000 | { |
2001 | u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0; | |
29848ac9 MW |
2002 | struct tsi148_driver *bridge; |
2003 | ||
2004 | bridge = lm->parent->driver_priv; | |
d22b8ed9 | 2005 | |
886953e9 | 2006 | mutex_lock(&lm->mtx); |
d22b8ed9 | 2007 | |
29848ac9 MW |
2008 | lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU); |
2009 | lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL); | |
2010 | lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); | |
d22b8ed9 MW |
2011 | |
2012 | reg_join(lm_base_high, lm_base_low, lm_base); | |
2013 | ||
2014 | if (lm_ctl & TSI148_LCSR_LMAT_EN) | |
2015 | enabled = 1; | |
2016 | ||
7946328f | 2017 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) |
d22b8ed9 | 2018 | *aspace |= VME_A16; |
7946328f MW |
2019 | |
2020 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) | |
d22b8ed9 | 2021 | *aspace |= VME_A24; |
7946328f MW |
2022 | |
2023 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) | |
d22b8ed9 | 2024 | *aspace |= VME_A32; |
7946328f MW |
2025 | |
2026 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) | |
d22b8ed9 | 2027 | *aspace |= VME_A64; |
7946328f | 2028 | |
d22b8ed9 MW |
2029 | |
2030 | if (lm_ctl & TSI148_LCSR_LMAT_SUPR) | |
2031 | *cycle |= VME_SUPER; | |
2032 | if (lm_ctl & TSI148_LCSR_LMAT_NPRIV) | |
2033 | *cycle |= VME_USER; | |
2034 | if (lm_ctl & TSI148_LCSR_LMAT_PGM) | |
2035 | *cycle |= VME_PROG; | |
2036 | if (lm_ctl & TSI148_LCSR_LMAT_DATA) | |
2037 | *cycle |= VME_DATA; | |
2038 | ||
886953e9 | 2039 | mutex_unlock(&lm->mtx); |
d22b8ed9 MW |
2040 | |
2041 | return enabled; | |
2042 | } | |
2043 | ||
2044 | /* | |
2045 | * Attach a callback to a specific location monitor. | |
2046 | * | |
2047 | * Callback will be passed the monitor triggered. | |
2048 | */ | |
5ade6c4d | 2049 | static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, |
42fb5031 | 2050 | void (*callback)(int)) |
d22b8ed9 MW |
2051 | { |
2052 | u32 lm_ctl, tmp; | |
48d9356e | 2053 | struct vme_bridge *tsi148_bridge; |
29848ac9 MW |
2054 | struct tsi148_driver *bridge; |
2055 | ||
48d9356e MW |
2056 | tsi148_bridge = lm->parent; |
2057 | ||
2058 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 2059 | |
886953e9 | 2060 | mutex_lock(&lm->mtx); |
d22b8ed9 MW |
2061 | |
2062 | /* Ensure that the location monitor is configured - need PGM or DATA */ | |
29848ac9 | 2063 | lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); |
d22b8ed9 | 2064 | if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) { |
886953e9 | 2065 | mutex_unlock(&lm->mtx); |
48d9356e MW |
2066 | dev_err(tsi148_bridge->parent, "Location monitor not properly " |
2067 | "configured\n"); | |
d22b8ed9 MW |
2068 | return -EINVAL; |
2069 | } | |
2070 | ||
2071 | /* Check that a callback isn't already attached */ | |
29848ac9 | 2072 | if (bridge->lm_callback[monitor] != NULL) { |
886953e9 | 2073 | mutex_unlock(&lm->mtx); |
48d9356e | 2074 | dev_err(tsi148_bridge->parent, "Existing callback attached\n"); |
d22b8ed9 MW |
2075 | return -EBUSY; |
2076 | } | |
2077 | ||
2078 | /* Attach callback */ | |
29848ac9 | 2079 | bridge->lm_callback[monitor] = callback; |
d22b8ed9 MW |
2080 | |
2081 | /* Enable Location Monitor interrupt */ | |
29848ac9 | 2082 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
d22b8ed9 | 2083 | tmp |= TSI148_LCSR_INTEN_LMEN[monitor]; |
29848ac9 | 2084 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); |
d22b8ed9 | 2085 | |
29848ac9 | 2086 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
d22b8ed9 | 2087 | tmp |= TSI148_LCSR_INTEO_LMEO[monitor]; |
29848ac9 | 2088 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
d22b8ed9 MW |
2089 | |
2090 | /* Ensure that global Location Monitor Enable set */ | |
2091 | if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) { | |
2092 | lm_ctl |= TSI148_LCSR_LMAT_EN; | |
29848ac9 | 2093 | iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); |
d22b8ed9 MW |
2094 | } |
2095 | ||
886953e9 | 2096 | mutex_unlock(&lm->mtx); |
d22b8ed9 MW |
2097 | |
2098 | return 0; | |
2099 | } | |
2100 | ||
2101 | /* | |
2102 | * Detach a callback function forn a specific location monitor. | |
2103 | */ | |
5ade6c4d | 2104 | static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor) |
d22b8ed9 MW |
2105 | { |
2106 | u32 lm_en, tmp; | |
29848ac9 MW |
2107 | struct tsi148_driver *bridge; |
2108 | ||
2109 | bridge = lm->parent->driver_priv; | |
d22b8ed9 | 2110 | |
886953e9 | 2111 | mutex_lock(&lm->mtx); |
d22b8ed9 MW |
2112 | |
2113 | /* Disable Location Monitor and ensure previous interrupts are clear */ | |
29848ac9 | 2114 | lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
d22b8ed9 | 2115 | lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor]; |
29848ac9 | 2116 | iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN); |
d22b8ed9 | 2117 | |
29848ac9 | 2118 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
d22b8ed9 | 2119 | tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor]; |
29848ac9 | 2120 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
d22b8ed9 MW |
2121 | |
2122 | iowrite32be(TSI148_LCSR_INTC_LMC[monitor], | |
29848ac9 | 2123 | bridge->base + TSI148_LCSR_INTC); |
d22b8ed9 MW |
2124 | |
2125 | /* Detach callback */ | |
29848ac9 | 2126 | bridge->lm_callback[monitor] = NULL; |
d22b8ed9 MW |
2127 | |
2128 | /* If all location monitors disabled, disable global Location Monitor */ | |
2129 | if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S | | |
2130 | TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) { | |
29848ac9 | 2131 | tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT); |
d22b8ed9 | 2132 | tmp &= ~TSI148_LCSR_LMAT_EN; |
29848ac9 | 2133 | iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT); |
d22b8ed9 MW |
2134 | } |
2135 | ||
886953e9 | 2136 | mutex_unlock(&lm->mtx); |
d22b8ed9 MW |
2137 | |
2138 | return 0; | |
2139 | } | |
2140 | ||
2141 | /* | |
2142 | * Determine Geographical Addressing | |
2143 | */ | |
5ade6c4d | 2144 | static int tsi148_slot_get(struct vme_bridge *tsi148_bridge) |
d22b8ed9 | 2145 | { |
7946328f | 2146 | u32 slot = 0; |
29848ac9 MW |
2147 | struct tsi148_driver *bridge; |
2148 | ||
2149 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 2150 | |
638f199d | 2151 | if (!geoid) { |
29848ac9 | 2152 | slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT); |
638f199d MW |
2153 | slot = slot & TSI148_LCSR_VSTAT_GA_M; |
2154 | } else | |
2155 | slot = geoid; | |
2156 | ||
d22b8ed9 MW |
2157 | return (int)slot; |
2158 | } | |
2159 | ||
8a508ff4 | 2160 | static void *tsi148_alloc_consistent(struct device *parent, size_t size, |
7f58f025 MV |
2161 | dma_addr_t *dma) |
2162 | { | |
2163 | struct pci_dev *pdev; | |
2164 | ||
2165 | /* Find pci_dev container of dev */ | |
177581fa | 2166 | pdev = to_pci_dev(parent); |
7f58f025 MV |
2167 | |
2168 | return pci_alloc_consistent(pdev, size, dma); | |
2169 | } | |
2170 | ||
8a508ff4 HS |
2171 | static void tsi148_free_consistent(struct device *parent, size_t size, |
2172 | void *vaddr, dma_addr_t dma) | |
7f58f025 MV |
2173 | { |
2174 | struct pci_dev *pdev; | |
2175 | ||
2176 | /* Find pci_dev container of dev */ | |
177581fa | 2177 | pdev = to_pci_dev(parent); |
7f58f025 MV |
2178 | |
2179 | pci_free_consistent(pdev, size, vaddr, dma); | |
2180 | } | |
2181 | ||
d22b8ed9 MW |
2182 | /* |
2183 | * Configure CR/CSR space | |
2184 | * | |
2185 | * Access to the CR/CSR can be configured at power-up. The location of the | |
2186 | * CR/CSR registers in the CR/CSR address space is determined by the boards | |
2187 | * Auto-ID or Geographic address. This function ensures that the window is | |
2188 | * enabled at an offset consistent with the boards geopgraphic address. | |
2189 | * | |
2190 | * Each board has a 512kB window, with the highest 4kB being used for the | |
2191 | * boards registers, this means there is a fix length 508kB window which must | |
2192 | * be mapped onto PCI memory. | |
2193 | */ | |
29848ac9 MW |
2194 | static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, |
2195 | struct pci_dev *pdev) | |
d22b8ed9 MW |
2196 | { |
2197 | u32 cbar, crat, vstat; | |
2198 | u32 crcsr_bus_high, crcsr_bus_low; | |
2199 | int retval; | |
29848ac9 MW |
2200 | struct tsi148_driver *bridge; |
2201 | ||
2202 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
2203 | |
2204 | /* Allocate mem for CR/CSR image */ | |
88b2608c JP |
2205 | bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE, |
2206 | &bridge->crcsr_bus); | |
29848ac9 | 2207 | if (bridge->crcsr_kernel == NULL) { |
48d9356e MW |
2208 | dev_err(tsi148_bridge->parent, "Failed to allocate memory for " |
2209 | "CR/CSR image\n"); | |
d22b8ed9 MW |
2210 | return -ENOMEM; |
2211 | } | |
2212 | ||
29848ac9 | 2213 | reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low); |
d22b8ed9 | 2214 | |
29848ac9 MW |
2215 | iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU); |
2216 | iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL); | |
d22b8ed9 MW |
2217 | |
2218 | /* Ensure that the CR/CSR is configured at the correct offset */ | |
29848ac9 | 2219 | cbar = ioread32be(bridge->base + TSI148_CBAR); |
d22b8ed9 MW |
2220 | cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3; |
2221 | ||
29848ac9 | 2222 | vstat = tsi148_slot_get(tsi148_bridge); |
d22b8ed9 MW |
2223 | |
2224 | if (cbar != vstat) { | |
638f199d | 2225 | cbar = vstat; |
48d9356e | 2226 | dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n"); |
29848ac9 | 2227 | iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); |
d22b8ed9 | 2228 | } |
48d9356e | 2229 | dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); |
d22b8ed9 | 2230 | |
29848ac9 | 2231 | crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); |
2981795c MW |
2232 | if (crat & TSI148_LCSR_CRAT_EN) |
2233 | dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n"); | |
2234 | else { | |
48d9356e | 2235 | dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n"); |
d22b8ed9 | 2236 | iowrite32be(crat | TSI148_LCSR_CRAT_EN, |
29848ac9 | 2237 | bridge->base + TSI148_LCSR_CRAT); |
2981795c | 2238 | } |
d22b8ed9 MW |
2239 | |
2240 | /* If we want flushed, error-checked writes, set up a window | |
2241 | * over the CR/CSR registers. We read from here to safely flush | |
2242 | * through VME writes. | |
2243 | */ | |
7946328f | 2244 | if (err_chk) { |
29848ac9 MW |
2245 | retval = tsi148_master_set(bridge->flush_image, 1, |
2246 | (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT, | |
2247 | VME_D16); | |
d22b8ed9 | 2248 | if (retval) |
48d9356e MW |
2249 | dev_err(tsi148_bridge->parent, "Configuring flush image" |
2250 | " failed\n"); | |
d22b8ed9 MW |
2251 | } |
2252 | ||
2253 | return 0; | |
2254 | ||
2255 | } | |
2256 | ||
29848ac9 MW |
2257 | static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge, |
2258 | struct pci_dev *pdev) | |
d22b8ed9 MW |
2259 | { |
2260 | u32 crat; | |
29848ac9 MW |
2261 | struct tsi148_driver *bridge; |
2262 | ||
2263 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
2264 | |
2265 | /* Turn off CR/CSR space */ | |
29848ac9 | 2266 | crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); |
d22b8ed9 | 2267 | iowrite32be(crat & ~TSI148_LCSR_CRAT_EN, |
29848ac9 | 2268 | bridge->base + TSI148_LCSR_CRAT); |
d22b8ed9 MW |
2269 | |
2270 | /* Free image */ | |
29848ac9 MW |
2271 | iowrite32be(0, bridge->base + TSI148_LCSR_CROU); |
2272 | iowrite32be(0, bridge->base + TSI148_LCSR_CROL); | |
d22b8ed9 | 2273 | |
29848ac9 MW |
2274 | pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, |
2275 | bridge->crcsr_bus); | |
d22b8ed9 MW |
2276 | } |
2277 | ||
2278 | static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
2279 | { | |
2280 | int retval, i, master_num; | |
2281 | u32 data; | |
b49c32ba | 2282 | struct list_head *pos = NULL, *n; |
29848ac9 MW |
2283 | struct vme_bridge *tsi148_bridge; |
2284 | struct tsi148_driver *tsi148_device; | |
d22b8ed9 MW |
2285 | struct vme_master_resource *master_image; |
2286 | struct vme_slave_resource *slave_image; | |
2287 | struct vme_dma_resource *dma_ctrlr; | |
42fb5031 | 2288 | struct vme_lm_resource *lm; |
d22b8ed9 MW |
2289 | |
2290 | /* If we want to support more than one of each bridge, we need to | |
2291 | * dynamically generate this so we get one per device | |
2292 | */ | |
7a6cb0d5 | 2293 | tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL); |
d22b8ed9 MW |
2294 | if (tsi148_bridge == NULL) { |
2295 | dev_err(&pdev->dev, "Failed to allocate memory for device " | |
2296 | "structure\n"); | |
2297 | retval = -ENOMEM; | |
2298 | goto err_struct; | |
2299 | } | |
326071b3 | 2300 | vme_init_bridge(tsi148_bridge); |
d22b8ed9 | 2301 | |
7a6cb0d5 | 2302 | tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL); |
29848ac9 MW |
2303 | if (tsi148_device == NULL) { |
2304 | dev_err(&pdev->dev, "Failed to allocate memory for device " | |
2305 | "structure\n"); | |
2306 | retval = -ENOMEM; | |
2307 | goto err_driver; | |
2308 | } | |
2309 | ||
29848ac9 MW |
2310 | tsi148_bridge->driver_priv = tsi148_device; |
2311 | ||
d22b8ed9 MW |
2312 | /* Enable the device */ |
2313 | retval = pci_enable_device(pdev); | |
2314 | if (retval) { | |
2315 | dev_err(&pdev->dev, "Unable to enable device\n"); | |
2316 | goto err_enable; | |
2317 | } | |
2318 | ||
2319 | /* Map Registers */ | |
2320 | retval = pci_request_regions(pdev, driver_name); | |
2321 | if (retval) { | |
2322 | dev_err(&pdev->dev, "Unable to reserve resources\n"); | |
2323 | goto err_resource; | |
2324 | } | |
2325 | ||
2326 | /* map registers in BAR 0 */ | |
29848ac9 MW |
2327 | tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0), |
2328 | 4096); | |
2329 | if (!tsi148_device->base) { | |
d22b8ed9 MW |
2330 | dev_err(&pdev->dev, "Unable to remap CRG region\n"); |
2331 | retval = -EIO; | |
2332 | goto err_remap; | |
2333 | } | |
2334 | ||
2335 | /* Check to see if the mapping worked out */ | |
29848ac9 | 2336 | data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF; |
d22b8ed9 MW |
2337 | if (data != PCI_VENDOR_ID_TUNDRA) { |
2338 | dev_err(&pdev->dev, "CRG region check failed\n"); | |
2339 | retval = -EIO; | |
2340 | goto err_test; | |
2341 | } | |
2342 | ||
2343 | /* Initialize wait queues & mutual exclusion flags */ | |
886953e9 EC |
2344 | init_waitqueue_head(&tsi148_device->dma_queue[0]); |
2345 | init_waitqueue_head(&tsi148_device->dma_queue[1]); | |
2346 | init_waitqueue_head(&tsi148_device->iack_queue); | |
2347 | mutex_init(&tsi148_device->vme_int); | |
2348 | mutex_init(&tsi148_device->vme_rmw); | |
d22b8ed9 | 2349 | |
886953e9 | 2350 | tsi148_bridge->parent = &pdev->dev; |
d22b8ed9 MW |
2351 | strcpy(tsi148_bridge->name, driver_name); |
2352 | ||
2353 | /* Setup IRQ */ | |
2354 | retval = tsi148_irq_init(tsi148_bridge); | |
2355 | if (retval != 0) { | |
2356 | dev_err(&pdev->dev, "Chip Initialization failed.\n"); | |
2357 | goto err_irq; | |
2358 | } | |
2359 | ||
2360 | /* If we are going to flush writes, we need to read from the VME bus. | |
2361 | * We need to do this safely, thus we read the devices own CR/CSR | |
2362 | * register. To do this we must set up a window in CR/CSR space and | |
2363 | * hence have one less master window resource available. | |
2364 | */ | |
2365 | master_num = TSI148_MAX_MASTER; | |
7946328f | 2366 | if (err_chk) { |
d22b8ed9 | 2367 | master_num--; |
29848ac9 | 2368 | |
32414878 | 2369 | tsi148_device->flush_image = |
29848ac9 MW |
2370 | kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL); |
2371 | if (tsi148_device->flush_image == NULL) { | |
d22b8ed9 MW |
2372 | dev_err(&pdev->dev, "Failed to allocate memory for " |
2373 | "flush resource structure\n"); | |
2374 | retval = -ENOMEM; | |
2375 | goto err_master; | |
2376 | } | |
29848ac9 | 2377 | tsi148_device->flush_image->parent = tsi148_bridge; |
886953e9 | 2378 | spin_lock_init(&tsi148_device->flush_image->lock); |
29848ac9 MW |
2379 | tsi148_device->flush_image->locked = 1; |
2380 | tsi148_device->flush_image->number = master_num; | |
886953e9 | 2381 | memset(&tsi148_device->flush_image->bus_resource, 0, |
d22b8ed9 | 2382 | sizeof(struct resource)); |
29848ac9 | 2383 | tsi148_device->flush_image->kern_base = NULL; |
d22b8ed9 MW |
2384 | } |
2385 | ||
2386 | /* Add master windows to list */ | |
d22b8ed9 | 2387 | for (i = 0; i < master_num; i++) { |
7946328f MW |
2388 | master_image = kmalloc(sizeof(struct vme_master_resource), |
2389 | GFP_KERNEL); | |
d22b8ed9 MW |
2390 | if (master_image == NULL) { |
2391 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
2392 | "master resource structure\n"); | |
2393 | retval = -ENOMEM; | |
2394 | goto err_master; | |
2395 | } | |
2396 | master_image->parent = tsi148_bridge; | |
886953e9 | 2397 | spin_lock_init(&master_image->lock); |
d22b8ed9 MW |
2398 | master_image->locked = 0; |
2399 | master_image->number = i; | |
2400 | master_image->address_attr = VME_A16 | VME_A24 | VME_A32 | | |
08e03c26 MW |
2401 | VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 | |
2402 | VME_USER3 | VME_USER4; | |
d22b8ed9 MW |
2403 | master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | |
2404 | VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 | | |
2405 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | | |
2406 | VME_PROG | VME_DATA; | |
2407 | master_image->width_attr = VME_D16 | VME_D32; | |
886953e9 | 2408 | memset(&master_image->bus_resource, 0, |
d22b8ed9 MW |
2409 | sizeof(struct resource)); |
2410 | master_image->kern_base = NULL; | |
886953e9 EC |
2411 | list_add_tail(&master_image->list, |
2412 | &tsi148_bridge->master_resources); | |
d22b8ed9 MW |
2413 | } |
2414 | ||
2415 | /* Add slave windows to list */ | |
d22b8ed9 | 2416 | for (i = 0; i < TSI148_MAX_SLAVE; i++) { |
7946328f MW |
2417 | slave_image = kmalloc(sizeof(struct vme_slave_resource), |
2418 | GFP_KERNEL); | |
d22b8ed9 MW |
2419 | if (slave_image == NULL) { |
2420 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
2421 | "slave resource structure\n"); | |
2422 | retval = -ENOMEM; | |
2423 | goto err_slave; | |
2424 | } | |
2425 | slave_image->parent = tsi148_bridge; | |
886953e9 | 2426 | mutex_init(&slave_image->mtx); |
d22b8ed9 MW |
2427 | slave_image->locked = 0; |
2428 | slave_image->number = i; | |
2429 | slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 | | |
08e03c26 | 2430 | VME_A64; |
d22b8ed9 MW |
2431 | slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | |
2432 | VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 | | |
2433 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | | |
2434 | VME_PROG | VME_DATA; | |
886953e9 EC |
2435 | list_add_tail(&slave_image->list, |
2436 | &tsi148_bridge->slave_resources); | |
d22b8ed9 MW |
2437 | } |
2438 | ||
2439 | /* Add dma engines to list */ | |
d22b8ed9 | 2440 | for (i = 0; i < TSI148_MAX_DMA; i++) { |
7946328f MW |
2441 | dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource), |
2442 | GFP_KERNEL); | |
d22b8ed9 MW |
2443 | if (dma_ctrlr == NULL) { |
2444 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
2445 | "dma resource structure\n"); | |
2446 | retval = -ENOMEM; | |
2447 | goto err_dma; | |
2448 | } | |
2449 | dma_ctrlr->parent = tsi148_bridge; | |
886953e9 | 2450 | mutex_init(&dma_ctrlr->mtx); |
d22b8ed9 MW |
2451 | dma_ctrlr->locked = 0; |
2452 | dma_ctrlr->number = i; | |
4f723df4 MW |
2453 | dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | |
2454 | VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME | | |
2455 | VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME | | |
2456 | VME_DMA_PATTERN_TO_MEM; | |
886953e9 EC |
2457 | INIT_LIST_HEAD(&dma_ctrlr->pending); |
2458 | INIT_LIST_HEAD(&dma_ctrlr->running); | |
2459 | list_add_tail(&dma_ctrlr->list, | |
2460 | &tsi148_bridge->dma_resources); | |
d22b8ed9 MW |
2461 | } |
2462 | ||
42fb5031 | 2463 | /* Add location monitor to list */ |
42fb5031 MW |
2464 | lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL); |
2465 | if (lm == NULL) { | |
2466 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
2467 | "location monitor resource structure\n"); | |
2468 | retval = -ENOMEM; | |
2469 | goto err_lm; | |
2470 | } | |
2471 | lm->parent = tsi148_bridge; | |
886953e9 | 2472 | mutex_init(&lm->mtx); |
42fb5031 MW |
2473 | lm->locked = 0; |
2474 | lm->number = 1; | |
2475 | lm->monitors = 4; | |
886953e9 | 2476 | list_add_tail(&lm->list, &tsi148_bridge->lm_resources); |
42fb5031 | 2477 | |
d22b8ed9 MW |
2478 | tsi148_bridge->slave_get = tsi148_slave_get; |
2479 | tsi148_bridge->slave_set = tsi148_slave_set; | |
2480 | tsi148_bridge->master_get = tsi148_master_get; | |
2481 | tsi148_bridge->master_set = tsi148_master_set; | |
2482 | tsi148_bridge->master_read = tsi148_master_read; | |
2483 | tsi148_bridge->master_write = tsi148_master_write; | |
2484 | tsi148_bridge->master_rmw = tsi148_master_rmw; | |
2485 | tsi148_bridge->dma_list_add = tsi148_dma_list_add; | |
2486 | tsi148_bridge->dma_list_exec = tsi148_dma_list_exec; | |
2487 | tsi148_bridge->dma_list_empty = tsi148_dma_list_empty; | |
c813f592 MW |
2488 | tsi148_bridge->irq_set = tsi148_irq_set; |
2489 | tsi148_bridge->irq_generate = tsi148_irq_generate; | |
d22b8ed9 MW |
2490 | tsi148_bridge->lm_set = tsi148_lm_set; |
2491 | tsi148_bridge->lm_get = tsi148_lm_get; | |
2492 | tsi148_bridge->lm_attach = tsi148_lm_attach; | |
2493 | tsi148_bridge->lm_detach = tsi148_lm_detach; | |
2494 | tsi148_bridge->slot_get = tsi148_slot_get; | |
7f58f025 MV |
2495 | tsi148_bridge->alloc_consistent = tsi148_alloc_consistent; |
2496 | tsi148_bridge->free_consistent = tsi148_free_consistent; | |
d22b8ed9 | 2497 | |
29848ac9 | 2498 | data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); |
d22b8ed9 | 2499 | dev_info(&pdev->dev, "Board is%s the VME system controller\n", |
7946328f | 2500 | (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not"); |
29848ac9 | 2501 | if (!geoid) |
638f199d MW |
2502 | dev_info(&pdev->dev, "VME geographical address is %d\n", |
2503 | data & TSI148_LCSR_VSTAT_GA_M); | |
29848ac9 | 2504 | else |
638f199d MW |
2505 | dev_info(&pdev->dev, "VME geographical address is set to %d\n", |
2506 | geoid); | |
29848ac9 | 2507 | |
d22b8ed9 MW |
2508 | dev_info(&pdev->dev, "VME Write and flush and error check is %s\n", |
2509 | err_chk ? "enabled" : "disabled"); | |
2510 | ||
0686ab7a WY |
2511 | retval = tsi148_crcsr_init(tsi148_bridge, pdev); |
2512 | if (retval) { | |
d22b8ed9 MW |
2513 | dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); |
2514 | goto err_crcsr; | |
4839737b | 2515 | } |
d22b8ed9 | 2516 | |
d22b8ed9 MW |
2517 | retval = vme_register_bridge(tsi148_bridge); |
2518 | if (retval != 0) { | |
2519 | dev_err(&pdev->dev, "Chip Registration failed.\n"); | |
2520 | goto err_reg; | |
2521 | } | |
2522 | ||
29848ac9 MW |
2523 | pci_set_drvdata(pdev, tsi148_bridge); |
2524 | ||
d22b8ed9 | 2525 | /* Clear VME bus "board fail", and "power-up reset" lines */ |
29848ac9 | 2526 | data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); |
d22b8ed9 MW |
2527 | data &= ~TSI148_LCSR_VSTAT_BRDFL; |
2528 | data |= TSI148_LCSR_VSTAT_CPURST; | |
29848ac9 | 2529 | iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT); |
d22b8ed9 MW |
2530 | |
2531 | return 0; | |
2532 | ||
d22b8ed9 | 2533 | err_reg: |
29848ac9 | 2534 | tsi148_crcsr_exit(tsi148_bridge, pdev); |
d22b8ed9 | 2535 | err_crcsr: |
42fb5031 MW |
2536 | err_lm: |
2537 | /* resources are stored in link list */ | |
b49c32ba | 2538 | list_for_each_safe(pos, n, &tsi148_bridge->lm_resources) { |
42fb5031 MW |
2539 | lm = list_entry(pos, struct vme_lm_resource, list); |
2540 | list_del(pos); | |
2541 | kfree(lm); | |
2542 | } | |
d22b8ed9 MW |
2543 | err_dma: |
2544 | /* resources are stored in link list */ | |
b49c32ba | 2545 | list_for_each_safe(pos, n, &tsi148_bridge->dma_resources) { |
d22b8ed9 MW |
2546 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); |
2547 | list_del(pos); | |
2548 | kfree(dma_ctrlr); | |
2549 | } | |
2550 | err_slave: | |
2551 | /* resources are stored in link list */ | |
b49c32ba | 2552 | list_for_each_safe(pos, n, &tsi148_bridge->slave_resources) { |
d22b8ed9 MW |
2553 | slave_image = list_entry(pos, struct vme_slave_resource, list); |
2554 | list_del(pos); | |
2555 | kfree(slave_image); | |
2556 | } | |
2557 | err_master: | |
2558 | /* resources are stored in link list */ | |
b49c32ba | 2559 | list_for_each_safe(pos, n, &tsi148_bridge->master_resources) { |
7946328f MW |
2560 | master_image = list_entry(pos, struct vme_master_resource, |
2561 | list); | |
d22b8ed9 MW |
2562 | list_del(pos); |
2563 | kfree(master_image); | |
2564 | } | |
2565 | ||
a82ad05e | 2566 | tsi148_irq_exit(tsi148_bridge, pdev); |
d22b8ed9 MW |
2567 | err_irq: |
2568 | err_test: | |
29848ac9 | 2569 | iounmap(tsi148_device->base); |
d22b8ed9 MW |
2570 | err_remap: |
2571 | pci_release_regions(pdev); | |
2572 | err_resource: | |
2573 | pci_disable_device(pdev); | |
2574 | err_enable: | |
29848ac9 MW |
2575 | kfree(tsi148_device); |
2576 | err_driver: | |
d22b8ed9 MW |
2577 | kfree(tsi148_bridge); |
2578 | err_struct: | |
2579 | return retval; | |
2580 | ||
2581 | } | |
2582 | ||
2583 | static void tsi148_remove(struct pci_dev *pdev) | |
2584 | { | |
2585 | struct list_head *pos = NULL; | |
b558ba2f | 2586 | struct list_head *tmplist; |
d22b8ed9 MW |
2587 | struct vme_master_resource *master_image; |
2588 | struct vme_slave_resource *slave_image; | |
2589 | struct vme_dma_resource *dma_ctrlr; | |
2590 | int i; | |
29848ac9 MW |
2591 | struct tsi148_driver *bridge; |
2592 | struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev); | |
2593 | ||
2594 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 2595 | |
d22b8ed9 | 2596 | |
29848ac9 | 2597 | dev_dbg(&pdev->dev, "Driver is being unloaded.\n"); |
d22b8ed9 MW |
2598 | |
2599 | /* | |
2600 | * Shutdown all inbound and outbound windows. | |
2601 | */ | |
2602 | for (i = 0; i < 8; i++) { | |
29848ac9 | 2603 | iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 2604 | TSI148_LCSR_OFFSET_ITAT); |
29848ac9 | 2605 | iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
2606 | TSI148_LCSR_OFFSET_OTAT); |
2607 | } | |
2608 | ||
2609 | /* | |
2610 | * Shutdown Location monitor. | |
2611 | */ | |
29848ac9 | 2612 | iowrite32be(0, bridge->base + TSI148_LCSR_LMAT); |
d22b8ed9 MW |
2613 | |
2614 | /* | |
2615 | * Shutdown CRG map. | |
2616 | */ | |
29848ac9 | 2617 | iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT); |
d22b8ed9 MW |
2618 | |
2619 | /* | |
2620 | * Clear error status. | |
2621 | */ | |
29848ac9 MW |
2622 | iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT); |
2623 | iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT); | |
2624 | iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT); | |
d22b8ed9 MW |
2625 | |
2626 | /* | |
2627 | * Remove VIRQ interrupt (if any) | |
2628 | */ | |
29848ac9 MW |
2629 | if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800) |
2630 | iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR); | |
d22b8ed9 | 2631 | |
d22b8ed9 MW |
2632 | /* |
2633 | * Map all Interrupts to PCI INTA | |
2634 | */ | |
29848ac9 MW |
2635 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1); |
2636 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2); | |
d22b8ed9 | 2637 | |
a82ad05e | 2638 | tsi148_irq_exit(tsi148_bridge, pdev); |
d22b8ed9 MW |
2639 | |
2640 | vme_unregister_bridge(tsi148_bridge); | |
2641 | ||
29848ac9 | 2642 | tsi148_crcsr_exit(tsi148_bridge, pdev); |
d22b8ed9 MW |
2643 | |
2644 | /* resources are stored in link list */ | |
b558ba2f | 2645 | list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) { |
d22b8ed9 MW |
2646 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); |
2647 | list_del(pos); | |
2648 | kfree(dma_ctrlr); | |
2649 | } | |
2650 | ||
2651 | /* resources are stored in link list */ | |
b558ba2f | 2652 | list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) { |
d22b8ed9 MW |
2653 | slave_image = list_entry(pos, struct vme_slave_resource, list); |
2654 | list_del(pos); | |
2655 | kfree(slave_image); | |
2656 | } | |
2657 | ||
2658 | /* resources are stored in link list */ | |
b558ba2f | 2659 | list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) { |
638f199d MW |
2660 | master_image = list_entry(pos, struct vme_master_resource, |
2661 | list); | |
d22b8ed9 MW |
2662 | list_del(pos); |
2663 | kfree(master_image); | |
2664 | } | |
2665 | ||
29848ac9 | 2666 | iounmap(bridge->base); |
d22b8ed9 MW |
2667 | |
2668 | pci_release_regions(pdev); | |
2669 | ||
2670 | pci_disable_device(pdev); | |
2671 | ||
29848ac9 MW |
2672 | kfree(tsi148_bridge->driver_priv); |
2673 | ||
d22b8ed9 MW |
2674 | kfree(tsi148_bridge); |
2675 | } | |
2676 | ||
01c07143 | 2677 | module_pci_driver(tsi148_driver); |
d22b8ed9 MW |
2678 | |
2679 | MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes"); | |
2680 | module_param(err_chk, bool, 0); | |
2681 | ||
638f199d MW |
2682 | MODULE_PARM_DESC(geoid, "Override geographical addressing"); |
2683 | module_param(geoid, int, 0); | |
2684 | ||
d22b8ed9 MW |
2685 | MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge"); |
2686 | MODULE_LICENSE("GPL"); |