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60479690 MW |
1 | /* |
2 | * ca91c042.h | |
3 | * | |
4 | * Support for the Tundra Universe 1 and Universe II VME bridge chips | |
5 | * | |
6 | * Author: Tom Armistead | |
3d0f8bc7 | 7 | * Updated by Ajit Prem |
60479690 MW |
8 | * Copyright 2004 Motorola Inc. |
9 | * | |
66bd8db5 MW |
10 | * Further updated by Martyn Welch <martyn.welch@ge.com> |
11 | * Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc. | |
3d0f8bc7 | 12 | * |
60479690 MW |
13 | * Derived from ca91c042.h by Michael Wyrick |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | */ | |
20 | ||
3d0f8bc7 MW |
21 | #ifndef _CA91CX42_H |
22 | #define _CA91CX42_H | |
60479690 MW |
23 | |
24 | #ifndef PCI_VENDOR_ID_TUNDRA | |
25 | #define PCI_VENDOR_ID_TUNDRA 0x10e3 | |
26 | #endif | |
27 | ||
3d0f8bc7 MW |
28 | #ifndef PCI_DEVICE_ID_TUNDRA_CA91C142 |
29 | #define PCI_DEVICE_ID_TUNDRA_CA91C142 0x0000 | |
60479690 MW |
30 | #endif |
31 | ||
60479690 | 32 | /* |
3d0f8bc7 | 33 | * Define the number of each that the CA91C142 supports. |
60479690 | 34 | */ |
3d0f8bc7 MW |
35 | #define CA91C142_MAX_MASTER 8 /* Max Master Windows */ |
36 | #define CA91C142_MAX_SLAVE 8 /* Max Slave Windows */ | |
37 | #define CA91C142_MAX_DMA 1 /* Max DMA Controllers */ | |
38 | #define CA91C142_MAX_MAILBOX 4 /* Max Mail Box registers */ | |
39 | ||
29848ac9 MW |
40 | /* Structure used to hold driver specific information */ |
41 | struct ca91cx42_driver { | |
e08e02fa | 42 | void __iomem *base; /* Base Address of device registers */ |
29848ac9 MW |
43 | wait_queue_head_t dma_queue; |
44 | wait_queue_head_t iack_queue; | |
45 | wait_queue_head_t mbox_queue; | |
fa54b326 AS |
46 | void (*lm_callback[4])(void *); /* Called in interrupt handler */ |
47 | void *lm_data[4]; | |
29848ac9 MW |
48 | void *crcsr_kernel; |
49 | dma_addr_t crcsr_bus; | |
50 | struct mutex vme_rmw; /* Only one RMW cycle at a time */ | |
51 | struct mutex vme_int; /* | |
52 | * Only one VME interrupt can be | |
53 | * generated at a time, provide locking | |
54 | */ | |
55 | }; | |
56 | ||
3d0f8bc7 MW |
57 | /* See Page 2-77 in the Universe User Manual */ |
58 | struct ca91cx42_dma_descriptor { | |
59 | unsigned int dctl; /* DMA Control */ | |
60 | unsigned int dtbc; /* Transfer Byte Count */ | |
4860ab74 | 61 | unsigned int dla; /* PCI Address */ |
3d0f8bc7 MW |
62 | unsigned int res1; /* Reserved */ |
63 | unsigned int dva; /* Vme Address */ | |
64 | unsigned int res2; /* Reserved */ | |
65 | unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ | |
66 | unsigned int res3; /* Reserved */ | |
67 | }; | |
68 | ||
69 | struct ca91cx42_dma_entry { | |
70 | struct ca91cx42_dma_descriptor descriptor; | |
71 | struct list_head list; | |
72 | }; | |
60479690 MW |
73 | |
74 | /* Universe Register Offsets */ | |
75 | /* general PCI configuration registers */ | |
3d0f8bc7 MW |
76 | #define CA91CX42_PCI_ID 0x000 |
77 | #define CA91CX42_PCI_CSR 0x004 | |
78 | #define CA91CX42_PCI_CLASS 0x008 | |
79 | #define CA91CX42_PCI_MISC0 0x00C | |
80 | #define CA91CX42_PCI_BS 0x010 | |
81 | #define CA91CX42_PCI_MISC1 0x03C | |
82 | ||
83 | #define LSI0_CTL 0x0100 | |
84 | #define LSI0_BS 0x0104 | |
85 | #define LSI0_BD 0x0108 | |
86 | #define LSI0_TO 0x010C | |
87 | ||
88 | #define LSI1_CTL 0x0114 | |
89 | #define LSI1_BS 0x0118 | |
90 | #define LSI1_BD 0x011C | |
91 | #define LSI1_TO 0x0120 | |
92 | ||
93 | #define LSI2_CTL 0x0128 | |
94 | #define LSI2_BS 0x012C | |
95 | #define LSI2_BD 0x0130 | |
96 | #define LSI2_TO 0x0134 | |
97 | ||
98 | #define LSI3_CTL 0x013C | |
99 | #define LSI3_BS 0x0140 | |
100 | #define LSI3_BD 0x0144 | |
101 | #define LSI3_TO 0x0148 | |
102 | ||
103 | #define LSI4_CTL 0x01A0 | |
104 | #define LSI4_BS 0x01A4 | |
105 | #define LSI4_BD 0x01A8 | |
106 | #define LSI4_TO 0x01AC | |
107 | ||
108 | #define LSI5_CTL 0x01B4 | |
109 | #define LSI5_BS 0x01B8 | |
110 | #define LSI5_BD 0x01BC | |
111 | #define LSI5_TO 0x01C0 | |
112 | ||
113 | #define LSI6_CTL 0x01C8 | |
114 | #define LSI6_BS 0x01CC | |
115 | #define LSI6_BD 0x01D0 | |
116 | #define LSI6_TO 0x01D4 | |
117 | ||
118 | #define LSI7_CTL 0x01DC | |
119 | #define LSI7_BS 0x01E0 | |
120 | #define LSI7_BD 0x01E4 | |
121 | #define LSI7_TO 0x01E8 | |
122 | ||
123 | static const int CA91CX42_LSI_CTL[] = { LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL, | |
124 | LSI4_CTL, LSI5_CTL, LSI6_CTL, LSI7_CTL }; | |
125 | ||
126 | static const int CA91CX42_LSI_BS[] = { LSI0_BS, LSI1_BS, LSI2_BS, LSI3_BS, | |
127 | LSI4_BS, LSI5_BS, LSI6_BS, LSI7_BS }; | |
128 | ||
129 | static const int CA91CX42_LSI_BD[] = { LSI0_BD, LSI1_BD, LSI2_BD, LSI3_BD, | |
130 | LSI4_BD, LSI5_BD, LSI6_BD, LSI7_BD }; | |
131 | ||
132 | static const int CA91CX42_LSI_TO[] = { LSI0_TO, LSI1_TO, LSI2_TO, LSI3_TO, | |
133 | LSI4_TO, LSI5_TO, LSI6_TO, LSI7_TO }; | |
60479690 MW |
134 | |
135 | #define SCYC_CTL 0x0170 | |
136 | #define SCYC_ADDR 0x0174 | |
137 | #define SCYC_EN 0x0178 | |
138 | #define SCYC_CMP 0x017C | |
139 | #define SCYC_SWP 0x0180 | |
140 | #define LMISC 0x0184 | |
60479690 | 141 | #define SLSI 0x0188 |
60479690 MW |
142 | #define L_CMDERR 0x018C |
143 | #define LAERR 0x0190 | |
144 | ||
145 | #define DCTL 0x0200 | |
146 | #define DTBC 0x0204 | |
147 | #define DLA 0x0208 | |
148 | #define DVA 0x0210 | |
149 | #define DCPP 0x0218 | |
150 | #define DGCS 0x0220 | |
151 | #define D_LLUE 0x0224 | |
152 | ||
3d0f8bc7 MW |
153 | #define LINT_EN 0x0300 |
154 | #define LINT_STAT 0x0304 | |
155 | #define LINT_MAP0 0x0308 | |
156 | #define LINT_MAP1 0x030C | |
157 | #define VINT_EN 0x0310 | |
158 | #define VINT_STAT 0x0314 | |
159 | #define VINT_MAP0 0x0318 | |
160 | #define VINT_MAP1 0x031C | |
161 | #define STATID 0x0320 | |
162 | ||
163 | #define V1_STATID 0x0324 | |
164 | #define V2_STATID 0x0328 | |
165 | #define V3_STATID 0x032C | |
166 | #define V4_STATID 0x0330 | |
167 | #define V5_STATID 0x0334 | |
168 | #define V6_STATID 0x0338 | |
169 | #define V7_STATID 0x033C | |
170 | ||
171 | static const int CA91CX42_V_STATID[8] = { 0, V1_STATID, V2_STATID, V3_STATID, | |
172 | V4_STATID, V5_STATID, V6_STATID, | |
173 | V7_STATID }; | |
174 | ||
175 | #define LINT_MAP2 0x0340 | |
176 | #define VINT_MAP2 0x0344 | |
177 | ||
178 | #define MBOX0 0x0348 | |
179 | #define MBOX1 0x034C | |
180 | #define MBOX2 0x0350 | |
181 | #define MBOX3 0x0354 | |
182 | #define SEMA0 0x0358 | |
183 | #define SEMA1 0x035C | |
184 | ||
185 | #define MAST_CTL 0x0400 | |
186 | #define MISC_CTL 0x0404 | |
187 | #define MISC_STAT 0x0408 | |
188 | #define USER_AM 0x040C | |
189 | ||
190 | #define VSI0_CTL 0x0F00 | |
191 | #define VSI0_BS 0x0F04 | |
192 | #define VSI0_BD 0x0F08 | |
193 | #define VSI0_TO 0x0F0C | |
194 | ||
195 | #define VSI1_CTL 0x0F14 | |
196 | #define VSI1_BS 0x0F18 | |
197 | #define VSI1_BD 0x0F1C | |
198 | #define VSI1_TO 0x0F20 | |
199 | ||
200 | #define VSI2_CTL 0x0F28 | |
201 | #define VSI2_BS 0x0F2C | |
202 | #define VSI2_BD 0x0F30 | |
203 | #define VSI2_TO 0x0F34 | |
204 | ||
205 | #define VSI3_CTL 0x0F3C | |
206 | #define VSI3_BS 0x0F40 | |
207 | #define VSI3_BD 0x0F44 | |
208 | #define VSI3_TO 0x0F48 | |
209 | ||
210 | #define LM_CTL 0x0F64 | |
211 | #define LM_BS 0x0F68 | |
212 | ||
213 | #define VRAI_CTL 0x0F70 | |
214 | ||
215 | #define VRAI_BS 0x0F74 | |
216 | #define VCSR_CTL 0x0F80 | |
217 | #define VCSR_TO 0x0F84 | |
218 | #define V_AMERR 0x0F88 | |
60479690 MW |
219 | #define VAERR 0x0F8C |
220 | ||
3d0f8bc7 MW |
221 | #define VSI4_CTL 0x0F90 |
222 | #define VSI4_BS 0x0F94 | |
223 | #define VSI4_BD 0x0F98 | |
224 | #define VSI4_TO 0x0F9C | |
225 | ||
226 | #define VSI5_CTL 0x0FA4 | |
227 | #define VSI5_BS 0x0FA8 | |
228 | #define VSI5_BD 0x0FAC | |
229 | #define VSI5_TO 0x0FB0 | |
230 | ||
231 | #define VSI6_CTL 0x0FB8 | |
232 | #define VSI6_BS 0x0FBC | |
233 | #define VSI6_BD 0x0FC0 | |
234 | #define VSI6_TO 0x0FC4 | |
235 | ||
236 | #define VSI7_CTL 0x0FCC | |
237 | #define VSI7_BS 0x0FD0 | |
238 | #define VSI7_BD 0x0FD4 | |
239 | #define VSI7_TO 0x0FD8 | |
240 | ||
241 | static const int CA91CX42_VSI_CTL[] = { VSI0_CTL, VSI1_CTL, VSI2_CTL, VSI3_CTL, | |
242 | VSI4_CTL, VSI5_CTL, VSI6_CTL, VSI7_CTL }; | |
60479690 | 243 | |
3d0f8bc7 MW |
244 | static const int CA91CX42_VSI_BS[] = { VSI0_BS, VSI1_BS, VSI2_BS, VSI3_BS, |
245 | VSI4_BS, VSI5_BS, VSI6_BS, VSI7_BS }; | |
60479690 | 246 | |
3d0f8bc7 MW |
247 | static const int CA91CX42_VSI_BD[] = { VSI0_BD, VSI1_BD, VSI2_BD, VSI3_BD, |
248 | VSI4_BD, VSI5_BD, VSI6_BD, VSI7_BD }; | |
60479690 | 249 | |
3d0f8bc7 MW |
250 | static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO, |
251 | VSI4_TO, VSI5_TO, VSI6_TO, VSI7_TO }; | |
60479690 | 252 | |
3d0f8bc7 MW |
253 | #define VCSR_CLR 0x0FF4 |
254 | #define VCSR_SET 0x0FF8 | |
255 | #define VCSR_BS 0x0FFC | |
60479690 | 256 | |
3d0f8bc7 MW |
257 | /* |
258 | * PCI Class Register | |
259 | * offset 008 | |
260 | */ | |
261 | #define CA91CX42_BM_PCI_CLASS_BASE 0xFF000000 | |
262 | #define CA91CX42_OF_PCI_CLASS_BASE 24 | |
263 | #define CA91CX42_BM_PCI_CLASS_SUB 0x00FF0000 | |
264 | #define CA91CX42_OF_PCI_CLASS_SUB 16 | |
265 | #define CA91CX42_BM_PCI_CLASS_PROG 0x0000FF00 | |
266 | #define CA91CX42_OF_PCI_CLASS_PROG 8 | |
267 | #define CA91CX42_BM_PCI_CLASS_RID 0x000000FF | |
268 | #define CA91CX42_OF_PCI_CLASS_RID 0 | |
269 | ||
270 | #define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_I 0 | |
271 | #define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_II 1 | |
272 | ||
273 | /* | |
274 | * PCI Misc Register | |
275 | * offset 00C | |
276 | */ | |
277 | #define CA91CX42_BM_PCI_MISC0_BISTC 0x80000000 | |
278 | #define CA91CX42_BM_PCI_MISC0_SBIST 0x60000000 | |
279 | #define CA91CX42_BM_PCI_MISC0_CCODE 0x0F000000 | |
280 | #define CA91CX42_BM_PCI_MISC0_MFUNCT 0x00800000 | |
281 | #define CA91CX42_BM_PCI_MISC0_LAYOUT 0x007F0000 | |
282 | #define CA91CX42_BM_PCI_MISC0_LTIMER 0x0000FF00 | |
283 | #define CA91CX42_OF_PCI_MISC0_LTIMER 8 | |
284 | ||
285 | ||
286 | /* | |
287 | * LSI Control Register | |
288 | * offset 100 | |
289 | */ | |
290 | #define CA91CX42_LSI_CTL_EN (1<<31) | |
291 | #define CA91CX42_LSI_CTL_PWEN (1<<30) | |
292 | ||
293 | #define CA91CX42_LSI_CTL_VDW_M (3<<22) | |
294 | #define CA91CX42_LSI_CTL_VDW_D8 0 | |
295 | #define CA91CX42_LSI_CTL_VDW_D16 (1<<22) | |
296 | #define CA91CX42_LSI_CTL_VDW_D32 (1<<23) | |
297 | #define CA91CX42_LSI_CTL_VDW_D64 (3<<22) | |
298 | ||
299 | #define CA91CX42_LSI_CTL_VAS_M (7<<16) | |
300 | #define CA91CX42_LSI_CTL_VAS_A16 0 | |
301 | #define CA91CX42_LSI_CTL_VAS_A24 (1<<16) | |
302 | #define CA91CX42_LSI_CTL_VAS_A32 (1<<17) | |
303 | #define CA91CX42_LSI_CTL_VAS_CRCSR (5<<16) | |
304 | #define CA91CX42_LSI_CTL_VAS_USER1 (3<<17) | |
305 | #define CA91CX42_LSI_CTL_VAS_USER2 (7<<16) | |
306 | ||
307 | #define CA91CX42_LSI_CTL_PGM_M (1<<14) | |
308 | #define CA91CX42_LSI_CTL_PGM_DATA 0 | |
309 | #define CA91CX42_LSI_CTL_PGM_PGM (1<<14) | |
310 | ||
311 | #define CA91CX42_LSI_CTL_SUPER_M (1<<12) | |
312 | #define CA91CX42_LSI_CTL_SUPER_NPRIV 0 | |
313 | #define CA91CX42_LSI_CTL_SUPER_SUPR (1<<12) | |
314 | ||
315 | #define CA91CX42_LSI_CTL_VCT_M (1<<8) | |
316 | #define CA91CX42_LSI_CTL_VCT_BLT (1<<8) | |
317 | #define CA91CX42_LSI_CTL_VCT_MBLT (1<<8) | |
318 | #define CA91CX42_LSI_CTL_LAS (1<<0) | |
319 | ||
04e10e15 MW |
320 | /* |
321 | * SCYC_CTL Register | |
322 | * offset 178 | |
323 | */ | |
324 | #define CA91CX42_SCYC_CTL_LAS_PCIMEM 0 | |
325 | #define CA91CX42_SCYC_CTL_LAS_PCIIO (1<<2) | |
326 | ||
327 | #define CA91CX42_SCYC_CTL_CYC_M (3<<0) | |
328 | #define CA91CX42_SCYC_CTL_CYC_RMW (1<<0) | |
329 | #define CA91CX42_SCYC_CTL_CYC_ADOH (1<<1) | |
3d0f8bc7 MW |
330 | |
331 | /* | |
332 | * LMISC Register | |
333 | * offset 184 | |
334 | */ | |
335 | #define CA91CX42_BM_LMISC_CRT 0xF0000000 | |
336 | #define CA91CX42_OF_LMISC_CRT 28 | |
337 | #define CA91CX42_BM_LMISC_CWT 0x0F000000 | |
338 | #define CA91CX42_OF_LMISC_CWT 24 | |
339 | ||
340 | /* | |
341 | * SLSI Register | |
342 | * offset 188 | |
343 | */ | |
344 | #define CA91CX42_BM_SLSI_EN 0x80000000 | |
345 | #define CA91CX42_BM_SLSI_PWEN 0x40000000 | |
346 | #define CA91CX42_BM_SLSI_VDW 0x00F00000 | |
347 | #define CA91CX42_OF_SLSI_VDW 20 | |
348 | #define CA91CX42_BM_SLSI_PGM 0x0000F000 | |
349 | #define CA91CX42_OF_SLSI_PGM 12 | |
350 | #define CA91CX42_BM_SLSI_SUPER 0x00000F00 | |
351 | #define CA91CX42_OF_SLSI_SUPER 8 | |
352 | #define CA91CX42_BM_SLSI_BS 0x000000F6 | |
353 | #define CA91CX42_OF_SLSI_BS 2 | |
354 | #define CA91CX42_BM_SLSI_LAS 0x00000003 | |
355 | #define CA91CX42_OF_SLSI_LAS 0 | |
356 | #define CA91CX42_BM_SLSI_RESERVED 0x3F0F0000 | |
357 | ||
4860ab74 MW |
358 | /* |
359 | * DCTL Register | |
360 | * offset 200 | |
361 | */ | |
362 | #define CA91CX42_DCTL_L2V (1<<31) | |
363 | #define CA91CX42_DCTL_VDW_M (3<<22) | |
4860ab74 MW |
364 | #define CA91CX42_DCTL_VDW_D8 0 |
365 | #define CA91CX42_DCTL_VDW_D16 (1<<22) | |
366 | #define CA91CX42_DCTL_VDW_D32 (1<<23) | |
367 | #define CA91CX42_DCTL_VDW_D64 (3<<22) | |
368 | ||
369 | #define CA91CX42_DCTL_VAS_M (7<<16) | |
370 | #define CA91CX42_DCTL_VAS_A16 0 | |
371 | #define CA91CX42_DCTL_VAS_A24 (1<<16) | |
372 | #define CA91CX42_DCTL_VAS_A32 (1<<17) | |
373 | #define CA91CX42_DCTL_VAS_USER1 (3<<17) | |
374 | #define CA91CX42_DCTL_VAS_USER2 (7<<16) | |
375 | ||
376 | #define CA91CX42_DCTL_PGM_M (1<<14) | |
377 | #define CA91CX42_DCTL_PGM_DATA 0 | |
378 | #define CA91CX42_DCTL_PGM_PGM (1<<14) | |
379 | ||
380 | #define CA91CX42_DCTL_SUPER_M (1<<12) | |
381 | #define CA91CX42_DCTL_SUPER_NPRIV 0 | |
382 | #define CA91CX42_DCTL_SUPER_SUPR (1<<12) | |
383 | ||
384 | #define CA91CX42_DCTL_VCT_M (1<<8) | |
385 | #define CA91CX42_DCTL_VCT_BLT (1<<8) | |
386 | #define CA91CX42_DCTL_LD64EN (1<<7) | |
387 | ||
388 | /* | |
389 | * DCPP Register | |
390 | * offset 218 | |
391 | */ | |
392 | #define CA91CX42_DCPP_M 0xf | |
393 | #define CA91CX42_DCPP_NULL (1<<0) | |
394 | ||
395 | /* | |
396 | * DMA General Control/Status Register (DGCS) | |
397 | * offset 220 | |
398 | */ | |
399 | #define CA91CX42_DGCS_GO (1<<31) | |
400 | #define CA91CX42_DGCS_STOP_REQ (1<<30) | |
401 | #define CA91CX42_DGCS_HALT_REQ (1<<29) | |
402 | #define CA91CX42_DGCS_CHAIN (1<<27) | |
403 | ||
404 | #define CA91CX42_DGCS_VON_M (7<<20) | |
405 | ||
406 | #define CA91CX42_DGCS_VOFF_M (0xf<<16) | |
407 | ||
408 | #define CA91CX42_DGCS_ACT (1<<15) | |
409 | #define CA91CX42_DGCS_STOP (1<<14) | |
410 | #define CA91CX42_DGCS_HALT (1<<13) | |
411 | #define CA91CX42_DGCS_DONE (1<<11) | |
412 | #define CA91CX42_DGCS_LERR (1<<10) | |
413 | #define CA91CX42_DGCS_VERR (1<<9) | |
414 | #define CA91CX42_DGCS_PERR (1<<8) | |
415 | #define CA91CX42_DGCS_INT_STOP (1<<6) | |
416 | #define CA91CX42_DGCS_INT_HALT (1<<5) | |
417 | #define CA91CX42_DGCS_INT_DONE (1<<3) | |
418 | #define CA91CX42_DGCS_INT_LERR (1<<2) | |
419 | #define CA91CX42_DGCS_INT_VERR (1<<1) | |
420 | #define CA91CX42_DGCS_INT_PERR (1<<0) | |
421 | ||
3d0f8bc7 MW |
422 | /* |
423 | * PCI Interrupt Enable Register | |
424 | * offset 300 | |
425 | */ | |
426 | #define CA91CX42_LINT_LM3 0x00800000 | |
427 | #define CA91CX42_LINT_LM2 0x00400000 | |
428 | #define CA91CX42_LINT_LM1 0x00200000 | |
429 | #define CA91CX42_LINT_LM0 0x00100000 | |
430 | #define CA91CX42_LINT_MBOX3 0x00080000 | |
431 | #define CA91CX42_LINT_MBOX2 0x00040000 | |
432 | #define CA91CX42_LINT_MBOX1 0x00020000 | |
433 | #define CA91CX42_LINT_MBOX0 0x00010000 | |
434 | #define CA91CX42_LINT_ACFAIL 0x00008000 | |
435 | #define CA91CX42_LINT_SYSFAIL 0x00004000 | |
436 | #define CA91CX42_LINT_SW_INT 0x00002000 | |
437 | #define CA91CX42_LINT_SW_IACK 0x00001000 | |
438 | ||
439 | #define CA91CX42_LINT_VERR 0x00000400 | |
440 | #define CA91CX42_LINT_LERR 0x00000200 | |
441 | #define CA91CX42_LINT_DMA 0x00000100 | |
442 | #define CA91CX42_LINT_VIRQ7 0x00000080 | |
443 | #define CA91CX42_LINT_VIRQ6 0x00000040 | |
444 | #define CA91CX42_LINT_VIRQ5 0x00000020 | |
445 | #define CA91CX42_LINT_VIRQ4 0x00000010 | |
446 | #define CA91CX42_LINT_VIRQ3 0x00000008 | |
447 | #define CA91CX42_LINT_VIRQ2 0x00000004 | |
448 | #define CA91CX42_LINT_VIRQ1 0x00000002 | |
449 | #define CA91CX42_LINT_VOWN 0x00000001 | |
450 | ||
451 | static const int CA91CX42_LINT_VIRQ[] = { 0, CA91CX42_LINT_VIRQ1, | |
452 | CA91CX42_LINT_VIRQ2, CA91CX42_LINT_VIRQ3, | |
453 | CA91CX42_LINT_VIRQ4, CA91CX42_LINT_VIRQ5, | |
454 | CA91CX42_LINT_VIRQ6, CA91CX42_LINT_VIRQ7 }; | |
455 | ||
456 | #define CA91CX42_LINT_MBOX 0x000F0000 | |
457 | ||
458 | static const int CA91CX42_LINT_LM[] = { CA91CX42_LINT_LM0, CA91CX42_LINT_LM1, | |
459 | CA91CX42_LINT_LM2, CA91CX42_LINT_LM3 }; | |
460 | ||
461 | /* | |
462 | * MAST_CTL Register | |
463 | * offset 400 | |
464 | */ | |
465 | #define CA91CX42_BM_MAST_CTL_MAXRTRY 0xF0000000 | |
466 | #define CA91CX42_OF_MAST_CTL_MAXRTRY 28 | |
467 | #define CA91CX42_BM_MAST_CTL_PWON 0x0F000000 | |
468 | #define CA91CX42_OF_MAST_CTL_PWON 24 | |
469 | #define CA91CX42_BM_MAST_CTL_VRL 0x00C00000 | |
470 | #define CA91CX42_OF_MAST_CTL_VRL 22 | |
471 | #define CA91CX42_BM_MAST_CTL_VRM 0x00200000 | |
472 | #define CA91CX42_BM_MAST_CTL_VREL 0x00100000 | |
473 | #define CA91CX42_BM_MAST_CTL_VOWN 0x00080000 | |
474 | #define CA91CX42_BM_MAST_CTL_VOWN_ACK 0x00040000 | |
475 | #define CA91CX42_BM_MAST_CTL_PABS 0x00001000 | |
476 | #define CA91CX42_BM_MAST_CTL_BUS_NO 0x0000000F | |
477 | #define CA91CX42_OF_MAST_CTL_BUS_NO 0 | |
478 | ||
479 | /* | |
480 | * MISC_CTL Register | |
481 | * offset 404 | |
482 | */ | |
483 | #define CA91CX42_MISC_CTL_VBTO 0xF0000000 | |
484 | #define CA91CX42_MISC_CTL_VARB 0x04000000 | |
485 | #define CA91CX42_MISC_CTL_VARBTO 0x03000000 | |
486 | #define CA91CX42_MISC_CTL_SW_LRST 0x00800000 | |
487 | #define CA91CX42_MISC_CTL_SW_SRST 0x00400000 | |
488 | #define CA91CX42_MISC_CTL_BI 0x00100000 | |
489 | #define CA91CX42_MISC_CTL_ENGBI 0x00080000 | |
490 | #define CA91CX42_MISC_CTL_RESCIND 0x00040000 | |
491 | #define CA91CX42_MISC_CTL_SYSCON 0x00020000 | |
492 | #define CA91CX42_MISC_CTL_V64AUTO 0x00010000 | |
493 | #define CA91CX42_MISC_CTL_RESERVED 0x0820FFFF | |
494 | ||
495 | #define CA91CX42_OF_MISC_CTL_VARBTO 24 | |
496 | #define CA91CX42_OF_MISC_CTL_VBTO 28 | |
497 | ||
498 | /* | |
499 | * MISC_STAT Register | |
500 | * offset 408 | |
501 | */ | |
502 | #define CA91CX42_BM_MISC_STAT_ENDIAN 0x80000000 | |
503 | #define CA91CX42_BM_MISC_STAT_LCLSIZE 0x40000000 | |
504 | #define CA91CX42_BM_MISC_STAT_DY4AUTO 0x08000000 | |
505 | #define CA91CX42_BM_MISC_STAT_MYBBSY 0x00200000 | |
506 | #define CA91CX42_BM_MISC_STAT_DY4DONE 0x00080000 | |
507 | #define CA91CX42_BM_MISC_STAT_TXFE 0x00040000 | |
508 | #define CA91CX42_BM_MISC_STAT_RXFE 0x00020000 | |
509 | #define CA91CX42_BM_MISC_STAT_DY4AUTOID 0x0000FF00 | |
510 | #define CA91CX42_OF_MISC_STAT_DY4AUTOID 8 | |
511 | ||
512 | /* | |
513 | * VSI Control Register | |
514 | * offset F00 | |
515 | */ | |
516 | #define CA91CX42_VSI_CTL_EN (1<<31) | |
517 | #define CA91CX42_VSI_CTL_PWEN (1<<30) | |
518 | #define CA91CX42_VSI_CTL_PREN (1<<29) | |
519 | ||
520 | #define CA91CX42_VSI_CTL_PGM_M (3<<22) | |
521 | #define CA91CX42_VSI_CTL_PGM_DATA (1<<22) | |
522 | #define CA91CX42_VSI_CTL_PGM_PGM (1<<23) | |
523 | ||
524 | #define CA91CX42_VSI_CTL_SUPER_M (3<<20) | |
525 | #define CA91CX42_VSI_CTL_SUPER_NPRIV (1<<20) | |
526 | #define CA91CX42_VSI_CTL_SUPER_SUPR (1<<21) | |
527 | ||
528 | #define CA91CX42_VSI_CTL_VAS_M (7<<16) | |
529 | #define CA91CX42_VSI_CTL_VAS_A16 0 | |
530 | #define CA91CX42_VSI_CTL_VAS_A24 (1<<16) | |
531 | #define CA91CX42_VSI_CTL_VAS_A32 (1<<17) | |
532 | #define CA91CX42_VSI_CTL_VAS_USER1 (3<<17) | |
533 | #define CA91CX42_VSI_CTL_VAS_USER2 (7<<16) | |
534 | ||
535 | #define CA91CX42_VSI_CTL_LD64EN (1<<7) | |
536 | #define CA91CX42_VSI_CTL_LLRMW (1<<6) | |
537 | ||
538 | #define CA91CX42_VSI_CTL_LAS_M (3<<0) | |
539 | #define CA91CX42_VSI_CTL_LAS_PCI_MS 0 | |
540 | #define CA91CX42_VSI_CTL_LAS_PCI_IO (1<<0) | |
541 | #define CA91CX42_VSI_CTL_LAS_PCI_CONF (1<<1) | |
542 | ||
2b82beb8 MW |
543 | /* LM_CTL Register |
544 | * offset F64 | |
545 | */ | |
546 | #define CA91CX42_LM_CTL_EN (1<<31) | |
547 | #define CA91CX42_LM_CTL_PGM (1<<23) | |
548 | #define CA91CX42_LM_CTL_DATA (1<<22) | |
549 | #define CA91CX42_LM_CTL_SUPR (1<<21) | |
550 | #define CA91CX42_LM_CTL_NPRIV (1<<20) | |
5a2f8831 | 551 | #define CA91CX42_LM_CTL_AS_M (7<<16) |
2b82beb8 MW |
552 | #define CA91CX42_LM_CTL_AS_A16 0 |
553 | #define CA91CX42_LM_CTL_AS_A24 (1<<16) | |
554 | #define CA91CX42_LM_CTL_AS_A32 (1<<17) | |
555 | ||
3d0f8bc7 MW |
556 | /* |
557 | * VRAI_CTL Register | |
558 | * offset F70 | |
559 | */ | |
560 | #define CA91CX42_BM_VRAI_CTL_EN 0x80000000 | |
561 | #define CA91CX42_BM_VRAI_CTL_PGM 0x00C00000 | |
562 | #define CA91CX42_OF_VRAI_CTL_PGM 22 | |
563 | #define CA91CX42_BM_VRAI_CTL_SUPER 0x00300000 | |
564 | #define CA91CX42_OF_VRAI_CTL_SUPER 20 | |
565 | #define CA91CX42_BM_VRAI_CTL_VAS 0x00030000 | |
566 | #define CA91CX42_OF_VRAI_CTL_VAS 16 | |
567 | ||
568 | /* VCSR_CTL Register | |
569 | * offset F80 | |
570 | */ | |
571 | #define CA91CX42_VCSR_CTL_EN (1<<31) | |
572 | ||
573 | #define CA91CX42_VCSR_CTL_LAS_M (3<<0) | |
574 | #define CA91CX42_VCSR_CTL_LAS_PCI_MS 0 | |
575 | #define CA91CX42_VCSR_CTL_LAS_PCI_IO (1<<0) | |
576 | #define CA91CX42_VCSR_CTL_LAS_PCI_CONF (1<<1) | |
577 | ||
578 | /* VCSR_BS Register | |
579 | * offset FFC | |
580 | */ | |
581 | #define CA91CX42_VCSR_BS_SLOT_M (0x1F<<27) | |
582 | ||
583 | #endif /* _CA91CX42_H */ |