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Merge branch 'for-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq
[linux-2.6-block.git] / drivers / vme / bridges / vme_ca91cx42.c
CommitLineData
60479690
MW		 1/*
2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
3 *
66bd8db5
MW		 4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
60479690
MW		 6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * Derived from ca91c042.c by Michael Wyrick
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
60479690
MW		 18#include <linux/module.h>
19#include <linux/mm.h>
20#include <linux/types.h>
21#include <linux/errno.h>
60479690
MW		 22#include <linux/pci.h>
23#include <linux/dma-mapping.h>
24#include <linux/poll.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
6af783c8 27#include <linux/sched.h>
5a0e3ad6 28#include <linux/slab.h>
7946328f
MW		 29#include <linux/time.h>
30#include <linux/io.h>
31#include <linux/uaccess.h>
db3b9e99 32#include <linux/vme.h>
60479690 33
60479690
MW		 34#include "../vme_bridge.h"
35#include "vme_ca91cx42.h"
36
3d0f8bc7
MW		 37static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
38static void ca91cx42_remove(struct pci_dev *);
60479690 39
12b2d5c0
MW		 40/* Module parameters */
41static int geoid;
42
584721ca 43static const char driver_name[] = "vme_ca91cx42";
60479690 44
c3a09c18 45static const struct pci_device_id ca91cx42_ids[] = {
3d0f8bc7
MW		 46 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
47 { },
60479690
MW		 48};
49
3d0f8bc7
MW		 50static struct pci_driver ca91cx42_driver = {
51 .name = driver_name,
52 .id_table = ca91cx42_ids,
53 .probe = ca91cx42_probe,
54 .remove = ca91cx42_remove,
60479690
MW		 55};
56
29848ac9 57static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
60479690 58{
886953e9 59 wake_up(&bridge->dma_queue);
60479690 60
3d0f8bc7
MW		 61 return CA91CX42_LINT_DMA;
62}
60479690 63
29848ac9 64static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
3d0f8bc7
MW		 65{
66 int i;
67 u32 serviced = 0;
60479690 68
3d0f8bc7
MW		 69 for (i = 0; i < 4; i++) {
70 if (stat & CA91CX42_LINT_LM[i]) {
71 /* We only enable interrupts if the callback is set */
29848ac9 72 bridge->lm_callback[i](i);
3d0f8bc7 73 serviced |= CA91CX42_LINT_LM[i];
60479690 74 }
60479690 75 }
60479690 76
3d0f8bc7
MW		 77 return serviced;
78}
60479690 79
3d0f8bc7 80/* XXX This needs to be split into 4 queues */
29848ac9 81static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
3d0f8bc7 82{
886953e9 83 wake_up(&bridge->mbox_queue);
60479690 84
3d0f8bc7
MW		 85 return CA91CX42_LINT_MBOX;
86}
60479690 87
29848ac9 88static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
3d0f8bc7 89{
886953e9 90 wake_up(&bridge->iack_queue);
60479690 91
3d0f8bc7 92 return CA91CX42_LINT_SW_IACK;
60479690
MW		 93}
94
48d9356e 95static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
60479690
MW		 96{
97 int val;
48d9356e
MW		 98 struct ca91cx42_driver *bridge;
99
100 bridge = ca91cx42_bridge->driver_priv;
60479690 101
29848ac9 102 val = ioread32(bridge->base + DGCS);
60479690
MW		 103
104 if (!(val & 0x00000800)) {
48d9356e
MW		 105 dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA "
106 "Read Error DGCS=%08X\n", val);
60479690 107 }
3d0f8bc7
MW		 108
109 return CA91CX42_LINT_VERR;
60479690
MW		 110}
111
48d9356e 112static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
60479690
MW		 113{
114 int val;
48d9356e 115 struct ca91cx42_driver *bridge;
60479690 116
48d9356e 117 bridge = ca91cx42_bridge->driver_priv;
60479690 118
48d9356e 119 val = ioread32(bridge->base + DGCS);
60479690 120
48d9356e
MW		 121 if (!(val & 0x00000800))
122 dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA "
123 "Read Error DGCS=%08X\n", val);
60479690 124
3d0f8bc7 125 return CA91CX42_LINT_LERR;
60479690
MW		 126}
127
3d0f8bc7 128
29848ac9
MW		 129static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
130 int stat)
60479690 131{
3d0f8bc7 132 int vec, i, serviced = 0;
29848ac9
MW		 133 struct ca91cx42_driver *bridge;
134
135 bridge = ca91cx42_bridge->driver_priv;
136
60479690
MW		 137
138 for (i = 7; i > 0; i--) {
3d0f8bc7 139 if (stat & (1 << i)) {
29848ac9 140 vec = ioread32(bridge->base +
3d0f8bc7
MW		 141 CA91CX42_V_STATID[i]) & 0xff;
142
c813f592 143 vme_irq_handler(ca91cx42_bridge, i, vec);
3d0f8bc7
MW		 144
145 serviced |= (1 << i);
60479690
MW		 146 }
147 }
3d0f8bc7
MW		 148
149 return serviced;
60479690
MW		 150}
151
29848ac9 152static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
60479690 153{
3d0f8bc7 154 u32 stat, enable, serviced = 0;
29848ac9
MW		 155 struct vme_bridge *ca91cx42_bridge;
156 struct ca91cx42_driver *bridge;
60479690 157
29848ac9 158 ca91cx42_bridge = ptr;
60479690 159
29848ac9
MW		 160 bridge = ca91cx42_bridge->driver_priv;
161
162 enable = ioread32(bridge->base + LINT_EN);
163 stat = ioread32(bridge->base + LINT_STAT);
60479690 164
3d0f8bc7
MW		 165 /* Only look at unmasked interrupts */
166 stat &= enable;
167
168 if (unlikely(!stat))
169 return IRQ_NONE;
170
171 if (stat & CA91CX42_LINT_DMA)
29848ac9 172 serviced |= ca91cx42_DMA_irqhandler(bridge);
3d0f8bc7
MW		 173 if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
174 CA91CX42_LINT_LM3))
29848ac9 175 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
3d0f8bc7 176 if (stat & CA91CX42_LINT_MBOX)
29848ac9 177 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
3d0f8bc7 178 if (stat & CA91CX42_LINT_SW_IACK)
29848ac9 179 serviced |= ca91cx42_IACK_irqhandler(bridge);
3d0f8bc7 180 if (stat & CA91CX42_LINT_VERR)
48d9356e 181 serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge);
3d0f8bc7 182 if (stat & CA91CX42_LINT_LERR)
48d9356e 183 serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge);
3d0f8bc7
MW		 184 if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
185 CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
186 CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
187 CA91CX42_LINT_VIRQ7))
29848ac9 188 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
3d0f8bc7
MW		 189
190 /* Clear serviced interrupts */
56fc5081 191 iowrite32(serviced, bridge->base + LINT_STAT);
60479690
MW		 192
193 return IRQ_HANDLED;
194}
195
29848ac9 196static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
60479690 197{
3d0f8bc7
MW		 198 int result, tmp;
199 struct pci_dev *pdev;
29848ac9
MW		 200 struct ca91cx42_driver *bridge;
201
202 bridge = ca91cx42_bridge->driver_priv;
60479690 203
3d0f8bc7 204 /* Need pdev */
29848ac9 205 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
60479690 206
3d0f8bc7 207 /* Initialise list for VME bus errors */
886953e9 208 INIT_LIST_HEAD(&ca91cx42_bridge->vme_errors);
60479690 209
886953e9 210 mutex_init(&ca91cx42_bridge->irq_mtx);
c813f592 211
3d0f8bc7
MW		 212 /* Disable interrupts from PCI to VME */
213 iowrite32(0, bridge->base + VINT_EN);
60479690 214
3d0f8bc7
MW		 215 /* Disable PCI interrupts */
216 iowrite32(0, bridge->base + LINT_EN);
217 /* Clear Any Pending PCI Interrupts */
218 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
60479690 219
3d0f8bc7 220 result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
29848ac9 221 driver_name, ca91cx42_bridge);
3d0f8bc7
MW		 222 if (result) {
223 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
224 pdev->irq);
225 return result;
60479690
MW		 226 }
227
3d0f8bc7
MW		 228 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
229 iowrite32(0, bridge->base + LINT_MAP0);
230 iowrite32(0, bridge->base + LINT_MAP1);
231 iowrite32(0, bridge->base + LINT_MAP2);
232
233 /* Enable DMA, mailbox & LM Interrupts */
234 tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
235 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
236 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
237
238 iowrite32(tmp, bridge->base + LINT_EN);
60479690 239
3d0f8bc7 240 return 0;
60479690
MW		 241}
242
29848ac9
MW		 243static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
244 struct pci_dev *pdev)
60479690 245{
ef22d576
WY		 246 struct vme_bridge *ca91cx42_bridge;
247
3d0f8bc7 248 /* Disable interrupts from PCI to VME */
29848ac9 249 iowrite32(0, bridge->base + VINT_EN);
60479690 250
3d0f8bc7 251 /* Disable PCI interrupts */
29848ac9 252 iowrite32(0, bridge->base + LINT_EN);
3d0f8bc7 253 /* Clear Any Pending PCI Interrupts */
29848ac9 254 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
60479690 255
ef22d576
WY		 256 ca91cx42_bridge = container_of((void *)bridge, struct vme_bridge,
257 driver_priv);
258 free_irq(pdev->irq, ca91cx42_bridge);
3d0f8bc7 259}
60479690 260
54b4a779
VB		 261static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level)
262{
263 u32 tmp;
264
265 tmp = ioread32(bridge->base + LINT_STAT);
266
267 if (tmp & (1 << level))
268 return 0;
269 else
270 return 1;
271}
272
3d0f8bc7
MW		 273/*
274 * Set up an VME interrupt
275 */
efbb979d
EC		 276static void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level,
277 int state, int sync)
c813f592 278
3d0f8bc7 279{
c813f592 280 struct pci_dev *pdev;
3d0f8bc7 281 u32 tmp;
29848ac9
MW		 282 struct ca91cx42_driver *bridge;
283
284 bridge = ca91cx42_bridge->driver_priv;
60479690 285
3d0f8bc7 286 /* Enable IRQ level */
29848ac9 287 tmp = ioread32(bridge->base + LINT_EN);
3d0f8bc7 288
c813f592 289 if (state == 0)
3d0f8bc7 290 tmp &= ~CA91CX42_LINT_VIRQ[level];
c813f592
MW		 291 else
292 tmp |= CA91CX42_LINT_VIRQ[level];
60479690 293
29848ac9 294 iowrite32(tmp, bridge->base + LINT_EN);
c813f592
MW		 295
296 if ((state == 0) && (sync != 0)) {
3d0f8bc7
MW		 297 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev,
298 dev);
299
300 synchronize_irq(pdev->irq);
60479690 301 }
60479690
MW		 302}
303
efbb979d 304static int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
29848ac9 305 int statid)
60479690 306{
3d0f8bc7 307 u32 tmp;
29848ac9
MW		 308 struct ca91cx42_driver *bridge;
309
310 bridge = ca91cx42_bridge->driver_priv;
60479690 311
3d0f8bc7
MW		 312 /* Universe can only generate even vectors */
313 if (statid & 1)
314 return -EINVAL;
60479690 315
886953e9 316 mutex_lock(&bridge->vme_int);
60479690 317
29848ac9 318 tmp = ioread32(bridge->base + VINT_EN);
60479690 319
3d0f8bc7 320 /* Set Status/ID */
29848ac9 321 iowrite32(statid << 24, bridge->base + STATID);
3d0f8bc7
MW		 322
323 /* Assert VMEbus IRQ */
324 tmp = tmp | (1 << (level + 24));
29848ac9 325 iowrite32(tmp, bridge->base + VINT_EN);
60479690 326
3d0f8bc7 327 /* Wait for IACK */
54b4a779
VB		 328 wait_event_interruptible(bridge->iack_queue,
329 ca91cx42_iack_received(bridge, level));
3d0f8bc7
MW		 330
331 /* Return interrupt to low state */
29848ac9 332 tmp = ioread32(bridge->base + VINT_EN);
3d0f8bc7 333 tmp = tmp & ~(1 << (level + 24));
29848ac9 334 iowrite32(tmp, bridge->base + VINT_EN);
3d0f8bc7 335
886953e9 336 mutex_unlock(&bridge->vme_int);
3d0f8bc7
MW		 337
338 return 0;
60479690
MW		 339}
340
efbb979d 341static int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
3d0f8bc7 342 unsigned long long vme_base, unsigned long long size,
6af04b06 343 dma_addr_t pci_base, u32 aspace, u32 cycle)
60479690 344{
21e0cf6d 345 unsigned int i, addr = 0, granularity;
3d0f8bc7
MW		 346 unsigned int temp_ctl = 0;
347 unsigned int vme_bound, pci_offset;
48d9356e 348 struct vme_bridge *ca91cx42_bridge;
29848ac9
MW		 349 struct ca91cx42_driver *bridge;
350
48d9356e
MW		 351 ca91cx42_bridge = image->parent;
352
353 bridge = ca91cx42_bridge->driver_priv;
60479690 354
3d0f8bc7 355 i = image->number;
60479690 356
3d0f8bc7
MW		 357 switch (aspace) {
358 case VME_A16:
359 addr |= CA91CX42_VSI_CTL_VAS_A16;
360 break;
361 case VME_A24:
362 addr |= CA91CX42_VSI_CTL_VAS_A24;
363 break;
364 case VME_A32:
365 addr |= CA91CX42_VSI_CTL_VAS_A32;
366 break;
367 case VME_USER1:
368 addr |= CA91CX42_VSI_CTL_VAS_USER1;
369 break;
370 case VME_USER2:
371 addr |= CA91CX42_VSI_CTL_VAS_USER2;
372 break;
373 case VME_A64:
374 case VME_CRCSR:
375 case VME_USER3:
376 case VME_USER4:
377 default:
48d9356e 378 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
3d0f8bc7
MW		 379 return -EINVAL;
380 break;
60479690
MW		 381 }
382
3d0f8bc7
MW		 383 /*
384 * Bound address is a valid address for the window, adjust
385 * accordingly
386 */
21e0cf6d 387 vme_bound = vme_base + size;
3d0f8bc7
MW		 388 pci_offset = pci_base - vme_base;
389
3d0f8bc7
MW		 390 if ((i == 0) || (i == 4))
391 granularity = 0x1000;
392 else
393 granularity = 0x10000;
394
395 if (vme_base & (granularity - 1)) {
48d9356e
MW		 396 dev_err(ca91cx42_bridge->parent, "Invalid VME base "
397 "alignment\n");
3d0f8bc7
MW		 398 return -EINVAL;
399 }
400 if (vme_bound & (granularity - 1)) {
48d9356e
MW		 401 dev_err(ca91cx42_bridge->parent, "Invalid VME bound "
402 "alignment\n");
3d0f8bc7
MW		 403 return -EINVAL;
404 }
405 if (pci_offset & (granularity - 1)) {
48d9356e
MW		 406 dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset "
407 "alignment\n");
3d0f8bc7 408 return -EINVAL;
60479690
MW		 409 }
410
3d0f8bc7 411 /* Disable while we are mucking around */
29848ac9 412 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
3d0f8bc7 413 temp_ctl &= ~CA91CX42_VSI_CTL_EN;
29848ac9 414 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
60479690 415
3d0f8bc7 416 /* Setup mapping */
29848ac9
MW		 417 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
418 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
419 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
3d0f8bc7 420
3d0f8bc7
MW		 421 /* Setup address space */
422 temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
423 temp_ctl |= addr;
424
425 /* Setup cycle types */
426 temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
427 if (cycle & VME_SUPER)
428 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
429 if (cycle & VME_USER)
430 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
431 if (cycle & VME_PROG)
432 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
433 if (cycle & VME_DATA)
434 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
435
436 /* Write ctl reg without enable */
29848ac9 437 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
3d0f8bc7
MW		 438
439 if (enabled)
440 temp_ctl |= CA91CX42_VSI_CTL_EN;
441
29848ac9 442 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
3d0f8bc7
MW		 443
444 return 0;
60479690
MW		 445}
446
efbb979d 447static int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
3d0f8bc7 448 unsigned long long *vme_base, unsigned long long *size,
6af04b06 449 dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
60479690 450{
3d0f8bc7
MW		 451 unsigned int i, granularity = 0, ctl = 0;
452 unsigned long long vme_bound, pci_offset;
29848ac9
MW		 453 struct ca91cx42_driver *bridge;
454
455 bridge = image->parent->driver_priv;
3d0f8bc7
MW		 456
457 i = image->number;
60479690 458
3d0f8bc7
MW		 459 if ((i == 0) || (i == 4))
460 granularity = 0x1000;
461 else
462 granularity = 0x10000;
463
464 /* Read Registers */
29848ac9 465 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
3d0f8bc7 466
29848ac9
MW		 467 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
468 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
469 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
3d0f8bc7
MW		 470
471 *pci_base = (dma_addr_t)vme_base + pci_offset;
472 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
473
474 *enabled = 0;
475 *aspace = 0;
476 *cycle = 0;
477
478 if (ctl & CA91CX42_VSI_CTL_EN)
479 *enabled = 1;
480
481 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
482 *aspace = VME_A16;
483 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
484 *aspace = VME_A24;
485 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
486 *aspace = VME_A32;
487 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
488 *aspace = VME_USER1;
489 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
490 *aspace = VME_USER2;
491
492 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
493 *cycle |= VME_SUPER;
494 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
495 *cycle |= VME_USER;
496 if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
497 *cycle |= VME_PROG;
498 if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
499 *cycle |= VME_DATA;
500
501 return 0;
502}
503
504/*
505 * Allocate and map PCI Resource
506 */
507static int ca91cx42_alloc_resource(struct vme_master_resource *image,
508 unsigned long long size)
509{
510 unsigned long long existing_size;
511 int retval = 0;
512 struct pci_dev *pdev;
29848ac9
MW		 513 struct vme_bridge *ca91cx42_bridge;
514
515 ca91cx42_bridge = image->parent;
3d0f8bc7
MW		 516
517 /* Find pci_dev container of dev */
518 if (ca91cx42_bridge->parent == NULL) {
48d9356e 519 dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n");
3d0f8bc7
MW		 520 return -EINVAL;
521 }
522 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
523
8fafb476
MW		 524 existing_size = (unsigned long long)(image->bus_resource.end -
525 image->bus_resource.start);
3d0f8bc7
MW		 526
527 /* If the existing size is OK, return */
528 if (existing_size == (size - 1))
529 return 0;
530
531 if (existing_size != 0) {
532 iounmap(image->kern_base);
533 image->kern_base = NULL;
794a8946 534 kfree(image->bus_resource.name);
886953e9
EC		 535 release_resource(&image->bus_resource);
536 memset(&image->bus_resource, 0, sizeof(struct resource));
3d0f8bc7
MW		 537 }
538
8fafb476 539 if (image->bus_resource.name == NULL) {
0aa3f139 540 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
8fafb476 541 if (image->bus_resource.name == NULL) {
48d9356e
MW		 542 dev_err(ca91cx42_bridge->parent, "Unable to allocate "
543 "memory for resource name\n");
3d0f8bc7
MW		 544 retval = -ENOMEM;
545 goto err_name;
546 }
60479690 547 }
3d0f8bc7 548
8fafb476 549 sprintf((char *)image->bus_resource.name, "%s.%d",
3d0f8bc7
MW		 550 ca91cx42_bridge->name, image->number);
551
8fafb476
MW		 552 image->bus_resource.start = 0;
553 image->bus_resource.end = (unsigned long)size;
554 image->bus_resource.flags = IORESOURCE_MEM;
3d0f8bc7
MW		 555
556 retval = pci_bus_alloc_resource(pdev->bus,
886953e9 557 &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
3d0f8bc7
MW		 558 0, NULL, NULL);
559 if (retval) {
48d9356e
MW		 560 dev_err(ca91cx42_bridge->parent, "Failed to allocate mem "
561 "resource for window %d size 0x%lx start 0x%lx\n",
3d0f8bc7 562 image->number, (unsigned long)size,
8fafb476 563 (unsigned long)image->bus_resource.start);
3d0f8bc7 564 goto err_resource;
60479690 565 }
3d0f8bc7
MW		 566
567 image->kern_base = ioremap_nocache(
8fafb476 568 image->bus_resource.start, size);
3d0f8bc7 569 if (image->kern_base == NULL) {
48d9356e 570 dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n");
3d0f8bc7
MW		 571 retval = -ENOMEM;
572 goto err_remap;
60479690
MW		 573 }
574
3d0f8bc7
MW		 575 return 0;
576
3d0f8bc7 577err_remap:
886953e9 578 release_resource(&image->bus_resource);
3d0f8bc7 579err_resource:
8fafb476 580 kfree(image->bus_resource.name);
886953e9 581 memset(&image->bus_resource, 0, sizeof(struct resource));
3d0f8bc7
MW		 582err_name:
583 return retval;
584}
585
586/*
4860ab74
MW		 587 * Free and unmap PCI Resource
588 */
3d0f8bc7
MW		 589static void ca91cx42_free_resource(struct vme_master_resource *image)
590{
591 iounmap(image->kern_base);
592 image->kern_base = NULL;
886953e9 593 release_resource(&image->bus_resource);
8fafb476 594 kfree(image->bus_resource.name);
886953e9 595 memset(&image->bus_resource, 0, sizeof(struct resource));
3d0f8bc7
MW		 596}
597
598
efbb979d 599static int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
6af04b06
MW		 600 unsigned long long vme_base, unsigned long long size, u32 aspace,
601 u32 cycle, u32 dwidth)
3d0f8bc7
MW		 602{
603 int retval = 0;
21e0cf6d 604 unsigned int i, granularity = 0;
3d0f8bc7
MW		 605 unsigned int temp_ctl = 0;
606 unsigned long long pci_bound, vme_offset, pci_base;
48d9356e 607 struct vme_bridge *ca91cx42_bridge;
29848ac9
MW		 608 struct ca91cx42_driver *bridge;
609
48d9356e
MW		 610 ca91cx42_bridge = image->parent;
611
612 bridge = ca91cx42_bridge->driver_priv;
3d0f8bc7 613
21e0cf6d
MW		 614 i = image->number;
615
616 if ((i == 0) || (i == 4))
617 granularity = 0x1000;
618 else
619 granularity = 0x10000;
620
3d0f8bc7 621 /* Verify input data */
21e0cf6d 622 if (vme_base & (granularity - 1)) {
48d9356e
MW		 623 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
624 "alignment\n");
3d0f8bc7
MW		 625 retval = -EINVAL;
626 goto err_window;
627 }
21e0cf6d 628 if (size & (granularity - 1)) {
48d9356e
MW		 629 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
630 "alignment\n");
3d0f8bc7
MW		 631 retval = -EINVAL;
632 goto err_window;
633 }
634
886953e9 635 spin_lock(&image->lock);
3d0f8bc7 636
3d0f8bc7
MW		 637 /*
638 * Let's allocate the resource here rather than further up the stack as
25985edc 639 * it avoids pushing loads of bus dependent stuff up the stack
3d0f8bc7
MW		 640 */
641 retval = ca91cx42_alloc_resource(image, size);
642 if (retval) {
886953e9 643 spin_unlock(&image->lock);
48d9356e
MW		 644 dev_err(ca91cx42_bridge->parent, "Unable to allocate memory "
645 "for resource name\n");
3d0f8bc7
MW		 646 retval = -ENOMEM;
647 goto err_res;
648 }
649
8fafb476 650 pci_base = (unsigned long long)image->bus_resource.start;
3d0f8bc7
MW		 651
652 /*
653 * Bound address is a valid address for the window, adjust
654 * according to window granularity.
655 */
21e0cf6d 656 pci_bound = pci_base + size;
3d0f8bc7
MW		 657 vme_offset = vme_base - pci_base;
658
3d0f8bc7 659 /* Disable while we are mucking around */
29848ac9 660 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
3d0f8bc7 661 temp_ctl &= ~CA91CX42_LSI_CTL_EN;
29848ac9 662 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
3d0f8bc7 663
3d0f8bc7
MW		 664 /* Setup cycle types */
665 temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
666 if (cycle & VME_BLT)
667 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
668 if (cycle & VME_MBLT)
669 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
670
671 /* Setup data width */
672 temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
673 switch (dwidth) {
674 case VME_D8:
675 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
676 break;
677 case VME_D16:
678 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
679 break;
680 case VME_D32:
681 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
682 break;
683 case VME_D64:
684 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
685 break;
686 default:
886953e9 687 spin_unlock(&image->lock);
48d9356e 688 dev_err(ca91cx42_bridge->parent, "Invalid data width\n");
3d0f8bc7
MW		 689 retval = -EINVAL;
690 goto err_dwidth;
691 break;
60479690 692 }
3d0f8bc7
MW		 693
694 /* Setup address space */
695 temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
696 switch (aspace) {
60479690 697 case VME_A16:
3d0f8bc7 698 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
60479690
MW		 699 break;
700 case VME_A24:
3d0f8bc7 701 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
60479690
MW		 702 break;
703 case VME_A32:
3d0f8bc7
MW		 704 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
705 break;
706 case VME_CRCSR:
707 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
60479690
MW		 708 break;
709 case VME_USER1:
3d0f8bc7 710 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
60479690
MW		 711 break;
712 case VME_USER2:
3d0f8bc7
MW		 713 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
714 break;
715 case VME_A64:
716 case VME_USER3:
717 case VME_USER4:
718 default:
886953e9 719 spin_unlock(&image->lock);
48d9356e 720 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
3d0f8bc7
MW		 721 retval = -EINVAL;
722 goto err_aspace;
60479690
MW		 723 break;
724 }
725
3d0f8bc7
MW		 726 temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
727 if (cycle & VME_SUPER)
728 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
729 if (cycle & VME_PROG)
730 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
60479690 731
3d0f8bc7 732 /* Setup mapping */
29848ac9
MW		 733 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
734 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
735 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
3d0f8bc7
MW		 736
737 /* Write ctl reg without enable */
29848ac9 738 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
3d0f8bc7
MW		 739
740 if (enabled)
741 temp_ctl |= CA91CX42_LSI_CTL_EN;
742
29848ac9 743 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
3d0f8bc7 744
886953e9 745 spin_unlock(&image->lock);
3d0f8bc7
MW		 746 return 0;
747
748err_aspace:
749err_dwidth:
750 ca91cx42_free_resource(image);
751err_res:
752err_window:
753 return retval;
754}
755
efbb979d
EC		 756static int __ca91cx42_master_get(struct vme_master_resource *image,
757 int *enabled, unsigned long long *vme_base, unsigned long long *size,
6af04b06 758 u32 *aspace, u32 *cycle, u32 *dwidth)
3d0f8bc7
MW		 759{
760 unsigned int i, ctl;
761 unsigned long long pci_base, pci_bound, vme_offset;
29848ac9
MW		 762 struct ca91cx42_driver *bridge;
763
764 bridge = image->parent->driver_priv;
3d0f8bc7
MW		 765
766 i = image->number;
767
29848ac9 768 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
3d0f8bc7 769
29848ac9
MW		 770 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
771 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
772 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
3d0f8bc7
MW		 773
774 *vme_base = pci_base + vme_offset;
21e0cf6d 775 *size = (unsigned long long)(pci_bound - pci_base);
3d0f8bc7
MW		 776
777 *enabled = 0;
778 *aspace = 0;
779 *cycle = 0;
780 *dwidth = 0;
781
782 if (ctl & CA91CX42_LSI_CTL_EN)
783 *enabled = 1;
784
785 /* Setup address space */
786 switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
787 case CA91CX42_LSI_CTL_VAS_A16:
788 *aspace = VME_A16;
789 break;
790 case CA91CX42_LSI_CTL_VAS_A24:
791 *aspace = VME_A24;
792 break;
793 case CA91CX42_LSI_CTL_VAS_A32:
794 *aspace = VME_A32;
795 break;
796 case CA91CX42_LSI_CTL_VAS_CRCSR:
797 *aspace = VME_CRCSR;
798 break;
799 case CA91CX42_LSI_CTL_VAS_USER1:
800 *aspace = VME_USER1;
801 break;
802 case CA91CX42_LSI_CTL_VAS_USER2:
803 *aspace = VME_USER2;
804 break;
805 }
806
807 /* XXX Not sure howto check for MBLT */
808 /* Setup cycle types */
809 if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
810 *cycle |= VME_BLT;
811 else
812 *cycle |= VME_SCT;
813
814 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
815 *cycle |= VME_SUPER;
816 else
817 *cycle |= VME_USER;
818
819 if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
820 *cycle = VME_PROG;
821 else
822 *cycle = VME_DATA;
823
824 /* Setup data width */
825 switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
826 case CA91CX42_LSI_CTL_VDW_D8:
827 *dwidth = VME_D8;
828 break;
829 case CA91CX42_LSI_CTL_VDW_D16:
830 *dwidth = VME_D16;
831 break;
832 case CA91CX42_LSI_CTL_VDW_D32:
833 *dwidth = VME_D32;
834 break;
835 case CA91CX42_LSI_CTL_VDW_D64:
836 *dwidth = VME_D64;
837 break;
838 }
839
3d0f8bc7
MW		 840 return 0;
841}
842
efbb979d 843static int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
6af04b06
MW		 844 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
845 u32 *cycle, u32 *dwidth)
3d0f8bc7
MW		 846{
847 int retval;
848
886953e9 849 spin_lock(&image->lock);
3d0f8bc7
MW		 850
851 retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
852 cycle, dwidth);
853
886953e9 854 spin_unlock(&image->lock);
3d0f8bc7
MW		 855
856 return retval;
857}
858
efbb979d
EC		 859static ssize_t ca91cx42_master_read(struct vme_master_resource *image,
860 void *buf, size_t count, loff_t offset)
3d0f8bc7 861{
21e0cf6d 862 ssize_t retval;
d90f32c2 863 void __iomem *addr = image->kern_base + offset;
53059aa0
AB		 864 unsigned int done = 0;
865 unsigned int count32;
866
867 if (count == 0)
868 return 0;
60479690 869
886953e9 870 spin_lock(&image->lock);
60479690 871
53059aa0
AB		 872 /* The following code handles VME address alignment problem
873 * in order to assure the maximal data width cycle.
874 * We cannot use memcpy_xxx directly here because it
875 * may cut data transfer in 8-bits cycles, thus making
876 * D16 cycle impossible.
877 * From the other hand, the bridge itself assures that
878 * maximal configured data cycle is used and splits it
879 * automatically for non-aligned addresses.
880 */
b91a9363 881 if ((uintptr_t)addr & 0x1) {
53059aa0
AB		 882 *(u8 *)buf = ioread8(addr);
883 done += 1;
884 if (done == count)
885 goto out;
886 }
b91a9363 887 if ((uintptr_t)addr & 0x2) {
53059aa0
AB		 888 if ((count - done) < 2) {
889 *(u8 *)(buf + done) = ioread8(addr + done);
890 done += 1;
891 goto out;
892 } else {
893 *(u16 *)(buf + done) = ioread16(addr + done);
894 done += 2;
895 }
896 }
60479690 897
53059aa0
AB		 898 count32 = (count - done) & ~0x3;
899 if (count32 > 0) {
900 memcpy_fromio(buf + done, addr + done, (unsigned int)count);
901 done += count32;
902 }
903
904 if ((count - done) & 0x2) {
905 *(u16 *)(buf + done) = ioread16(addr + done);
906 done += 2;
907 }
908 if ((count - done) & 0x1) {
909 *(u8 *)(buf + done) = ioread8(addr + done);
910 done += 1;
911 }
912out:
913 retval = count;
886953e9 914 spin_unlock(&image->lock);
3d0f8bc7
MW		 915
916 return retval;
60479690
MW		 917}
918
efbb979d
EC		 919static ssize_t ca91cx42_master_write(struct vme_master_resource *image,
920 void *buf, size_t count, loff_t offset)
60479690 921{
53059aa0 922 ssize_t retval;
d90f32c2 923 void __iomem *addr = image->kern_base + offset;
53059aa0
AB		 924 unsigned int done = 0;
925 unsigned int count32;
926
927 if (count == 0)
928 return 0;
60479690 929
886953e9 930 spin_lock(&image->lock);
60479690 931
53059aa0
AB		 932 /* Here we apply for the same strategy we do in master_read
933 * function in order to assure D16 cycle when required.
934 */
b91a9363 935 if ((uintptr_t)addr & 0x1) {
53059aa0
AB		 936 iowrite8(*(u8 *)buf, addr);
937 done += 1;
938 if (done == count)
939 goto out;
940 }
b91a9363 941 if ((uintptr_t)addr & 0x2) {
53059aa0
AB		 942 if ((count - done) < 2) {
943 iowrite8(*(u8 *)(buf + done), addr + done);
944 done += 1;
945 goto out;
946 } else {
947 iowrite16(*(u16 *)(buf + done), addr + done);
948 done += 2;
949 }
950 }
951
952 count32 = (count - done) & ~0x3;
953 if (count32 > 0) {
954 memcpy_toio(addr + done, buf + done, count32);
955 done += count32;
956 }
957
958 if ((count - done) & 0x2) {
959 iowrite16(*(u16 *)(buf + done), addr + done);
960 done += 2;
961 }
962 if ((count - done) & 0x1) {
963 iowrite8(*(u8 *)(buf + done), addr + done);
964 done += 1;
965 }
966out:
3d0f8bc7
MW		 967 retval = count;
968
886953e9
EC		 969 spin_unlock(&image->lock);
970
3d0f8bc7 971 return retval;
60479690
MW		 972}
973
efbb979d 974static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
04e10e15
MW		 975 unsigned int mask, unsigned int compare, unsigned int swap,
976 loff_t offset)
977{
b91a9363
MV		 978 u32 result;
979 uintptr_t pci_addr;
04e10e15
MW		 980 int i;
981 struct ca91cx42_driver *bridge;
982 struct device *dev;
983
984 bridge = image->parent->driver_priv;
985 dev = image->parent->parent;
986
987 /* Find the PCI address that maps to the desired VME address */
988 i = image->number;
989
990 /* Locking as we can only do one of these at a time */
886953e9 991 mutex_lock(&bridge->vme_rmw);
04e10e15
MW		 992
993 /* Lock image */
886953e9 994 spin_lock(&image->lock);
04e10e15 995
b91a9363 996 pci_addr = (uintptr_t)image->kern_base + offset;
04e10e15
MW		 997
998 /* Address must be 4-byte aligned */
999 if (pci_addr & 0x3) {
1000 dev_err(dev, "RMW Address not 4-byte aligned\n");
7c0ace54
JL		 1001 result = -EINVAL;
1002 goto out;
04e10e15
MW		 1003 }
1004
1005 /* Ensure RMW Disabled whilst configuring */
1006 iowrite32(0, bridge->base + SCYC_CTL);
1007
1008 /* Configure registers */
1009 iowrite32(mask, bridge->base + SCYC_EN);
1010 iowrite32(compare, bridge->base + SCYC_CMP);
1011 iowrite32(swap, bridge->base + SCYC_SWP);
1012 iowrite32(pci_addr, bridge->base + SCYC_ADDR);
1013
1014 /* Enable RMW */
1015 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
1016
1017 /* Kick process off with a read to the required address. */
1018 result = ioread32(image->kern_base + offset);
1019
1020 /* Disable RMW */
1021 iowrite32(0, bridge->base + SCYC_CTL);
1022
7c0ace54 1023out:
886953e9 1024 spin_unlock(&image->lock);
04e10e15 1025
886953e9 1026 mutex_unlock(&bridge->vme_rmw);
04e10e15
MW		 1027
1028 return result;
1029}
1030
efbb979d
EC		 1031static int ca91cx42_dma_list_add(struct vme_dma_list *list,
1032 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
4860ab74
MW		 1033{
1034 struct ca91cx42_dma_entry *entry, *prev;
1035 struct vme_dma_pci *pci_attr;
1036 struct vme_dma_vme *vme_attr;
1037 dma_addr_t desc_ptr;
1038 int retval = 0;
48d9356e
MW		 1039 struct device *dev;
1040
1041 dev = list->parent->parent->parent;
4860ab74
MW		 1042
1043 /* XXX descriptor must be aligned on 64-bit boundaries */
32414878 1044 entry = kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
4860ab74 1045 if (entry == NULL) {
48d9356e 1046 dev_err(dev, "Failed to allocate memory for dma resource "
4860ab74
MW		 1047 "structure\n");
1048 retval = -ENOMEM;
1049 goto err_mem;
1050 }
1051
1052 /* Test descriptor alignment */
886953e9 1053 if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {
48d9356e 1054 dev_err(dev, "Descriptor not aligned to 16 byte boundary as "
886953e9 1055 "required: %p\n", &entry->descriptor);
4860ab74
MW		 1056 retval = -EINVAL;
1057 goto err_align;
1058 }
1059
886953e9 1060 memset(&entry->descriptor, 0, sizeof(struct ca91cx42_dma_descriptor));
4860ab74
MW		 1061
1062 if (dest->type == VME_DMA_VME) {
1063 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
feffce47
KV		 1064 vme_attr = dest->private;
1065 pci_attr = src->private;
4860ab74 1066 } else {
feffce47
KV		 1067 vme_attr = src->private;
1068 pci_attr = dest->private;
4860ab74
MW		 1069 }
1070
25985edc 1071 /* Check we can do fulfill required attributes */
4860ab74
MW		 1072 if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
1073 VME_USER2)) != 0) {
1074
48d9356e 1075 dev_err(dev, "Unsupported cycle type\n");
4860ab74
MW		 1076 retval = -EINVAL;
1077 goto err_aspace;
1078 }
1079
1080 if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
1081 VME_PROG | VME_DATA)) != 0) {
1082
48d9356e 1083 dev_err(dev, "Unsupported cycle type\n");
4860ab74
MW		 1084 retval = -EINVAL;
1085 goto err_cycle;
1086 }
1087
25985edc 1088 /* Check to see if we can fulfill source and destination */
4860ab74
MW		 1089 if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
1090 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
1091
48d9356e 1092 dev_err(dev, "Cannot perform transfer with this "
4860ab74
MW		 1093 "source-destination combination\n");
1094 retval = -EINVAL;
1095 goto err_direct;
1096 }
1097
1098 /* Setup cycle types */
1099 if (vme_attr->cycle & VME_BLT)
1100 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1101
1102 /* Setup data width */
1103 switch (vme_attr->dwidth) {
1104 case VME_D8:
1105 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1106 break;
1107 case VME_D16:
1108 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1109 break;
1110 case VME_D32:
1111 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1112 break;
1113 case VME_D64:
1114 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1115 break;
1116 default:
48d9356e 1117 dev_err(dev, "Invalid data width\n");
4860ab74
MW		 1118 return -EINVAL;
1119 }
1120
1121 /* Setup address space */
1122 switch (vme_attr->aspace) {
1123 case VME_A16:
1124 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1125 break;
1126 case VME_A24:
1127 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1128 break;
1129 case VME_A32:
1130 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1131 break;
1132 case VME_USER1:
1133 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1134 break;
1135 case VME_USER2:
1136 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1137 break;
1138 default:
48d9356e 1139 dev_err(dev, "Invalid address space\n");
4860ab74
MW		 1140 return -EINVAL;
1141 break;
1142 }
1143
1144 if (vme_attr->cycle & VME_SUPER)
1145 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1146 if (vme_attr->cycle & VME_PROG)
1147 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1148
1149 entry->descriptor.dtbc = count;
1150 entry->descriptor.dla = pci_attr->address;
1151 entry->descriptor.dva = vme_attr->address;
1152 entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1153
1154 /* Add to list */
886953e9 1155 list_add_tail(&entry->list, &list->entries);
4860ab74
MW		 1156
1157 /* Fill out previous descriptors "Next Address" */
886953e9 1158 if (entry->list.prev != &list->entries) {
4860ab74
MW		 1159 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1160 list);
1161 /* We need the bus address for the pointer */
886953e9 1162 desc_ptr = virt_to_bus(&entry->descriptor);
4860ab74
MW		 1163 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1164 }
1165
1166 return 0;
1167
1168err_cycle:
1169err_aspace:
1170err_direct:
1171err_align:
1172 kfree(entry);
1173err_mem:
1174 return retval;
1175}
1176
1177static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1178{
1179 u32 tmp;
1180 struct ca91cx42_driver *bridge;
1181
1182 bridge = ca91cx42_bridge->driver_priv;
1183
1184 tmp = ioread32(bridge->base + DGCS);
1185
1186 if (tmp & CA91CX42_DGCS_ACT)
1187 return 0;
1188 else
1189 return 1;
1190}
1191
efbb979d 1192static int ca91cx42_dma_list_exec(struct vme_dma_list *list)
4860ab74
MW		 1193{
1194 struct vme_dma_resource *ctrlr;
1195 struct ca91cx42_dma_entry *entry;
1196 int retval = 0;
1197 dma_addr_t bus_addr;
1198 u32 val;
48d9356e 1199 struct device *dev;
4860ab74
MW		 1200 struct ca91cx42_driver *bridge;
1201
1202 ctrlr = list->parent;
1203
1204 bridge = ctrlr->parent->driver_priv;
48d9356e 1205 dev = ctrlr->parent->parent;
4860ab74 1206
886953e9 1207 mutex_lock(&ctrlr->mtx);
4860ab74 1208
886953e9 1209 if (!(list_empty(&ctrlr->running))) {
4860ab74
MW		 1210 /*
1211 * XXX We have an active DMA transfer and currently haven't
1212 * sorted out the mechanism for "pending" DMA transfers.
1213 * Return busy.
1214 */
1215 /* Need to add to pending here */
886953e9 1216 mutex_unlock(&ctrlr->mtx);
4860ab74
MW		 1217 return -EBUSY;
1218 } else {
886953e9 1219 list_add(&list->list, &ctrlr->running);
4860ab74
MW		 1220 }
1221
1222 /* Get first bus address and write into registers */
886953e9 1223 entry = list_first_entry(&list->entries, struct ca91cx42_dma_entry,
4860ab74
MW		 1224 list);
1225
886953e9 1226 bus_addr = virt_to_bus(&entry->descriptor);
4860ab74 1227
886953e9 1228 mutex_unlock(&ctrlr->mtx);
4860ab74
MW		 1229
1230 iowrite32(0, bridge->base + DTBC);
1231 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1232
1233 /* Start the operation */
1234 val = ioread32(bridge->base + DGCS);
1235
1236 /* XXX Could set VMEbus On and Off Counters here */
1237 val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1238
1239 val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1240 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1241 CA91CX42_DGCS_PERR);
1242
1243 iowrite32(val, bridge->base + DGCS);
1244
1245 val |= CA91CX42_DGCS_GO;
1246
1247 iowrite32(val, bridge->base + DGCS);
1248
1249 wait_event_interruptible(bridge->dma_queue,
1250 ca91cx42_dma_busy(ctrlr->parent));
1251
1252 /*
1253 * Read status register, this register is valid until we kick off a
1254 * new transfer.
1255 */
1256 val = ioread32(bridge->base + DGCS);
1257
1258 if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1259 CA91CX42_DGCS_PERR)) {
1260
48d9356e 1261 dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val);
4860ab74
MW		 1262 val = ioread32(bridge->base + DCTL);
1263 }
1264
1265 /* Remove list from running list */
886953e9
EC		 1266 mutex_lock(&ctrlr->mtx);
1267 list_del(&list->list);
1268 mutex_unlock(&ctrlr->mtx);
4860ab74
MW		 1269
1270 return retval;
1271
1272}
1273
efbb979d 1274static int ca91cx42_dma_list_empty(struct vme_dma_list *list)
4860ab74
MW		 1275{
1276 struct list_head *pos, *temp;
1277 struct ca91cx42_dma_entry *entry;
1278
1279 /* detach and free each entry */
886953e9 1280 list_for_each_safe(pos, temp, &list->entries) {
4860ab74
MW		 1281 list_del(pos);
1282 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1283 kfree(entry);
1284 }
1285
1286 return 0;
1287}
1288
2b82beb8
MW		 1289/*
1290 * All 4 location monitors reside at the same base - this is therefore a
1291 * system wide configuration.
1292 *
1293 * This does not enable the LM monitor - that should be done when the first
1294 * callback is attached and disabled when the last callback is removed.
1295 */
efbb979d 1296static int ca91cx42_lm_set(struct vme_lm_resource *lm,
6af04b06 1297 unsigned long long lm_base, u32 aspace, u32 cycle)
2b82beb8
MW		 1298{
1299 u32 temp_base, lm_ctl = 0;
1300 int i;
1301 struct ca91cx42_driver *bridge;
1302 struct device *dev;
1303
1304 bridge = lm->parent->driver_priv;
1305 dev = lm->parent->parent;
1306
1307 /* Check the alignment of the location monitor */
1308 temp_base = (u32)lm_base;
1309 if (temp_base & 0xffff) {
1310 dev_err(dev, "Location monitor must be aligned to 64KB "
1311 "boundary");
1312 return -EINVAL;
1313 }
1314
886953e9 1315 mutex_lock(&lm->mtx);
2b82beb8
MW		 1316
1317 /* If we already have a callback attached, we can't move it! */
1318 for (i = 0; i < lm->monitors; i++) {
1319 if (bridge->lm_callback[i] != NULL) {
886953e9 1320 mutex_unlock(&lm->mtx);
2b82beb8
MW		 1321 dev_err(dev, "Location monitor callback attached, "
1322 "can't reset\n");
1323 return -EBUSY;
1324 }
1325 }
1326
1327 switch (aspace) {
1328 case VME_A16:
1329 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1330 break;
1331 case VME_A24:
1332 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1333 break;
1334 case VME_A32:
1335 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1336 break;
1337 default:
886953e9 1338 mutex_unlock(&lm->mtx);
2b82beb8
MW		 1339 dev_err(dev, "Invalid address space\n");
1340 return -EINVAL;
1341 break;
1342 }
1343
1344 if (cycle & VME_SUPER)
1345 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1346 if (cycle & VME_USER)
1347 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1348 if (cycle & VME_PROG)
1349 lm_ctl |= CA91CX42_LM_CTL_PGM;
1350 if (cycle & VME_DATA)
1351 lm_ctl |= CA91CX42_LM_CTL_DATA;
1352
1353 iowrite32(lm_base, bridge->base + LM_BS);
1354 iowrite32(lm_ctl, bridge->base + LM_CTL);
1355
886953e9 1356 mutex_unlock(&lm->mtx);
2b82beb8
MW		 1357
1358 return 0;
1359}
1360
1361/* Get configuration of the callback monitor and return whether it is enabled
1362 * or disabled.
1363 */
efbb979d 1364static int ca91cx42_lm_get(struct vme_lm_resource *lm,
6af04b06 1365 unsigned long long *lm_base, u32 *aspace, u32 *cycle)
2b82beb8
MW		 1366{
1367 u32 lm_ctl, enabled = 0;
1368 struct ca91cx42_driver *bridge;
1369
1370 bridge = lm->parent->driver_priv;
1371
886953e9 1372 mutex_lock(&lm->mtx);
2b82beb8
MW		 1373
1374 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1375 lm_ctl = ioread32(bridge->base + LM_CTL);
1376
1377 if (lm_ctl & CA91CX42_LM_CTL_EN)
1378 enabled = 1;
1379
1380 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1381 *aspace = VME_A16;
1382 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1383 *aspace = VME_A24;
1384 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1385 *aspace = VME_A32;
1386
1387 *cycle = 0;
1388 if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1389 *cycle |= VME_SUPER;
1390 if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1391 *cycle |= VME_USER;
1392 if (lm_ctl & CA91CX42_LM_CTL_PGM)
1393 *cycle |= VME_PROG;
1394 if (lm_ctl & CA91CX42_LM_CTL_DATA)
1395 *cycle |= VME_DATA;
1396
886953e9 1397 mutex_unlock(&lm->mtx);
2b82beb8
MW		 1398
1399 return enabled;
1400}
1401
1402/*
1403 * Attach a callback to a specific location monitor.
1404 *
1405 * Callback will be passed the monitor triggered.
1406 */
efbb979d 1407static int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
2b82beb8
MW		 1408 void (*callback)(int))
1409{
1410 u32 lm_ctl, tmp;
1411 struct ca91cx42_driver *bridge;
1412 struct device *dev;
1413
1414 bridge = lm->parent->driver_priv;
1415 dev = lm->parent->parent;
1416
886953e9 1417 mutex_lock(&lm->mtx);
2b82beb8
MW		 1418
1419 /* Ensure that the location monitor is configured - need PGM or DATA */
1420 lm_ctl = ioread32(bridge->base + LM_CTL);
1421 if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
886953e9 1422 mutex_unlock(&lm->mtx);
2b82beb8
MW		 1423 dev_err(dev, "Location monitor not properly configured\n");
1424 return -EINVAL;
1425 }
1426
1427 /* Check that a callback isn't already attached */
1428 if (bridge->lm_callback[monitor] != NULL) {
886953e9 1429 mutex_unlock(&lm->mtx);
2b82beb8
MW		 1430 dev_err(dev, "Existing callback attached\n");
1431 return -EBUSY;
1432 }
1433
1434 /* Attach callback */
1435 bridge->lm_callback[monitor] = callback;
1436
1437 /* Enable Location Monitor interrupt */
1438 tmp = ioread32(bridge->base + LINT_EN);
1439 tmp |= CA91CX42_LINT_LM[monitor];
1440 iowrite32(tmp, bridge->base + LINT_EN);
1441
1442 /* Ensure that global Location Monitor Enable set */
1443 if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1444 lm_ctl |= CA91CX42_LM_CTL_EN;
1445 iowrite32(lm_ctl, bridge->base + LM_CTL);
1446 }
1447
886953e9 1448 mutex_unlock(&lm->mtx);
2b82beb8
MW		 1449
1450 return 0;
1451}
1452
1453/*
1454 * Detach a callback function forn a specific location monitor.
1455 */
efbb979d 1456static int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
2b82beb8
MW		 1457{
1458 u32 tmp;
1459 struct ca91cx42_driver *bridge;
1460
1461 bridge = lm->parent->driver_priv;
1462
886953e9 1463 mutex_lock(&lm->mtx);
2b82beb8
MW		 1464
1465 /* Disable Location Monitor and ensure previous interrupts are clear */
1466 tmp = ioread32(bridge->base + LINT_EN);
1467 tmp &= ~CA91CX42_LINT_LM[monitor];
1468 iowrite32(tmp, bridge->base + LINT_EN);
1469
1470 iowrite32(CA91CX42_LINT_LM[monitor],
1471 bridge->base + LINT_STAT);
1472
1473 /* Detach callback */
1474 bridge->lm_callback[monitor] = NULL;
1475
1476 /* If all location monitors disabled, disable global Location Monitor */
1477 if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1478 CA91CX42_LINT_LM3)) == 0) {
1479 tmp = ioread32(bridge->base + LM_CTL);
1480 tmp &= ~CA91CX42_LM_CTL_EN;
1481 iowrite32(tmp, bridge->base + LM_CTL);
1482 }
1483
886953e9 1484 mutex_unlock(&lm->mtx);
2b82beb8
MW		 1485
1486 return 0;
1487}
1488
efbb979d 1489static int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
60479690 1490{
3d0f8bc7 1491 u32 slot = 0;
29848ac9
MW		 1492 struct ca91cx42_driver *bridge;
1493
1494 bridge = ca91cx42_bridge->driver_priv;
60479690 1495
12b2d5c0 1496 if (!geoid) {
29848ac9 1497 slot = ioread32(bridge->base + VCSR_BS);
12b2d5c0
MW		 1498 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1499 } else
1500 slot = geoid;
1501
3d0f8bc7
MW		 1502 return (int)slot;
1503
1504}
1505
a11cfdf4 1506static void *ca91cx42_alloc_consistent(struct device *parent, size_t size,
7f58f025
MV		 1507 dma_addr_t *dma)
1508{
1509 struct pci_dev *pdev;
1510
1511 /* Find pci_dev container of dev */
1512 pdev = container_of(parent, struct pci_dev, dev);
1513
1514 return pci_alloc_consistent(pdev, size, dma);
1515}
1516
a11cfdf4
HS		 1517static void ca91cx42_free_consistent(struct device *parent, size_t size,
1518 void *vaddr, dma_addr_t dma)
7f58f025
MV		 1519{
1520 struct pci_dev *pdev;
1521
1522 /* Find pci_dev container of dev */
1523 pdev = container_of(parent, struct pci_dev, dev);
1524
1525 pci_free_consistent(pdev, size, vaddr, dma);
1526}
1527
3d0f8bc7
MW		 1528/*
1529 * Configure CR/CSR space
1530 *
1531 * Access to the CR/CSR can be configured at power-up. The location of the
1532 * CR/CSR registers in the CR/CSR address space is determined by the boards
1533 * Auto-ID or Geographic address. This function ensures that the window is
1534 * enabled at an offset consistent with the boards geopgraphic address.
1535 */
29848ac9
MW		 1536static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1537 struct pci_dev *pdev)
3d0f8bc7
MW		 1538{
1539 unsigned int crcsr_addr;
1540 int tmp, slot;
29848ac9
MW		 1541 struct ca91cx42_driver *bridge;
1542
1543 bridge = ca91cx42_bridge->driver_priv;
3d0f8bc7 1544
29848ac9 1545 slot = ca91cx42_slot_get(ca91cx42_bridge);
25331ba2
MW		 1546
1547 /* Write CSR Base Address if slot ID is supplied as a module param */
1548 if (geoid)
1549 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1550
3d0f8bc7
MW		 1551 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1552 if (slot == 0) {
1553 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1554 "CR/CSR space\n");
1555 return -EINVAL;
60479690 1556 }
3d0f8bc7
MW		 1557
1558 /* Allocate mem for CR/CSR image */
29848ac9 1559 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
886953e9 1560 &bridge->crcsr_bus);
29848ac9 1561 if (bridge->crcsr_kernel == NULL) {
3d0f8bc7
MW		 1562 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1563 "image\n");
1564 return -ENOMEM;
60479690
MW		 1565 }
1566
29848ac9 1567 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
60479690 1568
3d0f8bc7 1569 crcsr_addr = slot * (512 * 1024);
29848ac9 1570 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
60479690 1571
29848ac9 1572 tmp = ioread32(bridge->base + VCSR_CTL);
3d0f8bc7 1573 tmp |= CA91CX42_VCSR_CTL_EN;
29848ac9 1574 iowrite32(tmp, bridge->base + VCSR_CTL);
60479690 1575
3d0f8bc7 1576 return 0;
60479690
MW		 1577}
1578
29848ac9
MW		 1579static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1580 struct pci_dev *pdev)
60479690 1581{
3d0f8bc7 1582 u32 tmp;
29848ac9
MW		 1583 struct ca91cx42_driver *bridge;
1584
1585 bridge = ca91cx42_bridge->driver_priv;
60479690 1586
3d0f8bc7 1587 /* Turn off CR/CSR space */
29848ac9 1588 tmp = ioread32(bridge->base + VCSR_CTL);
3d0f8bc7 1589 tmp &= ~CA91CX42_VCSR_CTL_EN;
29848ac9 1590 iowrite32(tmp, bridge->base + VCSR_CTL);
60479690 1591
3d0f8bc7 1592 /* Free image */
29848ac9 1593 iowrite32(0, bridge->base + VCSR_TO);
60479690 1594
29848ac9
MW		 1595 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1596 bridge->crcsr_bus);
3d0f8bc7 1597}
60479690 1598
3d0f8bc7
MW		 1599static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1600{
1601 int retval, i;
1602 u32 data;
43f5e46c 1603 struct list_head *pos = NULL, *n;
29848ac9
MW		 1604 struct vme_bridge *ca91cx42_bridge;
1605 struct ca91cx42_driver *ca91cx42_device;
3d0f8bc7
MW		 1606 struct vme_master_resource *master_image;
1607 struct vme_slave_resource *slave_image;
3d0f8bc7 1608 struct vme_dma_resource *dma_ctrlr;
3d0f8bc7
MW		 1609 struct vme_lm_resource *lm;
1610
1611 /* We want to support more than one of each bridge so we need to
1612 * dynamically allocate the bridge structure
1613 */
7a6cb0d5 1614 ca91cx42_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
3d0f8bc7
MW		 1615
1616 if (ca91cx42_bridge == NULL) {
1617 dev_err(&pdev->dev, "Failed to allocate memory for device "
1618 "structure\n");
1619 retval = -ENOMEM;
1620 goto err_struct;
1621 }
1622
7a6cb0d5 1623 ca91cx42_device = kzalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
29848ac9
MW		 1624
1625 if (ca91cx42_device == NULL) {
1626 dev_err(&pdev->dev, "Failed to allocate memory for device "
1627 "structure\n");
1628 retval = -ENOMEM;
1629 goto err_driver;
1630 }
1631
29848ac9
MW		 1632 ca91cx42_bridge->driver_priv = ca91cx42_device;
1633
3d0f8bc7
MW		 1634 /* Enable the device */
1635 retval = pci_enable_device(pdev);
1636 if (retval) {
1637 dev_err(&pdev->dev, "Unable to enable device\n");
1638 goto err_enable;
1639 }
1640
1641 /* Map Registers */
1642 retval = pci_request_regions(pdev, driver_name);
1643 if (retval) {
1644 dev_err(&pdev->dev, "Unable to reserve resources\n");
1645 goto err_resource;
1646 }
1647
1648 /* map registers in BAR 0 */
29848ac9 1649 ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
3d0f8bc7 1650 4096);
29848ac9 1651 if (!ca91cx42_device->base) {
3d0f8bc7
MW		 1652 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1653 retval = -EIO;
1654 goto err_remap;
1655 }
1656
1657 /* Check to see if the mapping worked out */
29848ac9 1658 data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
3d0f8bc7
MW		 1659 if (data != PCI_VENDOR_ID_TUNDRA) {
1660 dev_err(&pdev->dev, "PCI_ID check failed\n");
1661 retval = -EIO;
1662 goto err_test;
1663 }
1664
1665 /* Initialize wait queues & mutual exclusion flags */
886953e9
EC		 1666 init_waitqueue_head(&ca91cx42_device->dma_queue);
1667 init_waitqueue_head(&ca91cx42_device->iack_queue);
1668 mutex_init(&ca91cx42_device->vme_int);
1669 mutex_init(&ca91cx42_device->vme_rmw);
3d0f8bc7 1670
886953e9 1671 ca91cx42_bridge->parent = &pdev->dev;
3d0f8bc7
MW		 1672 strcpy(ca91cx42_bridge->name, driver_name);
1673
1674 /* Setup IRQ */
1675 retval = ca91cx42_irq_init(ca91cx42_bridge);
1676 if (retval != 0) {
1677 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1678 goto err_irq;
1679 }
1680
1681 /* Add master windows to list */
886953e9 1682 INIT_LIST_HEAD(&ca91cx42_bridge->master_resources);
3d0f8bc7
MW		 1683 for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1684 master_image = kmalloc(sizeof(struct vme_master_resource),
1685 GFP_KERNEL);
1686 if (master_image == NULL) {
1687 dev_err(&pdev->dev, "Failed to allocate memory for "
1688 "master resource structure\n");
1689 retval = -ENOMEM;
1690 goto err_master;
1691 }
1692 master_image->parent = ca91cx42_bridge;
886953e9 1693 spin_lock_init(&master_image->lock);
3d0f8bc7
MW		 1694 master_image->locked = 0;
1695 master_image->number = i;
1696 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1697 VME_CRCSR | VME_USER1 | VME_USER2;
1698 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1699 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1700 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
886953e9 1701 memset(&master_image->bus_resource, 0,
3d0f8bc7
MW		 1702 sizeof(struct resource));
1703 master_image->kern_base = NULL;
886953e9
EC		 1704 list_add_tail(&master_image->list,
1705 &ca91cx42_bridge->master_resources);
3d0f8bc7
MW		 1706 }
1707
1708 /* Add slave windows to list */
886953e9 1709 INIT_LIST_HEAD(&ca91cx42_bridge->slave_resources);
3d0f8bc7
MW		 1710 for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1711 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1712 GFP_KERNEL);
1713 if (slave_image == NULL) {
1714 dev_err(&pdev->dev, "Failed to allocate memory for "
1715 "slave resource structure\n");
1716 retval = -ENOMEM;
1717 goto err_slave;
1718 }
1719 slave_image->parent = ca91cx42_bridge;
886953e9 1720 mutex_init(&slave_image->mtx);
3d0f8bc7
MW		 1721 slave_image->locked = 0;
1722 slave_image->number = i;
1723 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1724 VME_USER2;
1725
1726 /* Only windows 0 and 4 support A16 */
1727 if (i == 0 || i == 4)
1728 slave_image->address_attr |= VME_A16;
1729
1730 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1731 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
886953e9
EC		 1732 list_add_tail(&slave_image->list,
1733 &ca91cx42_bridge->slave_resources);
3d0f8bc7 1734 }
4860ab74 1735
3d0f8bc7 1736 /* Add dma engines to list */
886953e9 1737 INIT_LIST_HEAD(&ca91cx42_bridge->dma_resources);
3d0f8bc7
MW		 1738 for (i = 0; i < CA91C142_MAX_DMA; i++) {
1739 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1740 GFP_KERNEL);
1741 if (dma_ctrlr == NULL) {
1742 dev_err(&pdev->dev, "Failed to allocate memory for "
1743 "dma resource structure\n");
1744 retval = -ENOMEM;
1745 goto err_dma;
1746 }
1747 dma_ctrlr->parent = ca91cx42_bridge;
886953e9 1748 mutex_init(&dma_ctrlr->mtx);
3d0f8bc7
MW		 1749 dma_ctrlr->locked = 0;
1750 dma_ctrlr->number = i;
4f723df4
MW		 1751 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1752 VME_DMA_MEM_TO_VME;
886953e9
EC		 1753 INIT_LIST_HEAD(&dma_ctrlr->pending);
1754 INIT_LIST_HEAD(&dma_ctrlr->running);
1755 list_add_tail(&dma_ctrlr->list,
1756 &ca91cx42_bridge->dma_resources);
3d0f8bc7 1757 }
4860ab74 1758
3d0f8bc7 1759 /* Add location monitor to list */
886953e9 1760 INIT_LIST_HEAD(&ca91cx42_bridge->lm_resources);
3d0f8bc7
MW		 1761 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1762 if (lm == NULL) {
1763 dev_err(&pdev->dev, "Failed to allocate memory for "
1764 "location monitor resource structure\n");
1765 retval = -ENOMEM;
1766 goto err_lm;
1767 }
1768 lm->parent = ca91cx42_bridge;
886953e9 1769 mutex_init(&lm->mtx);
3d0f8bc7
MW		 1770 lm->locked = 0;
1771 lm->number = 1;
1772 lm->monitors = 4;
886953e9 1773 list_add_tail(&lm->list, &ca91cx42_bridge->lm_resources);
3d0f8bc7
MW		 1774
1775 ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1776 ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1777 ca91cx42_bridge->master_get = ca91cx42_master_get;
1778 ca91cx42_bridge->master_set = ca91cx42_master_set;
1779 ca91cx42_bridge->master_read = ca91cx42_master_read;
1780 ca91cx42_bridge->master_write = ca91cx42_master_write;
3d0f8bc7
MW		 1781 ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1782 ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1783 ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1784 ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
c813f592
MW		 1785 ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1786 ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
3d0f8bc7
MW		 1787 ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1788 ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1789 ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1790 ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
3d0f8bc7 1791 ca91cx42_bridge->slot_get = ca91cx42_slot_get;
7f58f025
MV		 1792 ca91cx42_bridge->alloc_consistent = ca91cx42_alloc_consistent;
1793 ca91cx42_bridge->free_consistent = ca91cx42_free_consistent;
3d0f8bc7 1794
29848ac9 1795 data = ioread32(ca91cx42_device->base + MISC_CTL);
3d0f8bc7
MW		 1796 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1797 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
29848ac9
MW		 1798 dev_info(&pdev->dev, "Slot ID is %d\n",
1799 ca91cx42_slot_get(ca91cx42_bridge));
3d0f8bc7 1800
7946328f 1801 if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))
3d0f8bc7 1802 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
60479690 1803
3d0f8bc7
MW		 1804 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1805 * ca91cx42_remove()
1806 */
1807 retval = vme_register_bridge(ca91cx42_bridge);
1808 if (retval != 0) {
1809 dev_err(&pdev->dev, "Chip Registration failed.\n");
1810 goto err_reg;
1811 }
1812
29848ac9
MW		 1813 pci_set_drvdata(pdev, ca91cx42_bridge);
1814
3d0f8bc7
MW		 1815 return 0;
1816
3d0f8bc7 1817err_reg:
29848ac9 1818 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
3d0f8bc7
MW		 1819err_lm:
1820 /* resources are stored in link list */
43f5e46c 1821 list_for_each_safe(pos, n, &ca91cx42_bridge->lm_resources) {
3d0f8bc7
MW		 1822 lm = list_entry(pos, struct vme_lm_resource, list);
1823 list_del(pos);
1824 kfree(lm);
1825 }
3d0f8bc7
MW		 1826err_dma:
1827 /* resources are stored in link list */
43f5e46c 1828 list_for_each_safe(pos, n, &ca91cx42_bridge->dma_resources) {
3d0f8bc7
MW		 1829 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1830 list_del(pos);
1831 kfree(dma_ctrlr);
60479690 1832 }
3d0f8bc7
MW		 1833err_slave:
1834 /* resources are stored in link list */
43f5e46c 1835 list_for_each_safe(pos, n, &ca91cx42_bridge->slave_resources) {
3d0f8bc7
MW		 1836 slave_image = list_entry(pos, struct vme_slave_resource, list);
1837 list_del(pos);
1838 kfree(slave_image);
1839 }
1840err_master:
1841 /* resources are stored in link list */
43f5e46c 1842 list_for_each_safe(pos, n, &ca91cx42_bridge->master_resources) {
3d0f8bc7
MW		 1843 master_image = list_entry(pos, struct vme_master_resource,
1844 list);
1845 list_del(pos);
1846 kfree(master_image);
1847 }
1848
29848ac9 1849 ca91cx42_irq_exit(ca91cx42_device, pdev);
3d0f8bc7
MW		 1850err_irq:
1851err_test:
29848ac9 1852 iounmap(ca91cx42_device->base);
3d0f8bc7
MW		 1853err_remap:
1854 pci_release_regions(pdev);
1855err_resource:
1856 pci_disable_device(pdev);
1857err_enable:
29848ac9
MW		 1858 kfree(ca91cx42_device);
1859err_driver:
3d0f8bc7
MW		 1860 kfree(ca91cx42_bridge);
1861err_struct:
1862 return retval;
60479690 1863
60479690
MW		 1864}
1865
efbb979d 1866static void ca91cx42_remove(struct pci_dev *pdev)
60479690 1867{
43f5e46c 1868 struct list_head *pos = NULL, *n;
3d0f8bc7
MW		 1869 struct vme_master_resource *master_image;
1870 struct vme_slave_resource *slave_image;
1871 struct vme_dma_resource *dma_ctrlr;
1872 struct vme_lm_resource *lm;
29848ac9
MW		 1873 struct ca91cx42_driver *bridge;
1874 struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1875
1876 bridge = ca91cx42_bridge->driver_priv;
1877
60479690 1878
3d0f8bc7 1879 /* Turn off Ints */
29848ac9 1880 iowrite32(0, bridge->base + LINT_EN);
3d0f8bc7
MW		 1881
1882 /* Turn off the windows */
29848ac9
MW		 1883 iowrite32(0x00800000, bridge->base + LSI0_CTL);
1884 iowrite32(0x00800000, bridge->base + LSI1_CTL);
1885 iowrite32(0x00800000, bridge->base + LSI2_CTL);
1886 iowrite32(0x00800000, bridge->base + LSI3_CTL);
1887 iowrite32(0x00800000, bridge->base + LSI4_CTL);
1888 iowrite32(0x00800000, bridge->base + LSI5_CTL);
1889 iowrite32(0x00800000, bridge->base + LSI6_CTL);
1890 iowrite32(0x00800000, bridge->base + LSI7_CTL);
1891 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1892 iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1893 iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1894 iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1895 iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1896 iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1897 iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1898 iowrite32(0x00F00000, bridge->base + VSI7_CTL);
3d0f8bc7
MW		 1899
1900 vme_unregister_bridge(ca91cx42_bridge);
bb9ea89e
MW		 1901
1902 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1903
3d0f8bc7 1904 /* resources are stored in link list */
43f5e46c 1905 list_for_each_safe(pos, n, &ca91cx42_bridge->lm_resources) {
3d0f8bc7
MW		 1906 lm = list_entry(pos, struct vme_lm_resource, list);
1907 list_del(pos);
1908 kfree(lm);
60479690 1909 }
3d0f8bc7
MW		 1910
1911 /* resources are stored in link list */
43f5e46c 1912 list_for_each_safe(pos, n, &ca91cx42_bridge->dma_resources) {
3d0f8bc7
MW		 1913 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1914 list_del(pos);
1915 kfree(dma_ctrlr);
60479690
MW		 1916 }
1917
3d0f8bc7 1918 /* resources are stored in link list */
43f5e46c 1919 list_for_each_safe(pos, n, &ca91cx42_bridge->slave_resources) {
3d0f8bc7
MW		 1920 slave_image = list_entry(pos, struct vme_slave_resource, list);
1921 list_del(pos);
1922 kfree(slave_image);
1923 }
60479690 1924
3d0f8bc7 1925 /* resources are stored in link list */
43f5e46c 1926 list_for_each_safe(pos, n, &ca91cx42_bridge->master_resources) {
3d0f8bc7
MW		 1927 master_image = list_entry(pos, struct vme_master_resource,
1928 list);
1929 list_del(pos);
1930 kfree(master_image);
1931 }
60479690 1932
29848ac9 1933 ca91cx42_irq_exit(bridge, pdev);
60479690 1934
29848ac9 1935 iounmap(bridge->base);
60479690 1936
3d0f8bc7 1937 pci_release_regions(pdev);
60479690 1938
3d0f8bc7
MW		 1939 pci_disable_device(pdev);
1940
1941 kfree(ca91cx42_bridge);
60479690
MW		 1942}
1943
c7b50a2a 1944module_pci_driver(ca91cx42_driver);
60479690 1945
12b2d5c0
MW		 1946MODULE_PARM_DESC(geoid, "Override geographical addressing");
1947module_param(geoid, int, 0);
1948
3d0f8bc7
MW		 1949MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1950MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)