[linux-2.6-block.git] / drivers / video / xilinxfb.c

/*
 * xilinxfb.c
 *
 * Xilinx TFT LCD frame buffer driver
 *
 * Author: MontaVista Software, Inc.
 *         source@mvista.com
 *
 * 2002-2007 (c) MontaVista Software, Inc.
 * 2007 (c) Secret Lab Technologies, Ltd.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/*
 * This driver was based on au1100fb.c by MontaVista rewritten for 2.6
 * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn
 * was based on skeletonfb.c, Skeleton for a frame buffer device by
 * Geert Uytterhoeven.
 */

#include <linux/device.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#if defined(CONFIG_OF)
#include <linux/of_device.h>
#include <linux/of_platform.h>
#endif
#include <asm/io.h>
#include <linux/xilinxfb.h>

#define DRIVER_NAME		"xilinxfb"
#define DRIVER_DESCRIPTION	"Xilinx TFT LCD frame buffer driver"

/*
 * Xilinx calls it "PLB TFT LCD Controller" though it can also be used for
 * the VGA port on the Xilinx ML40x board. This is a hardware display controller
 * for a 640x480 resolution TFT or VGA screen.
 *
 * The interface to the framebuffer is nice and simple.  There are two
 * control registers.  The first tells the LCD interface where in memory
 * the frame buffer is (only the 11 most significant bits are used, so
 * don't start thinking about scrolling).  The second allows the LCD to
 * be turned on or off as well as rotated 180 degrees.
 */
#define NUM_REGS	2
#define REG_FB_ADDR	0
#define REG_CTRL	1
#define REG_CTRL_ENABLE	 0x0001
#define REG_CTRL_ROTATE	 0x0002

/*
 * The hardware only handles a single mode: 640x480 24 bit true
 * color. Each pixel gets a word (32 bits) of memory.  Within each word,
 * the 8 most significant bits are ignored, the next 8 bits are the red
 * level, the next 8 bits are the green level and the 8 least
 * significant bits are the blue level.  Each row of the LCD uses 1024
 * words, but only the first 640 pixels are displayed with the other 384
 * words being ignored.  There are 480 rows.
 */
#define BYTES_PER_PIXEL	4
#define BITS_PER_PIXEL	(BYTES_PER_PIXEL * 8)

#define RED_SHIFT	16
#define GREEN_SHIFT	8
#define BLUE_SHIFT	0

#define PALETTE_ENTRIES_NO	16	/* passed to fb_alloc_cmap() */

/*
 * Default xilinxfb configuration
 */
static struct xilinxfb_platform_data xilinx_fb_default_pdata = {
	.xres = 640,
	.yres = 480,
	.xvirt = 1024,
	.yvirt = 480,
};

/*
 * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
 */
static struct fb_fix_screeninfo xilinx_fb_fix = {
	.id =		"Xilinx",
	.type =		FB_TYPE_PACKED_PIXELS,
	.visual =	FB_VISUAL_TRUECOLOR,
	.accel =	FB_ACCEL_NONE
};

static struct fb_var_screeninfo xilinx_fb_var = {
	.bits_per_pixel =	BITS_PER_PIXEL,

	.red =		{ RED_SHIFT, 8, 0 },
	.green =	{ GREEN_SHIFT, 8, 0 },
	.blue =		{ BLUE_SHIFT, 8, 0 },
	.transp =	{ 0, 0, 0 },

	.activate =	FB_ACTIVATE_NOW
};

struct xilinxfb_drvdata {

	struct fb_info	info;		/* FB driver info record */

	u32		regs_phys;	/* phys. address of the control registers */
	u32 __iomem	*regs;		/* virt. address of the control registers */

	void		*fb_virt;	/* virt. address of the frame buffer */
	dma_addr_t	fb_phys;	/* phys. address of the frame buffer */
	int		fb_alloced;	/* Flag, was the fb memory alloced? */

	u32		reg_ctrl_default;

	u32		pseudo_palette[PALETTE_ENTRIES_NO];
					/* Fake palette of 16 colors */
};

#define to_xilinxfb_drvdata(_info) \
	container_of(_info, struct xilinxfb_drvdata, info)

/*
 * The LCD controller has DCR interface to its registers, but all
 * the boards and configurations the driver has been tested with
 * use opb2dcr bridge. So the registers are seen as memory mapped.
 * This macro is to make it simple to add the direct DCR access
 * when it's needed.
 */
#define xilinx_fb_out_be32(driverdata, offset, val) \
	out_be32(driverdata->regs + offset, val)

static int
xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
	unsigned transp, struct fb_info *fbi)
{
	u32 *palette = fbi->pseudo_palette;

	if (regno >= PALETTE_ENTRIES_NO)
		return -EINVAL;

	if (fbi->var.grayscale) {
		/* Convert color to grayscale.
		 * grayscale = 0.30*R + 0.59*G + 0.11*B */
		red = green = blue =
			(red * 77 + green * 151 + blue * 28 + 127) >> 8;
	}

	/* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */

	/* We only handle 8 bits of each color. */
	red >>= 8;
	green >>= 8;
	blue >>= 8;
	palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
			 (blue << BLUE_SHIFT);

	return 0;
}

static int
xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
{
	struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);

	switch (blank_mode) {
	case FB_BLANK_UNBLANK:
		/* turn on panel */
		xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
		break;

	case FB_BLANK_NORMAL:
	case FB_BLANK_VSYNC_SUSPEND:
	case FB_BLANK_HSYNC_SUSPEND:
	case FB_BLANK_POWERDOWN:
		/* turn off panel */
		xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
	default:
		break;

	}
	return 0; /* success */
}

static struct fb_ops xilinxfb_ops =
{
	.owner			= THIS_MODULE,
	.fb_setcolreg		= xilinx_fb_setcolreg,
	.fb_blank		= xilinx_fb_blank,
	.fb_fillrect		= cfb_fillrect,
	.fb_copyarea		= cfb_copyarea,
	.fb_imageblit		= cfb_imageblit,
};

/* ---------------------------------------------------------------------
 * Bus independent setup/teardown
 */

static int xilinxfb_assign(struct device *dev, unsigned long physaddr,
			   struct xilinxfb_platform_data *pdata)
{
	struct xilinxfb_drvdata *drvdata;
	int rc;
	int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;

	/* Allocate the driver data region */
	drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
	if (!drvdata) {
		dev_err(dev, "Couldn't allocate device private record\n");
		return -ENOMEM;
	}
	dev_set_drvdata(dev, drvdata);

	/* Map the control registers in */
	if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
		dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
			physaddr);
		rc = -ENODEV;
		goto err_region;
	}
	drvdata->regs_phys = physaddr;
	drvdata->regs = ioremap(physaddr, 8);
	if (!drvdata->regs) {
		dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
			physaddr);
		rc = -ENODEV;
		goto err_map;
	}

	/* Allocate the framebuffer memory */
	if (pdata->fb_phys) {
		drvdata->fb_phys = pdata->fb_phys;
		drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
	} else {
		drvdata->fb_alloced = 1;
		drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
					&drvdata->fb_phys, GFP_KERNEL);
	}

	if (!drvdata->fb_virt) {
		dev_err(dev, "Could not allocate frame buffer memory\n");
		rc = -ENOMEM;
		goto err_fbmem;
	}

	/* Clear (turn to black) the framebuffer */
	memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);

	/* Tell the hardware where the frame buffer is */
	xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata->fb_phys);

	/* Turn on the display */
	drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
	if (pdata->rotate_screen)
		drvdata->reg_ctrl_default |= REG_CTRL_ROTATE;
	xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);

	/* Fill struct fb_info */
	drvdata->info.device = dev;
	drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
	drvdata->info.fbops = &xilinxfb_ops;
	drvdata->info.fix = xilinx_fb_fix;
	drvdata->info.fix.smem_start = drvdata->fb_phys;
	drvdata->info.fix.smem_len = fbsize;
	drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;

	drvdata->info.pseudo_palette = drvdata->pseudo_palette;
	drvdata->info.flags = FBINFO_DEFAULT;
	drvdata->info.var = xilinx_fb_var;
	drvdata->info.var.height = pdata->screen_height_mm;
	drvdata->info.var.width = pdata->screen_width_mm;
	drvdata->info.var.xres = pdata->xres;
	drvdata->info.var.yres = pdata->yres;
	drvdata->info.var.xres_virtual = pdata->xvirt;
	drvdata->info.var.yres_virtual = pdata->yvirt;

	/* Allocate a colour map */
	rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
	if (rc) {
		dev_err(dev, "Fail to allocate colormap (%d entries)\n",
			PALETTE_ENTRIES_NO);
		goto err_cmap;
	}

	/* Register new frame buffer */
	rc = register_framebuffer(&drvdata->info);
	if (rc) {
		dev_err(dev, "Could not register frame buffer\n");
		goto err_regfb;
	}

	/* Put a banner in the log (for DEBUG) */
	dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr, drvdata->regs);
	dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
		(unsigned long long) drvdata->fb_phys, drvdata->fb_virt,
		fbsize);

	return 0;	/* success */

err_regfb:
	fb_dealloc_cmap(&drvdata->info.cmap);

err_cmap:
	if (drvdata->fb_alloced)
		dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
			drvdata->fb_phys);
	/* Turn off the display */
	xilinx_fb_out_be32(drvdata, REG_CTRL, 0);

err_fbmem:
	iounmap(drvdata->regs);

err_map:
	release_mem_region(physaddr, 8);

err_region:
	kfree(drvdata);
	dev_set_drvdata(dev, NULL);

	return rc;
}

static int xilinxfb_release(struct device *dev)
{
	struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);

#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
	xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
#endif

	unregister_framebuffer(&drvdata->info);

	fb_dealloc_cmap(&drvdata->info.cmap);

	if (drvdata->fb_alloced)
		dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
				  drvdata->fb_virt, drvdata->fb_phys);

	/* Turn off the display */
	xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
	iounmap(drvdata->regs);

	release_mem_region(drvdata->regs_phys, 8);

	kfree(drvdata);
	dev_set_drvdata(dev, NULL);

	return 0;
}

/* ---------------------------------------------------------------------
 * Platform bus binding
 */

static int
xilinxfb_platform_probe(struct platform_device *pdev)
{
	struct xilinxfb_platform_data *pdata;
	struct resource *res;

	/* Find the registers address */
	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
	if (!res) {
		dev_err(&pdev->dev, "Couldn't get registers resource\n");
		return -ENODEV;
	}

	/* If a pdata structure is provided, then extract the parameters */
	pdata = &xilinx_fb_default_pdata;
	if (pdev->dev.platform_data) {
		pdata = pdev->dev.platform_data;
		if (!pdata->xres)
			pdata->xres = xilinx_fb_default_pdata.xres;
		if (!pdata->yres)
			pdata->yres = xilinx_fb_default_pdata.yres;
		if (!pdata->xvirt)
			pdata->xvirt = xilinx_fb_default_pdata.xvirt;
		if (!pdata->yvirt)
			pdata->yvirt = xilinx_fb_default_pdata.yvirt;
	}

	return xilinxfb_assign(&pdev->dev, res->start, pdata);
}

static int
xilinxfb_platform_remove(struct platform_device *pdev)
{
	return xilinxfb_release(&pdev->dev);
}


static struct platform_driver xilinxfb_platform_driver = {
	.probe		= xilinxfb_platform_probe,
	.remove		= xilinxfb_platform_remove,
	.driver = {
		.owner = THIS_MODULE,
		.name = DRIVER_NAME,
	},
};

/* ---------------------------------------------------------------------
 * OF bus binding
 */

#if defined(CONFIG_OF)
static int __devinit
xilinxfb_of_probe(struct of_device *op, const struct of_device_id *match)
{
	struct resource res;
	const u32 *prop;
	struct xilinxfb_platform_data pdata;
	int size, rc;

	/* Copy with the default pdata (not a ptr reference!) */
	pdata = xilinx_fb_default_pdata;

	dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match);

	rc = of_address_to_resource(op->node, 0, &res);
	if (rc) {
		dev_err(&op->dev, "invalid address\n");
		return rc;
	}

	prop = of_get_property(op->node, "phys-size", &size);
	if ((prop) && (size >= sizeof(u32)*2)) {
		pdata.screen_width_mm = prop[0];
		pdata.screen_height_mm = prop[1];
	}

	prop = of_get_property(op->node, "resolution", &size);
	if ((prop) && (size >= sizeof(u32)*2)) {
		pdata.xres = prop[0];
		pdata.yres = prop[1];
	}

	prop = of_get_property(op->node, "virtual-resolution", &size);
	if ((prop) && (size >= sizeof(u32)*2)) {
		pdata.xvirt = prop[0];
		pdata.yvirt = prop[1];
	}

	if (of_find_property(op->node, "rotate-display", NULL))
		pdata.rotate_screen = 1;

	return xilinxfb_assign(&op->dev, res.start, &pdata);
}

static int __devexit xilinxfb_of_remove(struct of_device *op)
{
	return xilinxfb_release(&op->dev);
}

/* Match table for of_platform binding */
static struct of_device_id xilinxfb_of_match[] __devinitdata = {
	{ .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
	{},
};
MODULE_DEVICE_TABLE(of, xilinxfb_of_match);

static struct of_platform_driver xilinxfb_of_driver = {
	.owner = THIS_MODULE,
	.name = DRIVER_NAME,
	.match_table = xilinxfb_of_match,
	.probe = xilinxfb_of_probe,
	.remove = __devexit_p(xilinxfb_of_remove),
	.driver = {
		.name = DRIVER_NAME,
	},
};

/* Registration helpers to keep the number of #ifdefs to a minimum */
static inline int __init xilinxfb_of_register(void)
{
	pr_debug("xilinxfb: calling of_register_platform_driver()\n");
	return of_register_platform_driver(&xilinxfb_of_driver);
}

static inline void __exit xilinxfb_of_unregister(void)
{
	of_unregister_platform_driver(&xilinxfb_of_driver);
}
#else /* CONFIG_OF */
/* CONFIG_OF not enabled; do nothing helpers */
static inline int __init xilinxfb_of_register(void) { return 0; }
static inline void __exit xilinxfb_of_unregister(void) { }
#endif /* CONFIG_OF */

/* ---------------------------------------------------------------------
 * Module setup and teardown
 */

static int __init
xilinxfb_init(void)
{
	int rc;
	rc = xilinxfb_of_register();
	if (rc)
		return rc;

	rc = platform_driver_register(&xilinxfb_platform_driver);
	if (rc)
		xilinxfb_of_unregister();

	return rc;
}

static void __exit
xilinxfb_cleanup(void)
{
	platform_driver_unregister(&xilinxfb_platform_driver);
	xilinxfb_of_unregister();
}

module_init(xilinxfb_init);
module_exit(xilinxfb_cleanup);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION(DRIVER_DESCRIPTION);
MODULE_LICENSE("GPL");
Commit	Line	Data
147394c8 AK	1	/*
	2	* xilinxfb.c
	3	*
	4	* Xilinx TFT LCD frame buffer driver
	5	*
	6	* Author: MontaVista Software, Inc.
	7	* source@mvista.com
	8	*
31e8d460 GL	9	* 2002-2007 (c) MontaVista Software, Inc.
	10	* 2007 (c) Secret Lab Technologies, Ltd.
	11	*
	12	* This file is licensed under the terms of the GNU General Public License
	13	* version 2. This program is licensed "as is" without any warranty of any
	14	* kind, whether express or implied.
147394c8 AK	15	*/
	16
	17	/*
	18	* This driver was based on au1100fb.c by MontaVista rewritten for 2.6
	19	* by Embedded Alley Solutions <source@embeddedalley.com>, which in turn
	20	* was based on skeletonfb.c, Skeleton for a frame buffer device by
	21	* Geert Uytterhoeven.
	22	*/
	23
3cb3ec2c	24	#include <linux/device.h>
147394c8 AK	25	#include <linux/module.h>
147394c8 AK	26	#include <linux/kernel.h>
147394c8 AK	27	#include <linux/errno.h>
	28	#include <linux/string.h>
	29	#include <linux/mm.h>
	30	#include <linux/fb.h>
	31	#include <linux/init.h>
	32	#include <linux/dma-mapping.h>
	33	#include <linux/platform_device.h>
31e8d460 GL	34	#if defined(CONFIG_OF)
	35	#include <linux/of_device.h>
	36	#include <linux/of_platform.h>
	37	#endif
147394c8	38	#include <asm/io.h>
dc8afdc7	39	#include <linux/xilinxfb.h>
147394c8 AK	40
	41	#define DRIVER_NAME "xilinxfb"
	42	#define DRIVER_DESCRIPTION "Xilinx TFT LCD frame buffer driver"
	43
	44	/*
	45	* Xilinx calls it "PLB TFT LCD Controller" though it can also be used for
	46	* the VGA port on the Xilinx ML40x board. This is a hardware display controller
	47	* for a 640x480 resolution TFT or VGA screen.
	48	*
	49	* The interface to the framebuffer is nice and simple. There are two
	50	* control registers. The first tells the LCD interface where in memory
	51	* the frame buffer is (only the 11 most significant bits are used, so
	52	* don't start thinking about scrolling). The second allows the LCD to
	53	* be turned on or off as well as rotated 180 degrees.
	54	*/
	55	#define NUM_REGS 2
	56	#define REG_FB_ADDR 0
	57	#define REG_CTRL 1
	58	#define REG_CTRL_ENABLE 0x0001
	59	#define REG_CTRL_ROTATE 0x0002
	60
	61	/*
	62	* The hardware only handles a single mode: 640x480 24 bit true
	63	* color. Each pixel gets a word (32 bits) of memory. Within each word,
	64	* the 8 most significant bits are ignored, the next 8 bits are the red
	65	* level, the next 8 bits are the green level and the 8 least
	66	* significant bits are the blue level. Each row of the LCD uses 1024
	67	* words, but only the first 640 pixels are displayed with the other 384
	68	* words being ignored. There are 480 rows.
	69	*/
	70	#define BYTES_PER_PIXEL 4
	71	#define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8)
147394c8 AK	72
	73	#define RED_SHIFT 16
	74	#define GREEN_SHIFT 8
	75	#define BLUE_SHIFT 0
	76
	77	#define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */
	78
01ba1e9d GL	79	/*
	80	* Default xilinxfb configuration
	81	*/
	82	static struct xilinxfb_platform_data xilinx_fb_default_pdata = {
b4d6a726 GL	83	.xres = 640,
	84	.yres = 480,
	85	.xvirt = 1024,
86a2249d	86	.yvirt = 480,
01ba1e9d GL	87	};
01ba1e9d GL	88
147394c8 AK	89	/*
	90	* Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
	91	*/
3f5b85d1	92	static struct fb_fix_screeninfo xilinx_fb_fix = {
147394c8 AK	93	.id = "Xilinx",
	94	.type = FB_TYPE_PACKED_PIXELS,
	95	.visual = FB_VISUAL_TRUECOLOR,
147394c8 AK	96	.accel = FB_ACCEL_NONE
	97	};
	98
3f5b85d1	99	static struct fb_var_screeninfo xilinx_fb_var = {
147394c8 AK	100	.bits_per_pixel = BITS_PER_PIXEL,
	101
	102	.red = { RED_SHIFT, 8, 0 },
	103	.green = { GREEN_SHIFT, 8, 0 },
	104	.blue = { BLUE_SHIFT, 8, 0 },
	105	.transp = { 0, 0, 0 },
	106
	107	.activate = FB_ACTIVATE_NOW
	108	};
	109
	110	struct xilinxfb_drvdata {
	111
	112	struct fb_info info; /* FB driver info record */
	113
	114	u32 regs_phys; /* phys. address of the control registers */
	115	u32 __iomem regs; / virt. address of the control registers */
	116
b9a22794	117	void fb_virt; / virt. address of the frame buffer */
147394c8	118	dma_addr_t fb_phys; /* phys. address of the frame buffer */
287e5d6f	119	int fb_alloced; /* Flag, was the fb memory alloced? */
147394c8 AK	120
	121	u32 reg_ctrl_default;
	122
	123	u32 pseudo_palette[PALETTE_ENTRIES_NO];
	124	/* Fake palette of 16 colors */
	125	};
	126
	127	#define to_xilinxfb_drvdata(_info) \
	128	container_of(_info, struct xilinxfb_drvdata, info)
	129
	130	/*
	131	* The LCD controller has DCR interface to its registers, but all
	132	* the boards and configurations the driver has been tested with
	133	* use opb2dcr bridge. So the registers are seen as memory mapped.
	134	* This macro is to make it simple to add the direct DCR access
	135	* when it's needed.
	136	*/
	137	#define xilinx_fb_out_be32(driverdata, offset, val) \
	138	out_be32(driverdata->regs + offset, val)
	139
	140	static int
	141	xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
	142	unsigned transp, struct fb_info *fbi)
	143	{
	144	u32 *palette = fbi->pseudo_palette;
	145
	146	if (regno >= PALETTE_ENTRIES_NO)
	147	return -EINVAL;
	148
	149	if (fbi->var.grayscale) {
	150	/* Convert color to grayscale.
	151	* grayscale = 0.30R + 0.59G + 0.11B /
	152	red = green = blue =
	153	(red * 77 + green * 151 + blue * 28 + 127) >> 8;
	154	}
	155
	156	/* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */
	157
	158	/* We only handle 8 bits of each color. */
	159	red >>= 8;
	160	green >>= 8;
	161	blue >>= 8;
	162	palette[regno] = (red << RED_SHIFT) \| (green << GREEN_SHIFT) \|
	163	(blue << BLUE_SHIFT);
	164
	165	return 0;
	166	}
	167
	168	static int
	169	xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
	170	{
	171	struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
	172
	173	switch (blank_mode) {
	174	case FB_BLANK_UNBLANK:
	175	/* turn on panel */
	176	xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
	177	break;
	178
	179	case FB_BLANK_NORMAL:
	180	case FB_BLANK_VSYNC_SUSPEND:
	181	case FB_BLANK_HSYNC_SUSPEND:
	182	case FB_BLANK_POWERDOWN:
	183	/* turn off panel */
184	xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
185	default:
186	break;
187
188	}
189	return 0; /* success */
190	}
191
192	static struct fb_ops xilinxfb_ops =
193	{
194	.owner = THIS_MODULE,
195	.fb_setcolreg = xilinx_fb_setcolreg,
196	.fb_blank = xilinx_fb_blank,
197	.fb_fillrect = cfb_fillrect,
198	.fb_copyarea = cfb_copyarea,
199	.fb_imageblit = cfb_imageblit,
200	};
201
26477622 GL	202	/* ---------------------------------------------------------------------
	203	* Bus independent setup/teardown
	204	*/
147394c8	205
26477622	206	static int xilinxfb_assign(struct device *dev, unsigned long physaddr,
01ba1e9d	207	struct xilinxfb_platform_data *pdata)
147394c8	208	{
147394c8	209	struct xilinxfb_drvdata *drvdata;
26477622	210	int rc;
b4d6a726	211	int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
147394c8	212
26477622	213	/* Allocate the driver data region */
147394c8 AK	214	drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
147394c8 AK	215	if (!drvdata) {
3cb3ec2c	216	dev_err(dev, "Couldn't allocate device private record\n");
147394c8 AK	217	return -ENOMEM;
	218	}
	219	dev_set_drvdata(dev, drvdata);
	220
	221	/* Map the control registers in */
26477622 GL	222	if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
	223	dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
	224	physaddr);
	225	rc = -ENODEV;
3fb99ce4	226	goto err_region;
147394c8	227	}
26477622 GL	228	drvdata->regs_phys = physaddr;
	229	drvdata->regs = ioremap(physaddr, 8);
	230	if (!drvdata->regs) {
	231	dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
	232	physaddr);
	233	rc = -ENODEV;
	234	goto err_map;
147394c8	235	}
147394c8 AK	236
147394c8 AK	237	/* Allocate the framebuffer memory */
287e5d6f GL	238	if (pdata->fb_phys) {
	239	drvdata->fb_phys = pdata->fb_phys;
	240	drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
	241	} else {
	242	drvdata->fb_alloced = 1;
	243	drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
	244	&drvdata->fb_phys, GFP_KERNEL);
	245	}
	246
147394c8	247	if (!drvdata->fb_virt) {
3cb3ec2c	248	dev_err(dev, "Could not allocate frame buffer memory\n");
26477622	249	rc = -ENOMEM;
3fb99ce4	250	goto err_fbmem;
147394c8 AK	251	}
	252
	253	/* Clear (turn to black) the framebuffer */
b4d6a726	254	memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);
147394c8 AK	255
	256	/* Tell the hardware where the frame buffer is */
	257	xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
	258
	259	/* Turn on the display */
f53161d1	260	drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
01ba1e9d	261	if (pdata->rotate_screen)
f53161d1	262	drvdata->reg_ctrl_default \|= REG_CTRL_ROTATE;
147394c8 AK	263	xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
	264
	265	/* Fill struct fb_info */
	266	drvdata->info.device = dev;
b9a22794	267	drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
147394c8 AK	268	drvdata->info.fbops = &xilinxfb_ops;
	269	drvdata->info.fix = xilinx_fb_fix;
	270	drvdata->info.fix.smem_start = drvdata->fb_phys;
b4d6a726 GL	271	drvdata->info.fix.smem_len = fbsize;
	272	drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;
	273
147394c8	274	drvdata->info.pseudo_palette = drvdata->pseudo_palette;
26477622 GL	275	drvdata->info.flags = FBINFO_DEFAULT;
26477622 GL	276	drvdata->info.var = xilinx_fb_var;
b4d6a726 GL	277	drvdata->info.var.height = pdata->screen_height_mm;
	278	drvdata->info.var.width = pdata->screen_width_mm;
	279	drvdata->info.var.xres = pdata->xres;
	280	drvdata->info.var.yres = pdata->yres;
	281	drvdata->info.var.xres_virtual = pdata->xvirt;
	282	drvdata->info.var.yres_virtual = pdata->yvirt;
147394c8	283
26477622 GL	284	/* Allocate a colour map */
	285	rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
	286	if (rc) {
3cb3ec2c	287	dev_err(dev, "Fail to allocate colormap (%d entries)\n",
147394c8	288	PALETTE_ENTRIES_NO);
3fb99ce4	289	goto err_cmap;
147394c8 AK	290	}
147394c8 AK	291
147394c8	292	/* Register new frame buffer */
26477622 GL	293	rc = register_framebuffer(&drvdata->info);
26477622 GL	294	if (rc) {
3cb3ec2c	295	dev_err(dev, "Could not register frame buffer\n");
3fb99ce4	296	goto err_regfb;
147394c8 AK	297	}
147394c8 AK	298
258de4ba	299	/* Put a banner in the log (for DEBUG) */
26477622	300	dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr, drvdata->regs);
a1080968 GL	301	dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
	302	(unsigned long long) drvdata->fb_phys, drvdata->fb_virt,
	303	fbsize);
b4d6a726	304
147394c8 AK	305	return 0; /* success */
147394c8 AK	306
3fb99ce4	307	err_regfb:
147394c8 AK	308	fb_dealloc_cmap(&drvdata->info.cmap);
147394c8 AK	309
3fb99ce4	310	err_cmap:
287e5d6f GL	311	if (drvdata->fb_alloced)
	312	dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
	313	drvdata->fb_phys);
147394c8 AK	314	/* Turn off the display */
147394c8 AK	315	xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
147394c8	316
3fb99ce4	317	err_fbmem:
26477622 GL	318	iounmap(drvdata->regs);
	319
	320	err_map:
	321	release_mem_region(physaddr, 8);
147394c8	322
3fb99ce4	323	err_region:
147394c8 AK	324	kfree(drvdata);
	325	dev_set_drvdata(dev, NULL);
	326
26477622	327	return rc;
147394c8 AK	328	}
147394c8 AK	329
26477622	330	static int xilinxfb_release(struct device *dev)
147394c8	331	{
26477622	332	struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);
147394c8 AK	333
	334	#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
	335	xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
	336	#endif
	337
	338	unregister_framebuffer(&drvdata->info);
	339
	340	fb_dealloc_cmap(&drvdata->info.cmap);
	341
287e5d6f GL	342	if (drvdata->fb_alloced)
	343	dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
	344	drvdata->fb_virt, drvdata->fb_phys);
147394c8 AK	345
	346	/* Turn off the display */
	347	xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
	348	iounmap(drvdata->regs);
	349
	350	release_mem_region(drvdata->regs_phys, 8);
	351
	352	kfree(drvdata);
	353	dev_set_drvdata(dev, NULL);
	354
	355	return 0;
	356	}
	357
26477622 GL	358	/* ---------------------------------------------------------------------
	359	* Platform bus binding
	360	*/
	361
	362	static int
47473e31	363	xilinxfb_platform_probe(struct platform_device *pdev)
26477622	364	{
26477622 GL	365	struct xilinxfb_platform_data *pdata;
26477622 GL	366	struct resource *res;
26477622 GL	367
	368	/* Find the registers address */
	369	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
	370	if (!res) {
47473e31	371	dev_err(&pdev->dev, "Couldn't get registers resource\n");
26477622 GL	372	return -ENODEV;
	373	}
	374
e3cec003	375	/* If a pdata structure is provided, then extract the parameters */
b4d6a726 GL	376	pdata = &xilinx_fb_default_pdata;
b4d6a726 GL	377	if (pdev->dev.platform_data) {
01ba1e9d	378	pdata = pdev->dev.platform_data;
b4d6a726 GL	379	if (!pdata->xres)
	380	pdata->xres = xilinx_fb_default_pdata.xres;
	381	if (!pdata->yres)
	382	pdata->yres = xilinx_fb_default_pdata.yres;
	383	if (!pdata->xvirt)
	384	pdata->xvirt = xilinx_fb_default_pdata.xvirt;
	385	if (!pdata->yvirt)
	386	pdata->yvirt = xilinx_fb_default_pdata.yvirt;
	387	}
26477622	388
01ba1e9d	389	return xilinxfb_assign(&pdev->dev, res->start, pdata);
26477622 GL	390	}
	391
	392	static int
47473e31	393	xilinxfb_platform_remove(struct platform_device *pdev)
26477622	394	{
47473e31	395	return xilinxfb_release(&pdev->dev);
26477622 GL	396	}
26477622 GL	397
147394c8	398
47473e31 GL	399	static struct platform_driver xilinxfb_platform_driver = {
	400	.probe = xilinxfb_platform_probe,
	401	.remove = xilinxfb_platform_remove,
	402	.driver = {
	403	.owner = THIS_MODULE,
	404	.name = DRIVER_NAME,
	405	},
147394c8 AK	406	};
147394c8 AK	407
31e8d460 GL	408	/* ---------------------------------------------------------------------
	409	* OF bus binding
	410	*/
	411
	412	#if defined(CONFIG_OF)
	413	static int __devinit
	414	xilinxfb_of_probe(struct of_device op, const struct of_device_id match)
	415	{
	416	struct resource res;
	417	const u32 *prop;
01ba1e9d	418	struct xilinxfb_platform_data pdata;
31e8d460 GL	419	int size, rc;
31e8d460 GL	420
01ba1e9d GL	421	/* Copy with the default pdata (not a ptr reference!) */
	422	pdata = xilinx_fb_default_pdata;
	423
31e8d460 GL	424	dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match);
	425
	426	rc = of_address_to_resource(op->node, 0, &res);
	427	if (rc) {
	428	dev_err(&op->dev, "invalid address\n");
	429	return rc;
	430	}
	431
b4d6a726	432	prop = of_get_property(op->node, "phys-size", &size);
31e8d460	433	if ((prop) && (size >= sizeof(u32)*2)) {
01ba1e9d GL	434	pdata.screen_width_mm = prop[0];
01ba1e9d GL	435	pdata.screen_height_mm = prop[1];
31e8d460 GL	436	}
31e8d460 GL	437
b4d6a726 GL	438	prop = of_get_property(op->node, "resolution", &size);
	439	if ((prop) && (size >= sizeof(u32)*2)) {
	440	pdata.xres = prop[0];
	441	pdata.yres = prop[1];
	442	}
	443
	444	prop = of_get_property(op->node, "virtual-resolution", &size);
	445	if ((prop) && (size >= sizeof(u32)*2)) {
	446	pdata.xvirt = prop[0];
	447	pdata.yvirt = prop[1];
	448	}
	449
31e8d460	450	if (of_find_property(op->node, "rotate-display", NULL))
01ba1e9d	451	pdata.rotate_screen = 1;
31e8d460	452
01ba1e9d	453	return xilinxfb_assign(&op->dev, res.start, &pdata);
31e8d460 GL	454	}
	455
	456	static int __devexit xilinxfb_of_remove(struct of_device *op)
	457	{
	458	return xilinxfb_release(&op->dev);
	459	}
	460
	461	/* Match table for of_platform binding */
911a3175	462	static struct of_device_id xilinxfb_of_match[] __devinitdata = {
0e349b0e	463	{ .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
31e8d460 GL	464	{},
	465	};
	466	MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
	467
	468	static struct of_platform_driver xilinxfb_of_driver = {
	469	.owner = THIS_MODULE,
	470	.name = DRIVER_NAME,
	471	.match_table = xilinxfb_of_match,
	472	.probe = xilinxfb_of_probe,
	473	.remove = __devexit_p(xilinxfb_of_remove),
	474	.driver = {
	475	.name = DRIVER_NAME,
	476	},
	477	};
	478
	479	/* Registration helpers to keep the number of #ifdefs to a minimum */
	480	static inline int __init xilinxfb_of_register(void)
	481	{
	482	pr_debug("xilinxfb: calling of_register_platform_driver()\n");
	483	return of_register_platform_driver(&xilinxfb_of_driver);
	484	}
	485
	486	static inline void __exit xilinxfb_of_unregister(void)
	487	{
	488	of_unregister_platform_driver(&xilinxfb_of_driver);
	489	}
	490	#else /* CONFIG_OF */
	491	/* CONFIG_OF not enabled; do nothing helpers */
	492	static inline int __init xilinxfb_of_register(void) { return 0; }
	493	static inline void __exit xilinxfb_of_unregister(void) { }
	494	#endif /* CONFIG_OF */
	495
	496	/* ---------------------------------------------------------------------
	497	* Module setup and teardown
	498	*/
	499
147394c8 AK	500	static int __init
	501	xilinxfb_init(void)
	502	{
31e8d460 GL	503	int rc;
	504	rc = xilinxfb_of_register();
	505	if (rc)
	506	return rc;
	507
	508	rc = platform_driver_register(&xilinxfb_platform_driver);
	509	if (rc)
	510	xilinxfb_of_unregister();
	511
	512	return rc;
147394c8 AK	513	}
	514
	515	static void __exit
	516	xilinxfb_cleanup(void)
	517	{
47473e31	518	platform_driver_unregister(&xilinxfb_platform_driver);
31e8d460	519	xilinxfb_of_unregister();
147394c8 AK	520	}
	521
	522	module_init(xilinxfb_init);
	523	module_exit(xilinxfb_cleanup);
	524
	525	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	526	MODULE_DESCRIPTION(DRIVER_DESCRIPTION);
	527	MODULE_LICENSE("GPL");