[linux-2.6-block.git] / drivers / video / via / via_clock.c

/*
 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
 * Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public
 * License as published by the Free Software Foundation;
 * either version 2, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
 * the implied warranty of MERCHANTABILITY or FITNESS FOR
 * A PARTICULAR PURPOSE.See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */
/*
 * clock and PLL management functions
 */

#include <linux/kernel.h>
#include <linux/via-core.h>
#include "via_clock.h"
#include "global.h"
#include "debug.h"

static inline u32 cle266_encode_pll(struct via_pll_config pll)
{
	return (pll.multiplier << 8)
		| (pll.rshift << 6)
		| pll.divisor;
}

static inline u32 k800_encode_pll(struct via_pll_config pll)
{
	return ((pll.divisor - 2) << 16)
		| (pll.rshift << 10)
		| (pll.multiplier - 2);
}

static inline u32 vx855_encode_pll(struct via_pll_config pll)
{
	return (pll.divisor << 16)
		| (pll.rshift << 10)
		| pll.multiplier;
}

static inline void cle266_set_primary_pll_encoded(u32 data)
{
	via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
	via_write_reg(VIASR, 0x46, data & 0xFF);
	via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
	via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
}

static inline void k800_set_primary_pll_encoded(u32 data)
{
	via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
	via_write_reg(VIASR, 0x44, data & 0xFF);
	via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
	via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
	via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
}

static inline void cle266_set_secondary_pll_encoded(u32 data)
{
	via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
	via_write_reg(VIASR, 0x44, data & 0xFF);
	via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
	via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
}

static inline void k800_set_secondary_pll_encoded(u32 data)
{
	via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
	via_write_reg(VIASR, 0x4A, data & 0xFF);
	via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
	via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
	via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
}

static void cle266_set_primary_pll(struct via_pll_config config)
{
	cle266_set_primary_pll_encoded(cle266_encode_pll(config));
}

static void k800_set_primary_pll(struct via_pll_config config)
{
	k800_set_primary_pll_encoded(k800_encode_pll(config));
}

static void vx855_set_primary_pll(struct via_pll_config config)
{
	k800_set_primary_pll_encoded(vx855_encode_pll(config));
}

static void cle266_set_secondary_pll(struct via_pll_config config)
{
	cle266_set_secondary_pll_encoded(cle266_encode_pll(config));
}

static void k800_set_secondary_pll(struct via_pll_config config)
{
	k800_set_secondary_pll_encoded(k800_encode_pll(config));
}

static void vx855_set_secondary_pll(struct via_pll_config config)
{
	k800_set_secondary_pll_encoded(vx855_encode_pll(config));
}

static void set_primary_pll_state(u8 state)
{
	u8 value;

	switch (state) {
	case VIA_STATE_ON:
		value = 0x20;
		break;
	case VIA_STATE_OFF:
		value = 0x00;
		break;
	default:
		return;
	}

	via_write_reg_mask(VIASR, 0x2D, value, 0x30);
}

static void set_secondary_pll_state(u8 state)
{
	u8 value;

	switch (state) {
	case VIA_STATE_ON:
		value = 0x08;
		break;
	case VIA_STATE_OFF:
		value = 0x00;
		break;
	default:
		return;
	}

	via_write_reg_mask(VIASR, 0x2D, value, 0x0C);
}

static void set_primary_clock_state(u8 state)
{
	u8 value;

	switch (state) {
	case VIA_STATE_ON:
		value = 0x20;
		break;
	case VIA_STATE_OFF:
		value = 0x00;
		break;
	default:
		return;
	}

	via_write_reg_mask(VIASR, 0x1B, value, 0x30);
}

static void set_secondary_clock_state(u8 state)
{
	u8 value;

	switch (state) {
	case VIA_STATE_ON:
		value = 0x80;
		break;
	case VIA_STATE_OFF:
		value = 0x00;
		break;
	default:
		return;
	}

	via_write_reg_mask(VIASR, 0x1B, value, 0xC0);
}

static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll)
{
	u8 data = 0;

	switch (source) {
	case VIA_CLKSRC_X1:
		data = 0x00;
		break;
	case VIA_CLKSRC_TVX1:
		data = 0x02;
		break;
	case VIA_CLKSRC_TVPLL:
		data = 0x04; /* 0x06 should be the same */
		break;
	case VIA_CLKSRC_DVP1TVCLKR:
		data = 0x0A;
		break;
	case VIA_CLKSRC_CAP0:
		data = 0xC;
		break;
	case VIA_CLKSRC_CAP1:
		data = 0x0E;
		break;
	}

	if (!use_pll)
		data |= 1;

	return data;
}

static void set_primary_clock_source(enum via_clksrc source, bool use_pll)
{
	u8 data = set_clock_source_common(source, use_pll) << 4;
	via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
}

static void set_secondary_clock_source(enum via_clksrc source, bool use_pll)
{
	u8 data = set_clock_source_common(source, use_pll);
	via_write_reg_mask(VIACR, 0x6C, data, 0x0F);
}

void via_clock_init(struct via_clock *clock, int gfx_chip)
{
	switch (gfx_chip) {
	case UNICHROME_CLE266:
	case UNICHROME_K400:
		clock->set_primary_clock_state = NULL;
		clock->set_primary_clock_source = NULL;
		clock->set_primary_pll_state = NULL;
		clock->set_primary_pll = cle266_set_primary_pll;

		clock->set_secondary_clock_state = NULL;
		clock->set_secondary_clock_source = NULL;
		clock->set_secondary_pll_state = NULL;
		clock->set_secondary_pll = cle266_set_secondary_pll;
		break;
	case UNICHROME_K800:
	case UNICHROME_PM800:
	case UNICHROME_CN700:
	case UNICHROME_CX700:
	case UNICHROME_CN750:
	case UNICHROME_K8M890:
	case UNICHROME_P4M890:
	case UNICHROME_P4M900:
	case UNICHROME_VX800:
		clock->set_primary_clock_state = set_primary_clock_state;
		clock->set_primary_clock_source = set_primary_clock_source;
		clock->set_primary_pll_state = set_primary_pll_state;
		clock->set_primary_pll = k800_set_primary_pll;

		clock->set_secondary_clock_state = set_secondary_clock_state;
		clock->set_secondary_clock_source = set_secondary_clock_source;
		clock->set_secondary_pll_state = set_secondary_pll_state;
		clock->set_secondary_pll = k800_set_secondary_pll;
		break;
	case UNICHROME_VX855:
	case UNICHROME_VX900:
		clock->set_primary_clock_state = set_primary_clock_state;
		clock->set_primary_clock_source = set_primary_clock_source;
		clock->set_primary_pll_state = set_primary_pll_state;
		clock->set_primary_pll = vx855_set_primary_pll;

		clock->set_secondary_clock_state = set_secondary_clock_state;
		clock->set_secondary_clock_source = set_secondary_clock_source;
		clock->set_secondary_pll_state = set_secondary_pll_state;
		clock->set_secondary_pll = vx855_set_secondary_pll;
		break;

	}
}
Commit	Line	Data
2c536f84 FTS	1	/*
	2	* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
	3	* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
	4	* Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public
	8	* License as published by the Free Software Foundation;
	9	* either version 2, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
	13	* the implied warranty of MERCHANTABILITY or FITNESS FOR
	14	* A PARTICULAR PURPOSE.See the GNU General Public License
	15	* for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc.,
	20	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	21	*/
	22	/*
	23	* clock and PLL management functions
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/via-core.h>
	28	#include "via_clock.h"
	29	#include "global.h"
	30	#include "debug.h"
	31
	32	static inline u32 cle266_encode_pll(struct via_pll_config pll)
	33	{
	34	return (pll.multiplier << 8)
	35	\| (pll.rshift << 6)
	36	\| pll.divisor;
	37	}
	38
	39	static inline u32 k800_encode_pll(struct via_pll_config pll)
	40	{
	41	return ((pll.divisor - 2) << 16)
	42	\| (pll.rshift << 10)
	43	\| (pll.multiplier - 2);
	44	}
	45
	46	static inline u32 vx855_encode_pll(struct via_pll_config pll)
	47	{
	48	return (pll.divisor << 16)
	49	\| (pll.rshift << 10)
	50	\| pll.multiplier;
	51	}
	52
	53	static inline void cle266_set_primary_pll_encoded(u32 data)
	54	{
	55	via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
	56	via_write_reg(VIASR, 0x46, data & 0xFF);
	57	via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
	58	via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
	59	}
	60
	61	static inline void k800_set_primary_pll_encoded(u32 data)
	62	{
	63	via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
	64	via_write_reg(VIASR, 0x44, data & 0xFF);
65	via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
66	via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
67	via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
68	}
69
70	static inline void cle266_set_secondary_pll_encoded(u32 data)
71	{
72	via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
73	via_write_reg(VIASR, 0x44, data & 0xFF);
74	via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
75	via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
76	}
77
78	static inline void k800_set_secondary_pll_encoded(u32 data)
79	{
80	via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
81	via_write_reg(VIASR, 0x4A, data & 0xFF);
82	via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
83	via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
84	via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
85	}
86
87	static void cle266_set_primary_pll(struct via_pll_config config)
88	{
89	cle266_set_primary_pll_encoded(cle266_encode_pll(config));
90	}
91
92	static void k800_set_primary_pll(struct via_pll_config config)
93	{
94	k800_set_primary_pll_encoded(k800_encode_pll(config));
95	}
96
97	static void vx855_set_primary_pll(struct via_pll_config config)
98	{
99	k800_set_primary_pll_encoded(vx855_encode_pll(config));
100	}
101
102	static void cle266_set_secondary_pll(struct via_pll_config config)
103	{
104	cle266_set_secondary_pll_encoded(cle266_encode_pll(config));
105	}
106
107	static void k800_set_secondary_pll(struct via_pll_config config)
108	{
109	k800_set_secondary_pll_encoded(k800_encode_pll(config));
110	}
111
112	static void vx855_set_secondary_pll(struct via_pll_config config)
113	{
114	k800_set_secondary_pll_encoded(vx855_encode_pll(config));
115	}
116
117	static void set_primary_pll_state(u8 state)
118	{
119	u8 value;
120
121	switch (state) {
122	case VIA_STATE_ON:
123	value = 0x20;
124	break;
125	case VIA_STATE_OFF:
126	value = 0x00;
127	break;
128	default:
129	return;
130	}
131
132	via_write_reg_mask(VIASR, 0x2D, value, 0x30);
133	}
134
135	static void set_secondary_pll_state(u8 state)
136	{
137	u8 value;
138
139	switch (state) {
140	case VIA_STATE_ON:
141	value = 0x08;
142	break;
143	case VIA_STATE_OFF:
144	value = 0x00;
145	break;
146	default:
147	return;
148	}
149
150	via_write_reg_mask(VIASR, 0x2D, value, 0x0C);
151	}
152
153	static void set_primary_clock_state(u8 state)
154	{
155	u8 value;
156
157	switch (state) {
158	case VIA_STATE_ON:
159	value = 0x20;
160	break;
161	case VIA_STATE_OFF:
162	value = 0x00;
163	break;
164	default:
165	return;
166	}
167
168	via_write_reg_mask(VIASR, 0x1B, value, 0x30);
169	}
170
171	static void set_secondary_clock_state(u8 state)
172	{
173	u8 value;
174
175	switch (state) {
176	case VIA_STATE_ON:
177	value = 0x80;
178	break;
179	case VIA_STATE_OFF:
180	value = 0x00;
181	break;
182	default:
183	return;
184	}
185
186	via_write_reg_mask(VIASR, 0x1B, value, 0xC0);
187	}
188
189	static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll)
190	{
191	u8 data = 0;
192
193	switch (source) {
194	case VIA_CLKSRC_X1:
195	data = 0x00;
196	break;
197	case VIA_CLKSRC_TVX1:
198	data = 0x02;
199	break;
200	case VIA_CLKSRC_TVPLL:
201	data = 0x04; /* 0x06 should be the same */
202	break;
203	case VIA_CLKSRC_DVP1TVCLKR:
204	data = 0x0A;
205	break;
206	case VIA_CLKSRC_CAP0:
207	data = 0xC;
208	break;
209	case VIA_CLKSRC_CAP1:
210	data = 0x0E;
211	break;
212	}
213
214	if (!use_pll)
215	data \|= 1;
216
217	return data;
218	}
219
220	static void set_primary_clock_source(enum via_clksrc source, bool use_pll)
221	{
222	u8 data = set_clock_source_common(source, use_pll) << 4;
223	via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
224	}
225
226	static void set_secondary_clock_source(enum via_clksrc source, bool use_pll)
227	{
228	u8 data = set_clock_source_common(source, use_pll);
229	via_write_reg_mask(VIACR, 0x6C, data, 0x0F);
230	}
231
232	void via_clock_init(struct via_clock *clock, int gfx_chip)
233	{
234	switch (gfx_chip) {
235	case UNICHROME_CLE266:
236	case UNICHROME_K400:
237	clock->set_primary_clock_state = NULL;
238	clock->set_primary_clock_source = NULL;
239	clock->set_primary_pll_state = NULL;
240	clock->set_primary_pll = cle266_set_primary_pll;
241
242	clock->set_secondary_clock_state = NULL;
243	clock->set_secondary_clock_source = NULL;
244	clock->set_secondary_pll_state = NULL;
245	clock->set_secondary_pll = cle266_set_secondary_pll;
246	break;
247	case UNICHROME_K800:
248	case UNICHROME_PM800:
249	case UNICHROME_CN700:
250	case UNICHROME_CX700:
251	case UNICHROME_CN750:
252	case UNICHROME_K8M890:
253	case UNICHROME_P4M890:
254	case UNICHROME_P4M900:
255	case UNICHROME_VX800:
256	clock->set_primary_clock_state = set_primary_clock_state;
257	clock->set_primary_clock_source = set_primary_clock_source;
258	clock->set_primary_pll_state = set_primary_pll_state;
259	clock->set_primary_pll = k800_set_primary_pll;
260
261	clock->set_secondary_clock_state = set_secondary_clock_state;
262	clock->set_secondary_clock_source = set_secondary_clock_source;
263	clock->set_secondary_pll_state = set_secondary_pll_state;
264	clock->set_secondary_pll = k800_set_secondary_pll;
265	break;
266	case UNICHROME_VX855:
267	case UNICHROME_VX900:
268	clock->set_primary_clock_state = set_primary_clock_state;
269	clock->set_primary_clock_source = set_primary_clock_source;
270	clock->set_primary_pll_state = set_primary_pll_state;
271	clock->set_primary_pll = vx855_set_primary_pll;
272
273	clock->set_secondary_clock_state = set_secondary_clock_state;
274	clock->set_secondary_clock_source = set_secondary_clock_source;
275	clock->set_secondary_pll_state = set_secondary_pll_state;
276	clock->set_secondary_pll = vx855_set_secondary_pll;
277	break;
278
279	}
280	}