projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tridentfb: add TGUI 9440 support
[linux-2.6-block.git] / drivers / video / tridentfb.c
CommitLineData
1da177e4
LT		 1/*
2 * Frame buffer driver for Trident Blade and Image series
3 *
245a2c2c 4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
1da177e4
LT		 5 *
6 *
7 * CREDITS:(in order of appearance)
245a2c2c
KH		 8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
1da177e4 14 * TODO:
245a2c2c
KH		 15 * timing value tweaking so it looks good on every monitor in every mode
16 * TGUI acceleration
1da177e4
LT		 17 */
18
1da177e4
LT		 19#include <linux/module.h>
20#include <linux/fb.h>
21#include <linux/init.h>
22#include <linux/pci.h>
23
24#include <linux/delay.h>
10172ed6 25#include <video/vga.h>
1da177e4
LT		 26#include <video/trident.h>
27
122e8ad3 28#define VERSION "0.7.9-NEWAPI"
1da177e4
LT		 29
30struct tridentfb_par {
245a2c2c 31 void __iomem *io_virt; /* iospace virtual memory address */
ea8ee55c 32 u32 pseudo_pal[16];
122e8ad3 33 int chip_id;
6eed8e1e 34 int flatpanel;
d9cad04b
KH		 35 void (*init_accel) (struct tridentfb_par *, int, int);
36 void (*wait_engine) (struct tridentfb_par *);
37 void (*fill_rect)
38 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
39 void (*copy_rect)
40 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
1da177e4
LT		 41};
42
245a2c2c 43static unsigned char eng_oper; /* engine operation... */
1da177e4
LT		 44static struct fb_ops tridentfb_ops;
45
1da177e4 46static struct fb_fix_screeninfo tridentfb_fix = {
245a2c2c 47 .id = "Trident",
1da177e4
LT		 48 .type = FB_TYPE_PACKED_PIXELS,
49 .ypanstep = 1,
50 .visual = FB_VISUAL_PSEUDOCOLOR,
51 .accel = FB_ACCEL_NONE,
52};
53
1da177e4
LT		 54/* defaults which are normally overriden by user values */
55
56/* video mode */
07f41e45 57static char *mode_option __devinitdata = "640x480";
6eed8e1e 58static int bpp __devinitdata = 8;
1da177e4 59
6eed8e1e 60static int noaccel __devinitdata;
1da177e4
LT		 61
62static int center;
63static int stretch;
64
6eed8e1e
KH		 65static int fp __devinitdata;
66static int crt __devinitdata;
1da177e4 67
6eed8e1e
KH		 68static int memsize __devinitdata;
69static int memdiff __devinitdata;
1da177e4
LT		 70static int nativex;
71
07f41e45
KH		 72module_param(mode_option, charp, 0);
73MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
9e3f0ca8
KH		 74module_param_named(mode, mode_option, charp, 0);
75MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
1da177e4
LT		 76module_param(bpp, int, 0);
77module_param(center, int, 0);
78module_param(stretch, int, 0);
79module_param(noaccel, int, 0);
80module_param(memsize, int, 0);
81module_param(memdiff, int, 0);
82module_param(nativex, int, 0);
83module_param(fp, int, 0);
6eed8e1e 84MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
1da177e4 85module_param(crt, int, 0);
6eed8e1e 86MODULE_PARM_DESC(crt, "Define if CRT is connected");
1da177e4 87
6bdf1035
KH		 88static int is_oldclock(int id)
89{
a0d92256
KH		 90 return (id == TGUI9440) ||
91 (id == TGUI9660) ||
0e73a47f
KH		 92 (id == CYBER9320);
93}
94
95static int is_oldprotect(int id)
96{
a0d92256
KH		 97 return (id == TGUI9440) ||
98 (id == TGUI9660) ||
0e73a47f
KH		 99 (id == PROVIDIA9685) ||
100 (id == CYBER9320) ||
101 (id == CYBER9382) ||
102 (id == CYBER9385);
6bdf1035
KH		 103}
104
e0759a5f
KH		 105static int is_blade(int id)
106{
107 return (id == BLADE3D) ||
108 (id == CYBERBLADEE4) ||
109 (id == CYBERBLADEi7) ||
110 (id == CYBERBLADEi7D) ||
111 (id == CYBERBLADEi1) ||
112 (id == CYBERBLADEi1D) ||
113 (id == CYBERBLADEAi1) ||
114 (id == CYBERBLADEAi1D);
115}
116
117static int is_xp(int id)
118{
119 return (id == CYBERBLADEXPAi1) ||
120 (id == CYBERBLADEXPm8) ||
121 (id == CYBERBLADEXPm16);
122}
123
1da177e4
LT		 124static int is3Dchip(int id)
125{
245a2c2c
KH		 126 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
127 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
128 (id == CYBER9397) || (id == CYBER9397DVD) ||
129 (id == CYBER9520) || (id == CYBER9525DVD) ||
130 (id == IMAGE975) || (id == IMAGE985) ||
131 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
132 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
133 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
134 (id == CYBERBLADEXPAi1));
1da177e4
LT		 135}
136
137static int iscyber(int id)
138{
139 switch (id) {
245a2c2c
KH		 140 case CYBER9388:
141 case CYBER9382:
142 case CYBER9385:
143 case CYBER9397:
144 case CYBER9397DVD:
145 case CYBER9520:
146 case CYBER9525DVD:
147 case CYBERBLADEE4:
148 case CYBERBLADEi7D:
149 case CYBERBLADEi1:
150 case CYBERBLADEi1D:
151 case CYBERBLADEAi1:
152 case CYBERBLADEAi1D:
153 case CYBERBLADEXPAi1:
154 return 1;
1da177e4 155
245a2c2c
KH		 156 case CYBER9320:
157 case TGUI9660:
0e73a47f 158 case PROVIDIA9685:
245a2c2c
KH		 159 case IMAGE975:
160 case IMAGE985:
161 case BLADE3D:
162 case CYBERBLADEi7: /* VIA MPV4 integrated version */
163
164 default:
165 /* case CYBERBLDAEXPm8: Strange */
166 /* case CYBERBLDAEXPm16: Strange */
167 return 0;
1da177e4
LT		 168 }
169}
170
306fa6f6
KH		 171static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
172{
173 fb_writeb(val, p->io_virt + reg);
174}
1da177e4 175
306fa6f6
KH		 176static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
177{
178 return fb_readb(p->io_virt + reg);
179}
1da177e4 180
306fa6f6
KH		 181static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
182{
183 fb_writel(v, par->io_virt + r);
184}
185
186static inline u32 readmmr(struct tridentfb_par *par, u16 r)
187{
188 return fb_readl(par->io_virt + r);
189}
1da177e4 190
1da177e4
LT		 191/*
192 * Blade specific acceleration.
193 */
194
245a2c2c 195#define point(x, y) ((y) << 16 | (x))
1da177e4
LT		 196#define STA 0x2120
197#define CMD 0x2144
198#define ROP 0x2148
199#define CLR 0x2160
200#define SR1 0x2100
201#define SR2 0x2104
202#define DR1 0x2108
203#define DR2 0x210C
204
205#define ROP_S 0xCC
206
306fa6f6 207static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
1da177e4 208{
245a2c2c
KH		 209 int v1 = (pitch >> 3) << 20;
210 int tmp = 0, v2;
1da177e4 211 switch (bpp) {
245a2c2c
KH		 212 case 8:
213 tmp = 0;
214 break;
215 case 15:
216 tmp = 5;
217 break;
218 case 16:
219 tmp = 1;
220 break;
221 case 24:
222 case 32:
223 tmp = 2;
224 break;
1da177e4 225 }
245a2c2c 226 v2 = v1 | (tmp << 29);
306fa6f6
KH		 227 writemmr(par, 0x21C0, v2);
228 writemmr(par, 0x21C4, v2);
229 writemmr(par, 0x21B8, v2);
230 writemmr(par, 0x21BC, v2);
231 writemmr(par, 0x21D0, v1);
232 writemmr(par, 0x21D4, v1);
233 writemmr(par, 0x21C8, v1);
234 writemmr(par, 0x21CC, v1);
235 writemmr(par, 0x216C, 0);
1da177e4
LT		 236}
237
306fa6f6 238static void blade_wait_engine(struct tridentfb_par *par)
1da177e4 239{
306fa6f6 240 while (readmmr(par, STA) & 0xFA800000) ;
1da177e4
LT		 241}
242
306fa6f6
KH		 243static void blade_fill_rect(struct tridentfb_par *par,
244 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
1da177e4 245{
306fa6f6
KH		 246 writemmr(par, CLR, c);
247 writemmr(par, ROP, rop ? 0x66 : ROP_S);
248 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
1da177e4 249
306fa6f6
KH		 250 writemmr(par, DR1, point(x, y));
251 writemmr(par, DR2, point(x + w - 1, y + h - 1));
1da177e4
LT		 252}
253
306fa6f6
KH		 254static void blade_copy_rect(struct tridentfb_par *par,
255 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
1da177e4 256{
245a2c2c 257 u32 s1, s2, d1, d2;
1da177e4 258 int direction = 2;
245a2c2c
KH		 259 s1 = point(x1, y1);
260 s2 = point(x1 + w - 1, y1 + h - 1);
261 d1 = point(x2, y2);
262 d2 = point(x2 + w - 1, y2 + h - 1);
1da177e4
LT		 263
264 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
245a2c2c 265 direction = 0;
1da177e4 266
306fa6f6
KH		 267 writemmr(par, ROP, ROP_S);
268 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
1da177e4 269
306fa6f6
KH		 270 writemmr(par, SR1, direction ? s2 : s1);
271 writemmr(par, SR2, direction ? s1 : s2);
272 writemmr(par, DR1, direction ? d2 : d1);
273 writemmr(par, DR2, direction ? d1 : d2);
1da177e4
LT		 274}
275
1da177e4
LT		 276/*
277 * BladeXP specific acceleration functions
278 */
279
280#define ROP_P 0xF0
245a2c2c 281#define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
1da177e4 282
306fa6f6 283static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
1da177e4 284{
245a2c2c 285 int tmp = 0, v1;
1da177e4
LT		 286 unsigned char x = 0;
287
288 switch (bpp) {
245a2c2c
KH		 289 case 8:
290 x = 0;
291 break;
292 case 16:
293 x = 1;
294 break;
295 case 24:
296 x = 3;
297 break;
298 case 32:
299 x = 2;
300 break;
1da177e4
LT		 301 }
302
303 switch (pitch << (bpp >> 3)) {
245a2c2c
KH		 304 case 8192:
305 case 512:
306 x |= 0x00;
307 break;
308 case 1024:
309 x |= 0x04;
310 break;
311 case 2048:
312 x |= 0x08;
313 break;
314 case 4096:
315 x |= 0x0C;
316 break;
1da177e4
LT		 317 }
318
306fa6f6 319 t_outb(par, x, 0x2125);
1da177e4
LT		 320
321 eng_oper = x | 0x40;
322
323 switch (bpp) {
245a2c2c
KH		 324 case 8:
325 tmp = 18;
326 break;
327 case 15:
328 case 16:
329 tmp = 19;
330 break;
331 case 24:
332 case 32:
333 tmp = 20;
334 break;
1da177e4
LT		 335 }
336
337 v1 = pitch << tmp;
338
306fa6f6
KH		 339 writemmr(par, 0x2154, v1);
340 writemmr(par, 0x2150, v1);
341 t_outb(par, 3, 0x2126);
1da177e4
LT		 342}
343
306fa6f6 344static void xp_wait_engine(struct tridentfb_par *par)
1da177e4
LT		 345{
346 int busy;
347 int count, timeout;
348
349 count = 0;
350 timeout = 0;
351 for (;;) {
306fa6f6 352 busy = t_inb(par, STA) & 0x80;
1da177e4
LT		 353 if (busy != 0x80)
354 return;
355 count++;
356 if (count == 10000000) {
357 /* Timeout */
358 count = 9990000;
359 timeout++;
360 if (timeout == 8) {
361 /* Reset engine */
306fa6f6 362 t_outb(par, 0x00, 0x2120);
1da177e4
LT		 363 return;
364 }
365 }
366 }
367}
368
306fa6f6
KH		 369static void xp_fill_rect(struct tridentfb_par *par,
370 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
1da177e4 371{
306fa6f6
KH		 372 writemmr(par, 0x2127, ROP_P);
373 writemmr(par, 0x2158, c);
374 writemmr(par, 0x2128, 0x4000);
375 writemmr(par, 0x2140, masked_point(h, w));
376 writemmr(par, 0x2138, masked_point(y, x));
377 t_outb(par, 0x01, 0x2124);
378 t_outb(par, eng_oper, 0x2125);
1da177e4
LT		 379}
380
306fa6f6
KH		 381static void xp_copy_rect(struct tridentfb_par *par,
382 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
1da177e4
LT		 383{
384 int direction;
245a2c2c 385 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
1da177e4
LT		 386
387 direction = 0x0004;
245a2c2c 388
1da177e4
LT		 389 if ((x1 < x2) && (y1 == y2)) {
390 direction |= 0x0200;
391 x1_tmp = x1 + w - 1;
392 x2_tmp = x2 + w - 1;
393 } else {
394 x1_tmp = x1;
395 x2_tmp = x2;
396 }
245a2c2c 397
1da177e4
LT		 398 if (y1 < y2) {
399 direction |= 0x0100;
400 y1_tmp = y1 + h - 1;
401 y2_tmp = y2 + h - 1;
245a2c2c 402 } else {
1da177e4
LT		 403 y1_tmp = y1;
404 y2_tmp = y2;
405 }
406
306fa6f6
KH		 407 writemmr(par, 0x2128, direction);
408 t_outb(par, ROP_S, 0x2127);
409 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
410 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
411 writemmr(par, 0x2140, masked_point(h, w));
412 t_outb(par, 0x01, 0x2124);
1da177e4
LT		 413}
414
1da177e4
LT		 415/*
416 * Image specific acceleration functions
417 */
306fa6f6 418static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
1da177e4
LT		 419{
420 int tmp = 0;
245a2c2c
KH		 421 switch (bpp) {
422 case 8:
423 tmp = 0;
424 break;
425 case 15:
426 tmp = 5;
427 break;
428 case 16:
429 tmp = 1;
430 break;
431 case 24:
432 case 32:
433 tmp = 2;
434 break;
1da177e4 435 }
306fa6f6
KH		 436 writemmr(par, 0x2120, 0xF0000000);
437 writemmr(par, 0x2120, 0x40000000 | tmp);
438 writemmr(par, 0x2120, 0x80000000);
439 writemmr(par, 0x2144, 0x00000000);
440 writemmr(par, 0x2148, 0x00000000);
441 writemmr(par, 0x2150, 0x00000000);
442 writemmr(par, 0x2154, 0x00000000);
443 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
444 writemmr(par, 0x216C, 0x00000000);
445 writemmr(par, 0x2170, 0x00000000);
446 writemmr(par, 0x217C, 0x00000000);
447 writemmr(par, 0x2120, 0x10000000);
448 writemmr(par, 0x2130, (2047 << 16) | 2047);
1da177e4
LT		 449}
450
306fa6f6 451static void image_wait_engine(struct tridentfb_par *par)
1da177e4 452{
306fa6f6 453 while (readmmr(par, 0x2164) & 0xF0000000) ;
1da177e4
LT		 454}
455
306fa6f6
KH		 456static void image_fill_rect(struct tridentfb_par *par,
457 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
1da177e4 458{
306fa6f6
KH		 459 writemmr(par, 0x2120, 0x80000000);
460 writemmr(par, 0x2120, 0x90000000 | ROP_S);
1da177e4 461
306fa6f6 462 writemmr(par, 0x2144, c);
1da177e4 463
306fa6f6
KH		 464 writemmr(par, DR1, point(x, y));
465 writemmr(par, DR2, point(x + w - 1, y + h - 1));
1da177e4 466
306fa6f6 467 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
1da177e4
LT		 468}
469
306fa6f6
KH		 470static void image_copy_rect(struct tridentfb_par *par,
471 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
1da177e4 472{
245a2c2c 473 u32 s1, s2, d1, d2;
1da177e4 474 int direction = 2;
245a2c2c
KH		 475 s1 = point(x1, y1);
476 s2 = point(x1 + w - 1, y1 + h - 1);
477 d1 = point(x2, y2);
478 d2 = point(x2 + w - 1, y2 + h - 1);
1da177e4 479
245a2c2c
KH		 480 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
481 direction = 0;
482
306fa6f6
KH		 483 writemmr(par, 0x2120, 0x80000000);
484 writemmr(par, 0x2120, 0x90000000 | ROP_S);
245a2c2c 485
306fa6f6
KH		 486 writemmr(par, SR1, direction ? s2 : s1);
487 writemmr(par, SR2, direction ? s1 : s2);
488 writemmr(par, DR1, direction ? d2 : d1);
489 writemmr(par, DR2, direction ? d1 : d2);
490 writemmr(par, 0x2124,
491 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
245a2c2c 492}
1da177e4 493
1da177e4
LT		 494/*
495 * Accel functions called by the upper layers
496 */
497#ifdef CONFIG_FB_TRIDENT_ACCEL
245a2c2c
KH		 498static void tridentfb_fillrect(struct fb_info *info,
499 const struct fb_fillrect *fr)
1da177e4 500{
306fa6f6 501 struct tridentfb_par *par = info->par;
1da177e4 502 int bpp = info->var.bits_per_pixel;
8dad46cf 503 int col = 0;
245a2c2c 504
1da177e4 505 switch (bpp) {
245a2c2c
KH		 506 default:
507 case 8:
508 col |= fr->color;
509 col |= col << 8;
510 col |= col << 16;
511 break;
512 case 16:
513 col = ((u32 *)(info->pseudo_palette))[fr->color];
514 break;
515 case 32:
516 col = ((u32 *)(info->pseudo_palette))[fr->color];
517 break;
518 }
519
d9cad04b 520 par->fill_rect(par, fr->dx, fr->dy, fr->width,
306fa6f6 521 fr->height, col, fr->rop);
d9cad04b 522 par->wait_engine(par);
1da177e4 523}
245a2c2c
KH		 524static void tridentfb_copyarea(struct fb_info *info,
525 const struct fb_copyarea *ca)
1da177e4 526{
306fa6f6
KH		 527 struct tridentfb_par *par = info->par;
528
d9cad04b 529 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
306fa6f6 530 ca->width, ca->height);
d9cad04b 531 par->wait_engine(par);
1da177e4
LT		 532}
533#else /* !CONFIG_FB_TRIDENT_ACCEL */
534#define tridentfb_fillrect cfb_fillrect
535#define tridentfb_copyarea cfb_copyarea
536#endif /* CONFIG_FB_TRIDENT_ACCEL */
537
538
539/*
540 * Hardware access functions
541 */
542
306fa6f6 543static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
1da177e4 544{
10172ed6 545 return vga_mm_rcrt(par->io_virt, reg);
1da177e4
LT		 546}
547
306fa6f6
KH		 548static inline void write3X4(struct tridentfb_par *par, int reg,
549 unsigned char val)
1da177e4 550{
10172ed6 551 vga_mm_wcrt(par->io_virt, reg, val);
1da177e4
LT		 552}
553
10172ed6
KH		 554static inline unsigned char read3CE(struct tridentfb_par *par,
555 unsigned char reg)
1da177e4 556{
10172ed6 557 return vga_mm_rgfx(par->io_virt, reg);
1da177e4
LT		 558}
559
306fa6f6
KH		 560static inline void writeAttr(struct tridentfb_par *par, int reg,
561 unsigned char val)
1da177e4 562{
10172ed6
KH		 563 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
564 vga_mm_wattr(par->io_virt, reg, val);
1da177e4
LT		 565}
566
306fa6f6
KH		 567static inline void write3CE(struct tridentfb_par *par, int reg,
568 unsigned char val)
1da177e4 569{
10172ed6 570 vga_mm_wgfx(par->io_virt, reg, val);
1da177e4
LT		 571}
572
e8ed857c 573static void enable_mmio(void)
1da177e4
LT		 574{
575 /* Goto New Mode */
10172ed6 576 vga_io_rseq(0x0B);
1da177e4
LT		 577
578 /* Unprotect registers */
10172ed6 579 vga_io_wseq(NewMode1, 0x80);
245a2c2c 580
1da177e4 581 /* Enable MMIO */
245a2c2c 582 outb(PCIReg, 0x3D4);
1da177e4 583 outb(inb(0x3D5) | 0x01, 0x3D5);
e8ed857c
KH		 584}
585
306fa6f6 586static void disable_mmio(struct tridentfb_par *par)
e8ed857c 587{
e8ed857c 588 /* Goto New Mode */
10172ed6 589 vga_mm_rseq(par->io_virt, 0x0B);
e8ed857c
KH		 590
591 /* Unprotect registers */
10172ed6 592 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
e8ed857c
KH		 593
594 /* Disable MMIO */
306fa6f6
KH		 595 t_outb(par, PCIReg, 0x3D4);
596 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
1da177e4
LT		 597}
598
306fa6f6
KH		 599static void crtc_unlock(struct tridentfb_par *par)
600{
10172ed6
KH		 601 write3X4(par, VGA_CRTC_V_SYNC_END,
602 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
306fa6f6 603}
1da177e4
LT		 604
605/* Return flat panel's maximum x resolution */
306fa6f6 606static int __devinit get_nativex(struct tridentfb_par *par)
1da177e4 607{
245a2c2c 608 int x, y, tmp;
1da177e4
LT		 609
610 if (nativex)
611 return nativex;
612
306fa6f6 613 tmp = (read3CE(par, VertStretch) >> 4) & 3;
1da177e4
LT		 614
615 switch (tmp) {
245a2c2c
KH		 616 case 0:
617 x = 1280; y = 1024;
618 break;
619 case 2:
620 x = 1024; y = 768;
621 break;
622 case 3:
623 x = 800; y = 600;
624 break;
625 case 4:
626 x = 1400; y = 1050;
627 break;
628 case 1:
629 default:
630 x = 640; y = 480;
631 break;
1da177e4
LT		 632 }
633
634 output("%dx%d flat panel found\n", x, y);
635 return x;
636}
637
638/* Set pitch */
306fa6f6 639static void set_lwidth(struct tridentfb_par *par, int width)
1da177e4 640{
10172ed6 641 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
306fa6f6
KH		 642 write3X4(par, AddColReg,
643 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
1da177e4
LT		 644}
645
646/* For resolutions smaller than FP resolution stretch */
306fa6f6 647static void screen_stretch(struct tridentfb_par *par)
1da177e4 648{
122e8ad3 649 if (par->chip_id != CYBERBLADEXPAi1)
306fa6f6 650 write3CE(par, BiosReg, 0);
245a2c2c 651 else
306fa6f6
KH		 652 write3CE(par, BiosReg, 8);
653 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
654 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
1da177e4
LT		 655}
656
657/* For resolutions smaller than FP resolution center */
306fa6f6 658static void screen_center(struct tridentfb_par *par)
1da177e4 659{
306fa6f6
KH		 660 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
661 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
1da177e4
LT		 662}
663
664/* Address of first shown pixel in display memory */
306fa6f6 665static void set_screen_start(struct tridentfb_par *par, int base)
1da177e4 666{
306fa6f6 667 u8 tmp;
10172ed6
KH		 668 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
669 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
306fa6f6
KH		 670 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
671 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
672 tmp = read3X4(par, CRTHiOrd) & 0xF8;
673 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
1da177e4
LT		 674}
675
1da177e4 676/* Set dotclock frequency */
306fa6f6 677static void set_vclk(struct tridentfb_par *par, unsigned long freq)
1da177e4 678{
245a2c2c 679 int m, n, k;
6bdf1035
KH		 680 unsigned long fi, d, di;
681 unsigned char best_m = 0, best_n = 0, best_k = 0;
682 unsigned char hi, lo;
1da177e4 683
3f275ea3 684 d = 20000;
6bdf1035
KH		 685 for (k = 1; k >= 0; k--)
686 for (m = 0; m < 32; m++)
687 for (n = 0; n < 122; n++) {
3f275ea3 688 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
245a2c2c
KH		 689 if ((di = abs(fi - freq)) < d) {
690 d = di;
6bdf1035
KH		 691 best_n = n;
692 best_m = m;
693 best_k = k;
245a2c2c 694 }
3f275ea3
KH		 695 if (fi > freq)
696 break;
245a2c2c 697 }
6bdf1035
KH		 698
699 if (is_oldclock(par->chip_id)) {
700 lo = best_n | (best_m << 7);
701 hi = (best_m >> 1) | (best_k << 4);
702 } else {
703 lo = best_n;
704 hi = best_m | (best_k << 6);
705 }
706
122e8ad3 707 if (is3Dchip(par->chip_id)) {
10172ed6
KH		 708 vga_mm_wseq(par->io_virt, ClockHigh, hi);
709 vga_mm_wseq(par->io_virt, ClockLow, lo);
1da177e4 710 } else {
c1724fec
KH		 711 t_outb(par, lo, 0x43C8);
712 t_outb(par, hi, 0x43C9);
1da177e4 713 }
245a2c2c 714 debug("VCLK = %X %X\n", hi, lo);
1da177e4
LT		 715}
716
717/* Set number of lines for flat panels*/
306fa6f6 718static void set_number_of_lines(struct tridentfb_par *par, int lines)
1da177e4 719{
306fa6f6 720 int tmp = read3CE(par, CyberEnhance) & 0x8F;
1da177e4
LT		 721 if (lines > 1024)
722 tmp |= 0x50;
723 else if (lines > 768)
724 tmp |= 0x30;
725 else if (lines > 600)
726 tmp |= 0x20;
727 else if (lines > 480)
728 tmp |= 0x10;
306fa6f6 729 write3CE(par, CyberEnhance, tmp);
1da177e4
LT		 730}
731
732/*
733 * If we see that FP is active we assume we have one.
6eed8e1e 734 * Otherwise we have a CRT display. User can override.
1da177e4 735 */
6eed8e1e 736static int __devinit is_flatpanel(struct tridentfb_par *par)
1da177e4
LT		 737{
738 if (fp)
6eed8e1e 739 return 1;
122e8ad3 740 if (crt || !iscyber(par->chip_id))
6eed8e1e
KH		 741 return 0;
742 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
1da177e4
LT		 743}
744
745/* Try detecting the video memory size */
306fa6f6 746static unsigned int __devinit get_memsize(struct tridentfb_par *par)
1da177e4
LT		 747{
748 unsigned char tmp, tmp2;
749 unsigned int k;
750
751 /* If memory size provided by user */
752 if (memsize)
753 k = memsize * Kb;
754 else
122e8ad3 755 switch (par->chip_id) {
245a2c2c
KH		 756 case CYBER9525DVD:
757 k = 2560 * Kb;
758 break;
1da177e4 759 default:
306fa6f6 760 tmp = read3X4(par, SPR) & 0x0F;
1da177e4
LT		 761 switch (tmp) {
762
245a2c2c 763 case 0x01:
b614ce8b 764 k = 512 * Kb;
245a2c2c
KH		 765 break;
766 case 0x02:
767 k = 6 * Mb; /* XP */
768 break;
769 case 0x03:
770 k = 1 * Mb;
771 break;
772 case 0x04:
773 k = 8 * Mb;
774 break;
775 case 0x06:
776 k = 10 * Mb; /* XP */
777 break;
778 case 0x07:
779 k = 2 * Mb;
780 break;
781 case 0x08:
782 k = 12 * Mb; /* XP */
783 break;
784 case 0x0A:
785 k = 14 * Mb; /* XP */
786 break;
787 case 0x0C:
788 k = 16 * Mb; /* XP */
789 break;
790 case 0x0E: /* XP */
791
10172ed6 792 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
245a2c2c
KH		 793 switch (tmp2) {
794 case 0x00:
795 k = 20 * Mb;
796 break;
797 case 0x01:
798 k = 24 * Mb;
799 break;
800 case 0x10:
801 k = 28 * Mb;
802 break;
803 case 0x11:
804 k = 32 * Mb;
805 break;
806 default:
807 k = 1 * Mb;
808 break;
809 }
810 break;
811
812 case 0x0F:
813 k = 4 * Mb;
814 break;
815 default:
816 k = 1 * Mb;
1da177e4 817 break;
1da177e4 818 }
245a2c2c 819 }
1da177e4
LT		 820
821 k -= memdiff * Kb;
245a2c2c 822 output("framebuffer size = %d Kb\n", k / Kb);
1da177e4
LT		 823 return k;
824}
825
826/* See if we can handle the video mode described in var */
245a2c2c
KH		 827static int tridentfb_check_var(struct fb_var_screeninfo *var,
828 struct fb_info *info)
1da177e4 829{
6eed8e1e 830 struct tridentfb_par *par = info->par;
1da177e4
LT		 831 int bpp = var->bits_per_pixel;
832 debug("enter\n");
833
834 /* check color depth */
245a2c2c 835 if (bpp == 24)
1da177e4 836 bpp = var->bits_per_pixel = 32;
245a2c2c 837 /* check whether resolution fits on panel and in memory */
6eed8e1e 838 if (par->flatpanel && nativex && var->xres > nativex)
1da177e4 839 return -EINVAL;
245a2c2c 840 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
1da177e4
LT		 841 return -EINVAL;
842
843 switch (bpp) {
245a2c2c
KH		 844 case 8:
845 var->red.offset = 0;
846 var->green.offset = 0;
847 var->blue.offset = 0;
848 var->red.length = 6;
849 var->green.length = 6;
850 var->blue.length = 6;
851 break;
852 case 16:
853 var->red.offset = 11;
854 var->green.offset = 5;
855 var->blue.offset = 0;
856 var->red.length = 5;
857 var->green.length = 6;
858 var->blue.length = 5;
859 break;
860 case 32:
861 var->red.offset = 16;
862 var->green.offset = 8;
863 var->blue.offset = 0;
864 var->red.length = 8;
865 var->green.length = 8;
866 var->blue.length = 8;
867 break;
868 default:
869 return -EINVAL;
1da177e4
LT		 870 }
871 debug("exit\n");
872
873 return 0;
874
875}
245a2c2c 876
1da177e4
LT		 877/* Pan the display */
878static int tridentfb_pan_display(struct fb_var_screeninfo *var,
245a2c2c 879 struct fb_info *info)
1da177e4 880{
306fa6f6 881 struct tridentfb_par *par = info->par;
1da177e4
LT		 882 unsigned int offset;
883
884 debug("enter\n");
885 offset = (var->xoffset + (var->yoffset * var->xres))
245a2c2c 886 * var->bits_per_pixel / 32;
1da177e4
LT		 887 info->var.xoffset = var->xoffset;
888 info->var.yoffset = var->yoffset;
306fa6f6 889 set_screen_start(par, offset);
1da177e4
LT		 890 debug("exit\n");
891 return 0;
892}
893
306fa6f6
KH		 894static void shadowmode_on(struct tridentfb_par *par)
895{
896 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
897}
898
899static void shadowmode_off(struct tridentfb_par *par)
900{
901 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
902}
1da177e4
LT		 903
904/* Set the hardware to the requested video mode */
905static int tridentfb_set_par(struct fb_info *info)
906{
245a2c2c
KH		 907 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
908 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
909 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
910 struct fb_var_screeninfo *var = &info->var;
1da177e4
LT		 911 int bpp = var->bits_per_pixel;
912 unsigned char tmp;
3f275ea3
KH		 913 unsigned long vclk;
914
1da177e4 915 debug("enter\n");
245a2c2c 916 hdispend = var->xres / 8 - 1;
7f762d23
KH		 917 hsyncstart = (var->xres + var->right_margin) / 8 - 1;
918 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8 - 1;
919 htotal = (var->xres + var->left_margin + var->right_margin +
920 var->hsync_len) / 8 - 5;
0e73a47f 921 hblankstart = hdispend + 1;
7f762d23 922 hblankend = htotal + 3;
1da177e4 923
1da177e4
LT		 924 vdispend = var->yres - 1;
925 vsyncstart = var->yres + var->lower_margin;
7f762d23
KH		 926 vsyncend = vsyncstart + var->vsync_len;
927 vtotal = var->upper_margin + vsyncend - 2;
0e73a47f 928 vblankstart = vdispend + 1;
7f762d23 929 vblankend = vtotal;
1da177e4 930
306fa6f6
KH		 931 crtc_unlock(par);
932 write3CE(par, CyberControl, 8);
1da177e4 933
6eed8e1e 934 if (par->flatpanel && var->xres < nativex) {
1da177e4
LT		 935 /*
936 * on flat panels with native size larger
937 * than requested resolution decide whether
938 * we stretch or center
939 */
10172ed6 940 t_outb(par, 0xEB, VGA_MIS_W);
1da177e4 941
306fa6f6 942 shadowmode_on(par);
1da177e4 943
245a2c2c 944 if (center)
306fa6f6 945 screen_center(par);
1da177e4 946 else if (stretch)
306fa6f6 947 screen_stretch(par);
1da177e4
LT		 948
949 } else {
10172ed6 950 t_outb(par, 0x2B, VGA_MIS_W);
306fa6f6 951 write3CE(par, CyberControl, 8);
1da177e4
LT		 952 }
953
954 /* vertical timing values */
10172ed6
KH		 955 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
956 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
957 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
958 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
959 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
7f762d23 960 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1da177e4
LT		 961
962 /* horizontal timing values */
10172ed6
KH		 963 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
964 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
965 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
966 write3X4(par, VGA_CRTC_H_SYNC_END,
306fa6f6 967 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
10172ed6 968 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
7f762d23 969 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1da177e4
LT		 970
971 /* higher bits of vertical timing values */
972 tmp = 0x10;
973 if (vtotal & 0x100) tmp |= 0x01;
974 if (vdispend & 0x100) tmp |= 0x02;
975 if (vsyncstart & 0x100) tmp |= 0x04;
976 if (vblankstart & 0x100) tmp |= 0x08;
977
978 if (vtotal & 0x200) tmp |= 0x20;
979 if (vdispend & 0x200) tmp |= 0x40;
980 if (vsyncstart & 0x200) tmp |= 0x80;
10172ed6 981 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1da177e4 982
7f762d23
KH		 983 tmp = read3X4(par, CRTHiOrd) & 0x07;
984 tmp |= 0x08; /* line compare bit 10 */
1da177e4
LT		 985 if (vtotal & 0x400) tmp |= 0x80;
986 if (vblankstart & 0x400) tmp |= 0x40;
987 if (vsyncstart & 0x400) tmp |= 0x20;
988 if (vdispend & 0x400) tmp |= 0x10;
306fa6f6 989 write3X4(par, CRTHiOrd, tmp);
1da177e4 990
7f762d23
KH		 991 tmp = (htotal >> 8) & 0x01;
992 tmp |= (hdispend >> 7) & 0x02;
993 tmp |= (hsyncstart >> 5) & 0x08;
994 tmp |= (hblankstart >> 4) & 0x10;
306fa6f6 995 write3X4(par, HorizOverflow, tmp);
245a2c2c 996
1da177e4
LT		 997 tmp = 0x40;
998 if (vblankstart & 0x200) tmp |= 0x20;
245a2c2c 999//FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
10172ed6 1000 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1da177e4 1001
10172ed6
KH		 1002 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1003 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1004 write3X4(par, VGA_CRTC_MODE, 0xC3);
1da177e4 1005
306fa6f6 1006 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1da177e4 1007
245a2c2c 1008 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
306fa6f6
KH		 1009 /* enable access extended memory */
1010 write3X4(par, CRTCModuleTest, tmp);
1da177e4 1011
306fa6f6
KH		 1012 /* enable GE for text acceleration */
1013 write3X4(par, GraphEngReg, 0x80);
1da177e4 1014
245a2c2c 1015#ifdef CONFIG_FB_TRIDENT_ACCEL
d9cad04b 1016 par->init_accel(par, info->var.xres, bpp);
8dad46cf 1017#endif
245a2c2c 1018
1da177e4 1019 switch (bpp) {
245a2c2c
KH		 1020 case 8:
1021 tmp = 0x00;
1022 break;
1023 case 16:
1024 tmp = 0x05;
1025 break;
1026 case 24:
1027 tmp = 0x29;
1028 break;
1029 case 32:
1030 tmp = 0x09;
1031 break;
1da177e4
LT		 1032 }
1033
306fa6f6 1034 write3X4(par, PixelBusReg, tmp);
1da177e4 1035
0e73a47f
KH		 1036 tmp = read3X4(par, DRAMControl);
1037 if (!is_oldprotect(par->chip_id))
1038 tmp |= 0x10;
122e8ad3 1039 if (iscyber(par->chip_id))
245a2c2c 1040 tmp |= 0x20;
306fa6f6 1041 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1da177e4 1042
306fa6f6 1043 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
0e73a47f
KH		 1044 if (!is_xp(par->chip_id))
1045 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
306fa6f6 1046 /* MMIO & PCI read and write burst enable */
a0d92256
KH		 1047 if (par->chip_id != TGUI9440)
1048 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1da177e4 1049
3f275ea3
KH		 1050 /* convert from picoseconds to kHz */
1051 vclk = PICOS2KHZ(info->var.pixclock);
1da177e4 1052 if (bpp == 32)
3f275ea3 1053 vclk *= 2;
306fa6f6 1054 set_vclk(par, vclk);
1da177e4 1055
10172ed6
KH		 1056 vga_mm_wseq(par->io_virt, 0, 3);
1057 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
306fa6f6 1058 /* enable 4 maps because needed in chain4 mode */
10172ed6
KH		 1059 vga_mm_wseq(par->io_virt, 2, 0x0F);
1060 vga_mm_wseq(par->io_virt, 3, 0);
1061 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1da177e4 1062
306fa6f6
KH		 1063 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1064 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
1065 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1066 write3CE(par, 0x6, 0x05); /* graphics mode */
1067 write3CE(par, 0x7, 0x0F); /* planes? */
1da177e4 1068
122e8ad3 1069 if (par->chip_id == CYBERBLADEXPAi1) {
1da177e4 1070 /* This fixes snow-effect in 32 bpp */
10172ed6 1071 write3X4(par, VGA_CRTC_H_SYNC_START, 0x84);
1da177e4
LT		 1072 }
1073
306fa6f6
KH		 1074 /* graphics mode and support 256 color modes */
1075 writeAttr(par, 0x10, 0x41);
1076 writeAttr(par, 0x12, 0x0F); /* planes */
1077 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1da177e4 1078
245a2c2c
KH		 1079 /* colors */
1080 for (tmp = 0; tmp < 0x10; tmp++)
306fa6f6 1081 writeAttr(par, tmp, tmp);
10172ed6
KH		 1082 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1083 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1da177e4
LT		 1084
1085 switch (bpp) {
245a2c2c
KH		 1086 case 8:
1087 tmp = 0;
1088 break;
1089 case 15:
1090 tmp = 0x10;
1091 break;
1092 case 16:
1093 tmp = 0x30;
1094 break;
1095 case 24:
1096 case 32:
1097 tmp = 0xD0;
1098 break;
1da177e4
LT		 1099 }
1100
10172ed6
KH		 1101 t_inb(par, VGA_PEL_IW);
1102 t_inb(par, VGA_PEL_MSK);
1103 t_inb(par, VGA_PEL_MSK);
1104 t_inb(par, VGA_PEL_MSK);
1105 t_inb(par, VGA_PEL_MSK);
1106 t_outb(par, tmp, VGA_PEL_MSK);
1107 t_inb(par, VGA_PEL_IW);
1da177e4 1108
6eed8e1e 1109 if (par->flatpanel)
306fa6f6
KH		 1110 set_number_of_lines(par, info->var.yres);
1111 set_lwidth(par, info->var.xres * bpp / (4 * 16));
1da177e4 1112 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
245a2c2c
KH		 1113 info->fix.line_length = info->var.xres * (bpp >> 3);
1114 info->cmap.len = (bpp == 8) ? 256 : 16;
1da177e4
LT		 1115 debug("exit\n");
1116 return 0;
1117}
1118
1119/* Set one color register */
1120static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
245a2c2c
KH		 1121 unsigned blue, unsigned transp,
1122 struct fb_info *info)
1da177e4
LT		 1123{
1124 int bpp = info->var.bits_per_pixel;
306fa6f6 1125 struct tridentfb_par *par = info->par;
1da177e4
LT		 1126
1127 if (regno >= info->cmap.len)
1128 return 1;
1129
973d9ab2 1130 if (bpp == 8) {
10172ed6
KH		 1131 t_outb(par, 0xFF, VGA_PEL_MSK);
1132 t_outb(par, regno, VGA_PEL_IW);
1da177e4 1133
10172ed6
KH		 1134 t_outb(par, red >> 10, VGA_PEL_D);
1135 t_outb(par, green >> 10, VGA_PEL_D);
1136 t_outb(par, blue >> 10, VGA_PEL_D);
1da177e4 1137
973d9ab2
AD		 1138 } else if (regno < 16) {
1139 if (bpp == 16) { /* RGB 565 */
1140 u32 col;
1141
1142 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1143 ((blue & 0xF800) >> 11);
1144 col |= col << 16;
1145 ((u32 *)(info->pseudo_palette))[regno] = col;
1146 } else if (bpp == 32) /* ARGB 8888 */
1147 ((u32*)info->pseudo_palette)[regno] =
245a2c2c
KH		 1148 ((transp & 0xFF00) << 16) |
1149 ((red & 0xFF00) << 8) |
973d9ab2 1150 ((green & 0xFF00)) |
245a2c2c 1151 ((blue & 0xFF00) >> 8);
973d9ab2 1152 }
1da177e4 1153
245a2c2c 1154/* debug("exit\n"); */
1da177e4
LT		 1155 return 0;
1156}
1157
1158/* Try blanking the screen.For flat panels it does nothing */
1159static int tridentfb_blank(int blank_mode, struct fb_info *info)
1160{
245a2c2c 1161 unsigned char PMCont, DPMSCont;
306fa6f6 1162 struct tridentfb_par *par = info->par;
1da177e4
LT		 1163
1164 debug("enter\n");
6eed8e1e 1165 if (par->flatpanel)
1da177e4 1166 return 0;
306fa6f6
KH		 1167 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1168 PMCont = t_inb(par, 0x83C6) & 0xFC;
1169 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
245a2c2c 1170 switch (blank_mode) {
1da177e4
LT		 1171 case FB_BLANK_UNBLANK:
1172 /* Screen: On, HSync: On, VSync: On */
1173 case FB_BLANK_NORMAL:
1174 /* Screen: Off, HSync: On, VSync: On */
1175 PMCont |= 0x03;
1176 DPMSCont |= 0x00;
1177 break;
1178 case FB_BLANK_HSYNC_SUSPEND:
1179 /* Screen: Off, HSync: Off, VSync: On */
1180 PMCont |= 0x02;
1181 DPMSCont |= 0x01;
1182 break;
1183 case FB_BLANK_VSYNC_SUSPEND:
1184 /* Screen: Off, HSync: On, VSync: Off */
1185 PMCont |= 0x02;
1186 DPMSCont |= 0x02;
1187 break;
1188 case FB_BLANK_POWERDOWN:
1189 /* Screen: Off, HSync: Off, VSync: Off */
1190 PMCont |= 0x00;
1191 DPMSCont |= 0x03;
1192 break;
245a2c2c 1193 }
1da177e4 1194
306fa6f6
KH		 1195 write3CE(par, PowerStatus, DPMSCont);
1196 t_outb(par, 4, 0x83C8);
1197 t_outb(par, PMCont, 0x83C6);
1da177e4
LT		 1198
1199 debug("exit\n");
1200
1201 /* let fbcon do a softblank for us */
1202 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1203}
1204
245a2c2c
KH		 1205static struct fb_ops tridentfb_ops = {
1206 .owner = THIS_MODULE,
1207 .fb_setcolreg = tridentfb_setcolreg,
1208 .fb_pan_display = tridentfb_pan_display,
1209 .fb_blank = tridentfb_blank,
1210 .fb_check_var = tridentfb_check_var,
1211 .fb_set_par = tridentfb_set_par,
1212 .fb_fillrect = tridentfb_fillrect,
1213 .fb_copyarea = tridentfb_copyarea,
1214 .fb_imageblit = cfb_imageblit,
1215};
1216
e09ed099
KH		 1217static int __devinit trident_pci_probe(struct pci_dev *dev,
1218 const struct pci_device_id *id)
1da177e4
LT		 1219{
1220 int err;
1221 unsigned char revision;
e09ed099
KH		 1222 struct fb_info *info;
1223 struct tridentfb_par *default_par;
122e8ad3
KH		 1224 int defaultaccel;
1225 int chip3D;
1226 int chip_id;
1da177e4
LT		 1227
1228 err = pci_enable_device(dev);
1229 if (err)
1230 return err;
1231
e09ed099
KH		 1232 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1233 if (!info)
1234 return -ENOMEM;
1235 default_par = info->par;
1236
1da177e4
LT		 1237 chip_id = id->device;
1238
245a2c2c 1239 if (chip_id == CYBERBLADEi1)
9fa68eae
KP		 1240 output("*** Please do use cyblafb, Cyberblade/i1 support "
1241 "will soon be removed from tridentfb!\n");
1242
1243
1da177e4 1244 /* If PCI id is 0x9660 then further detect chip type */
245a2c2c 1245
1da177e4 1246 if (chip_id == TGUI9660) {
10172ed6 1247 revision = vga_io_rseq(RevisionID);
245a2c2c 1248
1da177e4 1249 switch (revision) {
0e73a47f
KH		 1250 case 0x21:
1251 chip_id = PROVIDIA9685;
1252 break;
245a2c2c
KH		 1253 case 0x22:
1254 case 0x23:
1255 chip_id = CYBER9397;
1256 break;
1257 case 0x2A:
1258 chip_id = CYBER9397DVD;
1259 break;
1260 case 0x30:
1261 case 0x33:
1262 case 0x34:
1263 case 0x35:
1264 case 0x38:
1265 case 0x3A:
1266 case 0xB3:
1267 chip_id = CYBER9385;
1268 break;
1269 case 0x40 ... 0x43:
1270 chip_id = CYBER9382;
1271 break;
1272 case 0x4A:
1273 chip_id = CYBER9388;
1274 break;
1275 default:
1276 break;
1da177e4
LT		 1277 }
1278 }
1279
1280 chip3D = is3Dchip(chip_id);
1da177e4
LT		 1281
1282 if (is_xp(chip_id)) {
d9cad04b
KH		 1283 default_par->init_accel = xp_init_accel;
1284 default_par->wait_engine = xp_wait_engine;
1285 default_par->fill_rect = xp_fill_rect;
1286 default_par->copy_rect = xp_copy_rect;
245a2c2c 1287 } else if (is_blade(chip_id)) {
d9cad04b
KH		 1288 default_par->init_accel = blade_init_accel;
1289 default_par->wait_engine = blade_wait_engine;
1290 default_par->fill_rect = blade_fill_rect;
1291 default_par->copy_rect = blade_copy_rect;
1da177e4 1292 } else {
d9cad04b
KH		 1293 default_par->init_accel = image_init_accel;
1294 default_par->wait_engine = image_wait_engine;
1295 default_par->fill_rect = image_fill_rect;
1296 default_par->copy_rect = image_copy_rect;
1da177e4
LT		 1297 }
1298
122e8ad3
KH		 1299 default_par->chip_id = chip_id;
1300
1da177e4
LT		 1301 /* acceleration is on by default for 3D chips */
1302 defaultaccel = chip3D && !noaccel;
1303
1da177e4 1304 /* setup MMIO region */
245a2c2c
KH		 1305 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1306 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1da177e4
LT		 1307
1308 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1309 debug("request_region failed!\n");
3876ae8b 1310 framebuffer_release(info);
1da177e4
LT		 1311 return -1;
1312 }
1313
e09ed099
KH		 1314 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1315 tridentfb_fix.mmio_len);
1da177e4 1316
e09ed099 1317 if (!default_par->io_virt) {
1da177e4 1318 debug("ioremap failed\n");
e8ed857c
KH		 1319 err = -1;
1320 goto out_unmap1;
1da177e4
LT		 1321 }
1322
1da177e4 1323 /* setup framebuffer memory */
245a2c2c 1324 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
e09ed099 1325 tridentfb_fix.smem_len = get_memsize(default_par);
245a2c2c 1326
1da177e4
LT		 1327 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1328 debug("request_mem_region failed!\n");
e09ed099 1329 disable_mmio(info->par);
a02f6402 1330 err = -1;
e8ed857c 1331 goto out_unmap1;
1da177e4
LT		 1332 }
1333
3876ae8b
KH		 1334 enable_mmio();
1335
e09ed099
KH		 1336 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1337 tridentfb_fix.smem_len);
1da177e4 1338
e09ed099 1339 if (!info->screen_base) {
1da177e4 1340 debug("ioremap failed\n");
a02f6402 1341 err = -1;
e8ed857c 1342 goto out_unmap2;
1da177e4
LT		 1343 }
1344
1345 output("%s board found\n", pci_name(dev));
6eed8e1e 1346 default_par->flatpanel = is_flatpanel(default_par);
1da177e4 1347
6eed8e1e 1348 if (default_par->flatpanel)
e09ed099 1349 nativex = get_nativex(default_par);
1da177e4 1350
e09ed099
KH		 1351 info->fix = tridentfb_fix;
1352 info->fbops = &tridentfb_ops;
1da177e4
LT		 1353
1354
e09ed099 1355 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1da177e4 1356#ifdef CONFIG_FB_TRIDENT_ACCEL
e09ed099 1357 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1da177e4 1358#endif
ea8ee55c 1359 if (!fb_find_mode(&info->var, info,
07f41e45 1360 mode_option, NULL, 0, NULL, bpp)) {
a02f6402 1361 err = -EINVAL;
e8ed857c 1362 goto out_unmap2;
a02f6402 1363 }
e09ed099 1364 err = fb_alloc_cmap(&info->cmap, 256, 0);
e8ed857c
KH		 1365 if (err < 0)
1366 goto out_unmap2;
1367
d9cad04b 1368 if (defaultaccel && default_par->init_accel)
ea8ee55c 1369 info->var.accel_flags |= FB_ACCELF_TEXT;
1da177e4 1370 else
ea8ee55c
KH		 1371 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1372 info->var.activate |= FB_ACTIVATE_NOW;
e09ed099
KH		 1373 info->device = &dev->dev;
1374 if (register_framebuffer(info) < 0) {
1da177e4 1375 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
e09ed099 1376 fb_dealloc_cmap(&info->cmap);
a02f6402 1377 err = -EINVAL;
e8ed857c 1378 goto out_unmap2;
1da177e4
LT		 1379 }
1380 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
ea8ee55c
KH		 1381 info->node, info->fix.id, info->var.xres,
1382 info->var.yres, info->var.bits_per_pixel);
e09ed099
KH		 1383
1384 pci_set_drvdata(dev, info);
1da177e4 1385 return 0;
a02f6402 1386
e8ed857c 1387out_unmap2:
e09ed099
KH		 1388 if (info->screen_base)
1389 iounmap(info->screen_base);
e8ed857c 1390 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
e09ed099 1391 disable_mmio(info->par);
e8ed857c 1392out_unmap1:
e09ed099
KH		 1393 if (default_par->io_virt)
1394 iounmap(default_par->io_virt);
e8ed857c 1395 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
e09ed099 1396 framebuffer_release(info);
a02f6402 1397 return err;
1da177e4
LT		 1398}
1399
245a2c2c 1400static void __devexit trident_pci_remove(struct pci_dev *dev)
1da177e4 1401{
e09ed099
KH		 1402 struct fb_info *info = pci_get_drvdata(dev);
1403 struct tridentfb_par *par = info->par;
1404
1405 unregister_framebuffer(info);
1da177e4 1406 iounmap(par->io_virt);
e09ed099 1407 iounmap(info->screen_base);
1da177e4 1408 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
e8ed857c 1409 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
e09ed099
KH		 1410 pci_set_drvdata(dev, NULL);
1411 framebuffer_release(info);
1da177e4
LT		 1412}
1413
1414/* List of boards that we are trying to support */
1415static struct pci_device_id trident_devices[] = {
245a2c2c
KH		 1416 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1417 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1418 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1419 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1420 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1421 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1422 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1423 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
a0d92256 1424 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
245a2c2c
KH		 1425 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1426 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1427 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1428 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1429 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1430 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1431 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1432 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1433 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1434 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1435 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1436 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4 1437 {0,}
245a2c2c
KH		 1438};
1439
1440MODULE_DEVICE_TABLE(pci, trident_devices);
1da177e4
LT		 1441
1442static struct pci_driver tridentfb_pci_driver = {
245a2c2c
KH		 1443 .name = "tridentfb",
1444 .id_table = trident_devices,
1445 .probe = trident_pci_probe,
1446 .remove = __devexit_p(trident_pci_remove)
1da177e4
LT		 1447};
1448
1449/*
1450 * Parse user specified options (`video=trident:')
1451 * example:
245a2c2c 1452 * video=trident:800x600,bpp=16,noaccel
1da177e4
LT		 1453 */
1454#ifndef MODULE
07f41e45 1455static int __init tridentfb_setup(char *options)
1da177e4 1456{
245a2c2c 1457 char *opt;
1da177e4
LT		 1458 if (!options || !*options)
1459 return 0;
245a2c2c
KH		 1460 while ((opt = strsep(&options, ",")) != NULL) {
1461 if (!*opt)
1462 continue;
1463 if (!strncmp(opt, "noaccel", 7))
1da177e4 1464 noaccel = 1;
245a2c2c 1465 else if (!strncmp(opt, "fp", 2))
6eed8e1e 1466 fp = 1;
245a2c2c 1467 else if (!strncmp(opt, "crt", 3))
6eed8e1e 1468 fp = 0;
245a2c2c
KH		 1469 else if (!strncmp(opt, "bpp=", 4))
1470 bpp = simple_strtoul(opt + 4, NULL, 0);
1471 else if (!strncmp(opt, "center", 6))
1da177e4 1472 center = 1;
245a2c2c 1473 else if (!strncmp(opt, "stretch", 7))
1da177e4 1474 stretch = 1;
245a2c2c
KH		 1475 else if (!strncmp(opt, "memsize=", 8))
1476 memsize = simple_strtoul(opt + 8, NULL, 0);
1477 else if (!strncmp(opt, "memdiff=", 8))
1478 memdiff = simple_strtoul(opt + 8, NULL, 0);
1479 else if (!strncmp(opt, "nativex=", 8))
1480 nativex = simple_strtoul(opt + 8, NULL, 0);
1da177e4 1481 else
07f41e45 1482 mode_option = opt;
1da177e4
LT		 1483 }
1484 return 0;
1485}
1486#endif
1487
1488static int __init tridentfb_init(void)
1489{
1490#ifndef MODULE
1491 char *option = NULL;
1492
1493 if (fb_get_options("tridentfb", &option))
1494 return -ENODEV;
1495 tridentfb_setup(option);
1496#endif
1497 output("Trident framebuffer %s initializing\n", VERSION);
1498 return pci_register_driver(&tridentfb_pci_driver);
1499}
1500
1501static void __exit tridentfb_exit(void)
1502{
1503 pci_unregister_driver(&tridentfb_pci_driver);
1504}
1505
1da177e4
LT		 1506module_init(tridentfb_init);
1507module_exit(tridentfb_exit);
1508
1509MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1510MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1511MODULE_LICENSE("GPL");
1512
Linux 6.x block layer and io_uring tree(s)