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cpuset: update top cpuset's mems after adding a node
[linux-2.6-block.git] / drivers / video / tridentfb.c
CommitLineData
1da177e4 1/*
49b1f4b4 2 * Frame buffer driver for Trident TGUI, Blade and Image series
1da177e4 3 *
245a2c2c 4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
1da177e4
LT		 5 *
6 *
7 * CREDITS:(in order of appearance)
245a2c2c
KH		 8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
1da177e4 14 * TODO:
245a2c2c 15 * timing value tweaking so it looks good on every monitor in every mode
1da177e4
LT		 16 */
17
1da177e4
LT		 18#include <linux/module.h>
19#include <linux/fb.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22
23#include <linux/delay.h>
10172ed6 24#include <video/vga.h>
1da177e4
LT		 25#include <video/trident.h>
26
1da177e4 27struct tridentfb_par {
245a2c2c 28 void __iomem *io_virt; /* iospace virtual memory address */
ea8ee55c 29 u32 pseudo_pal[16];
122e8ad3 30 int chip_id;
6eed8e1e 31 int flatpanel;
d9cad04b
KH		 32 void (*init_accel) (struct tridentfb_par *, int, int);
33 void (*wait_engine) (struct tridentfb_par *);
34 void (*fill_rect)
35 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
36 void (*copy_rect)
37 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
0292be4a
KH		 38 void (*image_blit)
39 (struct tridentfb_par *par, const char*,
40 u32, u32, u32, u32, u32, u32);
5cf13845 41 unsigned char eng_oper; /* engine operation... */
1da177e4
LT		 42};
43
1da177e4 44static struct fb_fix_screeninfo tridentfb_fix = {
245a2c2c 45 .id = "Trident",
1da177e4
LT		 46 .type = FB_TYPE_PACKED_PIXELS,
47 .ypanstep = 1,
48 .visual = FB_VISUAL_PSEUDOCOLOR,
49 .accel = FB_ACCEL_NONE,
50};
51
1da177e4
LT		 52/* defaults which are normally overriden by user values */
53
54/* video mode */
5cf13845 55static char *mode_option __devinitdata = "640x480-8@60";
6eed8e1e 56static int bpp __devinitdata = 8;
1da177e4 57
6eed8e1e 58static int noaccel __devinitdata;
1da177e4
LT		 59
60static int center;
61static int stretch;
62
6eed8e1e
KH		 63static int fp __devinitdata;
64static int crt __devinitdata;
1da177e4 65
6eed8e1e
KH		 66static int memsize __devinitdata;
67static int memdiff __devinitdata;
1da177e4
LT		 68static int nativex;
69
07f41e45
KH		 70module_param(mode_option, charp, 0);
71MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
9e3f0ca8
KH		 72module_param_named(mode, mode_option, charp, 0);
73MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
1da177e4
LT		 74module_param(bpp, int, 0);
75module_param(center, int, 0);
76module_param(stretch, int, 0);
77module_param(noaccel, int, 0);
78module_param(memsize, int, 0);
79module_param(memdiff, int, 0);
80module_param(nativex, int, 0);
81module_param(fp, int, 0);
6eed8e1e 82MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
1da177e4 83module_param(crt, int, 0);
6eed8e1e 84MODULE_PARM_DESC(crt, "Define if CRT is connected");
1da177e4 85
5cf13845 86static inline int is_oldclock(int id)
6bdf1035 87{
a0d92256
KH		 88 return (id == TGUI9440) ||
89 (id == TGUI9660) ||
0e73a47f
KH		 90 (id == CYBER9320);
91}
92
5cf13845 93static inline int is_oldprotect(int id)
0e73a47f 94{
5cf13845 95 return is_oldclock(id) ||
0e73a47f 96 (id == PROVIDIA9685) ||
0e73a47f
KH		 97 (id == CYBER9382) ||
98 (id == CYBER9385);
6bdf1035
KH		 99}
100
5cf13845 101static inline int is_blade(int id)
e0759a5f
KH		 102{
103 return (id == BLADE3D) ||
104 (id == CYBERBLADEE4) ||
105 (id == CYBERBLADEi7) ||
106 (id == CYBERBLADEi7D) ||
107 (id == CYBERBLADEi1) ||
108 (id == CYBERBLADEi1D) ||
109 (id == CYBERBLADEAi1) ||
110 (id == CYBERBLADEAi1D);
111}
112
5cf13845 113static inline int is_xp(int id)
e0759a5f
KH		 114{
115 return (id == CYBERBLADEXPAi1) ||
116 (id == CYBERBLADEXPm8) ||
117 (id == CYBERBLADEXPm16);
118}
119
5cf13845 120static inline int is3Dchip(int id)
1da177e4 121{
5cf13845 122 return is_blade(id) || is_xp(id) ||
245a2c2c
KH		 123 (id == CYBER9397) || (id == CYBER9397DVD) ||
124 (id == CYBER9520) || (id == CYBER9525DVD) ||
5cf13845 125 (id == IMAGE975) || (id == IMAGE985);
1da177e4
LT		 126}
127
5cf13845 128static inline int iscyber(int id)
1da177e4
LT		 129{
130 switch (id) {
245a2c2c
KH		 131 case CYBER9388:
132 case CYBER9382:
133 case CYBER9385:
134 case CYBER9397:
135 case CYBER9397DVD:
136 case CYBER9520:
137 case CYBER9525DVD:
138 case CYBERBLADEE4:
139 case CYBERBLADEi7D:
140 case CYBERBLADEi1:
141 case CYBERBLADEi1D:
142 case CYBERBLADEAi1:
143 case CYBERBLADEAi1D:
144 case CYBERBLADEXPAi1:
145 return 1;
1da177e4 146
245a2c2c 147 case CYBER9320:
245a2c2c 148 case CYBERBLADEi7: /* VIA MPV4 integrated version */
245a2c2c
KH		 149 default:
150 /* case CYBERBLDAEXPm8: Strange */
151 /* case CYBERBLDAEXPm16: Strange */
152 return 0;
1da177e4
LT		 153 }
154}
155
306fa6f6
KH		 156static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
157{
158 fb_writeb(val, p->io_virt + reg);
159}
1da177e4 160
306fa6f6
KH		 161static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
162{
163 return fb_readb(p->io_virt + reg);
164}
1da177e4 165
306fa6f6
KH		 166static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
167{
168 fb_writel(v, par->io_virt + r);
169}
170
171static inline u32 readmmr(struct tridentfb_par *par, u16 r)
172{
173 return fb_readl(par->io_virt + r);
174}
1da177e4 175
1da177e4
LT		 176/*
177 * Blade specific acceleration.
178 */
179
245a2c2c 180#define point(x, y) ((y) << 16 | (x))
1da177e4 181
306fa6f6 182static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
1da177e4 183{
245a2c2c 184 int v1 = (pitch >> 3) << 20;
49b1f4b4
KH		 185 int tmp = bpp == 24 ? 2 : (bpp >> 4);
186 int v2 = v1 | (tmp << 29);
187
306fa6f6
KH		 188 writemmr(par, 0x21C0, v2);
189 writemmr(par, 0x21C4, v2);
190 writemmr(par, 0x21B8, v2);
191 writemmr(par, 0x21BC, v2);
192 writemmr(par, 0x21D0, v1);
193 writemmr(par, 0x21D4, v1);
194 writemmr(par, 0x21C8, v1);
195 writemmr(par, 0x21CC, v1);
196 writemmr(par, 0x216C, 0);
1da177e4
LT		 197}
198
306fa6f6 199static void blade_wait_engine(struct tridentfb_par *par)
1da177e4 200{
49b1f4b4
KH		 201 while (readmmr(par, STATUS) & 0xFA800000)
202 cpu_relax();
1da177e4
LT		 203}
204
306fa6f6
KH		 205static void blade_fill_rect(struct tridentfb_par *par,
206 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
1da177e4 207{
49b1f4b4
KH		 208 writemmr(par, COLOR, c);
209 writemmr(par, ROP, rop ? ROP_X : ROP_S);
306fa6f6 210 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
1da177e4 211
49b1f4b4
KH		 212 writemmr(par, DST1, point(x, y));
213 writemmr(par, DST2, point(x + w - 1, y + h - 1));
1da177e4
LT		 214}
215
0292be4a
KH		 216static void blade_image_blit(struct tridentfb_par *par, const char *data,
217 u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
218{
219 unsigned size = ((w + 31) >> 5) * h;
220
221 writemmr(par, COLOR, c);
222 writemmr(par, BGCOLOR, b);
223 writemmr(par, CMD, 0xa0000000 | 3 << 19);
224
225 writemmr(par, DST1, point(x, y));
226 writemmr(par, DST2, point(x + w - 1, y + h - 1));
227
228 memcpy(par->io_virt + 0x10000, data, 4 * size);
229}
230
306fa6f6
KH		 231static void blade_copy_rect(struct tridentfb_par *par,
232 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
1da177e4 233{
1da177e4 234 int direction = 2;
49b1f4b4
KH		 235 u32 s1 = point(x1, y1);
236 u32 s2 = point(x1 + w - 1, y1 + h - 1);
237 u32 d1 = point(x2, y2);
238 u32 d2 = point(x2 + w - 1, y2 + h - 1);
1da177e4
LT		 239
240 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
245a2c2c 241 direction = 0;
1da177e4 242
306fa6f6
KH		 243 writemmr(par, ROP, ROP_S);
244 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
1da177e4 245
49b1f4b4
KH		 246 writemmr(par, SRC1, direction ? s2 : s1);
247 writemmr(par, SRC2, direction ? s1 : s2);
248 writemmr(par, DST1, direction ? d2 : d1);
249 writemmr(par, DST2, direction ? d1 : d2);
1da177e4
LT		 250}
251
1da177e4
LT		 252/*
253 * BladeXP specific acceleration functions
254 */
255
306fa6f6 256static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
1da177e4 257{
49b1f4b4
KH		 258 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
259 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
1da177e4
LT		 260
261 switch (pitch << (bpp >> 3)) {
245a2c2c
KH		 262 case 8192:
263 case 512:
264 x |= 0x00;
265 break;
266 case 1024:
267 x |= 0x04;
268 break;
269 case 2048:
270 x |= 0x08;
271 break;
272 case 4096:
273 x |= 0x0C;
274 break;
1da177e4
LT		 275 }
276
306fa6f6 277 t_outb(par, x, 0x2125);
1da177e4 278
5cf13845 279 par->eng_oper = x | 0x40;
1da177e4 280
306fa6f6
KH		 281 writemmr(par, 0x2154, v1);
282 writemmr(par, 0x2150, v1);
283 t_outb(par, 3, 0x2126);
1da177e4
LT		 284}
285
306fa6f6 286static void xp_wait_engine(struct tridentfb_par *par)
1da177e4 287{
5cf13845
KH		 288 int count = 0;
289 int timeout = 0;
1da177e4 290
49b1f4b4 291 while (t_inb(par, STATUS) & 0x80) {
1da177e4
LT		 292 count++;
293 if (count == 10000000) {
294 /* Timeout */
295 count = 9990000;
296 timeout++;
297 if (timeout == 8) {
298 /* Reset engine */
49b1f4b4 299 t_outb(par, 0x00, STATUS);
1da177e4
LT		 300 return;
301 }
302 }
49b1f4b4 303 cpu_relax();
1da177e4
LT		 304 }
305}
306
306fa6f6
KH		 307static void xp_fill_rect(struct tridentfb_par *par,
308 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
1da177e4 309{
306fa6f6
KH		 310 writemmr(par, 0x2127, ROP_P);
311 writemmr(par, 0x2158, c);
49b1f4b4
KH		 312 writemmr(par, DRAWFL, 0x4000);
313 writemmr(par, OLDDIM, point(h, w));
314 writemmr(par, OLDDST, point(y, x));
315 t_outb(par, 0x01, OLDCMD);
5cf13845 316 t_outb(par, par->eng_oper, 0x2125);
1da177e4
LT		 317}
318
306fa6f6
KH		 319static void xp_copy_rect(struct tridentfb_par *par,
320 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
1da177e4 321{
245a2c2c 322 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
5cf13845 323 int direction = 0x0004;
245a2c2c 324
1da177e4
LT		 325 if ((x1 < x2) && (y1 == y2)) {
326 direction |= 0x0200;
327 x1_tmp = x1 + w - 1;
328 x2_tmp = x2 + w - 1;
329 } else {
330 x1_tmp = x1;
331 x2_tmp = x2;
332 }
245a2c2c 333
1da177e4
LT		 334 if (y1 < y2) {
335 direction |= 0x0100;
336 y1_tmp = y1 + h - 1;
337 y2_tmp = y2 + h - 1;
245a2c2c 338 } else {
1da177e4
LT		 339 y1_tmp = y1;
340 y2_tmp = y2;
341 }
342
49b1f4b4 343 writemmr(par, DRAWFL, direction);
306fa6f6 344 t_outb(par, ROP_S, 0x2127);
49b1f4b4
KH		 345 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
346 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
347 writemmr(par, OLDDIM, point(h, w));
348 t_outb(par, 0x01, OLDCMD);
1da177e4
LT		 349}
350
1da177e4
LT		 351/*
352 * Image specific acceleration functions
353 */
306fa6f6 354static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
1da177e4 355{
49b1f4b4
KH		 356 int tmp = bpp == 24 ? 2: (bpp >> 4);
357
306fa6f6
KH		 358 writemmr(par, 0x2120, 0xF0000000);
359 writemmr(par, 0x2120, 0x40000000 | tmp);
360 writemmr(par, 0x2120, 0x80000000);
361 writemmr(par, 0x2144, 0x00000000);
362 writemmr(par, 0x2148, 0x00000000);
363 writemmr(par, 0x2150, 0x00000000);
364 writemmr(par, 0x2154, 0x00000000);
365 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
366 writemmr(par, 0x216C, 0x00000000);
367 writemmr(par, 0x2170, 0x00000000);
368 writemmr(par, 0x217C, 0x00000000);
369 writemmr(par, 0x2120, 0x10000000);
370 writemmr(par, 0x2130, (2047 << 16) | 2047);
1da177e4
LT		 371}
372
306fa6f6 373static void image_wait_engine(struct tridentfb_par *par)
1da177e4 374{
49b1f4b4
KH		 375 while (readmmr(par, 0x2164) & 0xF0000000)
376 cpu_relax();
1da177e4
LT		 377}
378
306fa6f6
KH		 379static void image_fill_rect(struct tridentfb_par *par,
380 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
1da177e4 381{
306fa6f6
KH		 382 writemmr(par, 0x2120, 0x80000000);
383 writemmr(par, 0x2120, 0x90000000 | ROP_S);
1da177e4 384
306fa6f6 385 writemmr(par, 0x2144, c);
1da177e4 386
49b1f4b4
KH		 387 writemmr(par, DST1, point(x, y));
388 writemmr(par, DST2, point(x + w - 1, y + h - 1));
1da177e4 389
306fa6f6 390 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
1da177e4
LT		 391}
392
306fa6f6
KH		 393static void image_copy_rect(struct tridentfb_par *par,
394 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
1da177e4 395{
2c86a0c2 396 int direction = 0x4;
49b1f4b4
KH		 397 u32 s1 = point(x1, y1);
398 u32 s2 = point(x1 + w - 1, y1 + h - 1);
399 u32 d1 = point(x2, y2);
400 u32 d2 = point(x2 + w - 1, y2 + h - 1);
1da177e4 401
245a2c2c
KH		 402 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
403 direction = 0;
404
306fa6f6
KH		 405 writemmr(par, 0x2120, 0x80000000);
406 writemmr(par, 0x2120, 0x90000000 | ROP_S);
245a2c2c 407
49b1f4b4
KH		 408 writemmr(par, SRC1, direction ? s2 : s1);
409 writemmr(par, SRC2, direction ? s1 : s2);
410 writemmr(par, DST1, direction ? d2 : d1);
411 writemmr(par, DST2, direction ? d1 : d2);
306fa6f6
KH		 412 writemmr(par, 0x2124,
413 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
245a2c2c 414}
1da177e4 415
bcac2d5f
KH		 416/*
417 * TGUI 9440/96XX acceleration
418 */
419
420static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
421{
49b1f4b4 422 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
bcac2d5f
KH		 423
424 /* disable clipping */
425 writemmr(par, 0x2148, 0);
426 writemmr(par, 0x214C, point(4095, 2047));
427
bcac2d5f
KH		 428 switch ((pitch * bpp) / 8) {
429 case 8192:
430 case 512:
431 x |= 0x00;
432 break;
433 case 1024:
434 x |= 0x04;
435 break;
436 case 2048:
437 x |= 0x08;
438 break;
439 case 4096:
440 x |= 0x0C;
441 break;
442 }
443
444 fb_writew(x, par->io_virt + 0x2122);
445}
446
447static void tgui_fill_rect(struct tridentfb_par *par,
448 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
449{
450 t_outb(par, ROP_P, 0x2127);
49b1f4b4
KH		 451 writemmr(par, OLDCLR, c);
452 writemmr(par, DRAWFL, 0x4020);
453 writemmr(par, OLDDIM, point(w - 1, h - 1));
454 writemmr(par, OLDDST, point(x, y));
455 t_outb(par, 1, OLDCMD);
bcac2d5f
KH		 456}
457
458static void tgui_copy_rect(struct tridentfb_par *par,
459 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
460{
461 int flags = 0;
462 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
463
464 if ((x1 < x2) && (y1 == y2)) {
465 flags |= 0x0200;
466 x1_tmp = x1 + w - 1;
467 x2_tmp = x2 + w - 1;
468 } else {
469 x1_tmp = x1;
470 x2_tmp = x2;
471 }
472
473 if (y1 < y2) {
474 flags |= 0x0100;
475 y1_tmp = y1 + h - 1;
476 y2_tmp = y2 + h - 1;
477 } else {
478 y1_tmp = y1;
479 y2_tmp = y2;
480 }
481
49b1f4b4 482 writemmr(par, DRAWFL, 0x4 | flags);
bcac2d5f 483 t_outb(par, ROP_S, 0x2127);
49b1f4b4
KH		 484 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
485 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
486 writemmr(par, OLDDIM, point(w - 1, h - 1));
487 t_outb(par, 1, OLDCMD);
bcac2d5f
KH		 488}
489
1da177e4
LT		 490/*
491 * Accel functions called by the upper layers
492 */
493#ifdef CONFIG_FB_TRIDENT_ACCEL
245a2c2c
KH		 494static void tridentfb_fillrect(struct fb_info *info,
495 const struct fb_fillrect *fr)
1da177e4 496{
306fa6f6 497 struct tridentfb_par *par = info->par;
49b1f4b4 498 int col;
245a2c2c 499
01a2d9ed
KH		 500 if (info->flags & FBINFO_HWACCEL_DISABLED) {
501 cfb_fillrect(info, fr);
502 return;
503 }
49b1f4b4
KH		 504 if (info->var.bits_per_pixel == 8) {
505 col = fr->color;
245a2c2c
KH		 506 col |= col << 8;
507 col |= col << 16;
49b1f4b4 508 } else
245a2c2c 509 col = ((u32 *)(info->pseudo_palette))[fr->color];
245a2c2c 510
49b1f4b4 511 par->wait_engine(par);
d9cad04b 512 par->fill_rect(par, fr->dx, fr->dy, fr->width,
306fa6f6 513 fr->height, col, fr->rop);
1da177e4 514}
49b1f4b4 515
0292be4a
KH		 516static void tridentfb_imageblit(struct fb_info *info,
517 const struct fb_image *img)
518{
519 struct tridentfb_par *par = info->par;
520 int col, bgcol;
521
522 if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
523 cfb_imageblit(info, img);
524 return;
525 }
526 if (info->var.bits_per_pixel == 8) {
527 col = img->fg_color;
528 col |= col << 8;
529 col |= col << 16;
530 bgcol = img->bg_color;
531 bgcol |= bgcol << 8;
532 bgcol |= bgcol << 16;
533 } else {
534 col = ((u32 *)(info->pseudo_palette))[img->fg_color];
535 bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
536 }
537
538 par->wait_engine(par);
539 if (par->image_blit)
540 par->image_blit(par, img->data, img->dx, img->dy,
541 img->width, img->height, col, bgcol);
542 else
543 cfb_imageblit(info, img);
544}
545
245a2c2c
KH		 546static void tridentfb_copyarea(struct fb_info *info,
547 const struct fb_copyarea *ca)
1da177e4 548{
306fa6f6
KH		 549 struct tridentfb_par *par = info->par;
550
01a2d9ed
KH		 551 if (info->flags & FBINFO_HWACCEL_DISABLED) {
552 cfb_copyarea(info, ca);
553 return;
554 }
49b1f4b4 555 par->wait_engine(par);
d9cad04b 556 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
306fa6f6 557 ca->width, ca->height);
49b1f4b4
KH		 558}
559
560static int tridentfb_sync(struct fb_info *info)
561{
562 struct tridentfb_par *par = info->par;
563
01a2d9ed
KH		 564 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
565 par->wait_engine(par);
49b1f4b4 566 return 0;
1da177e4 567}
49b1f4b4
KH		 568#else
569#define tridentfb_fillrect cfb_fillrect
570#define tridentfb_copyarea cfb_copyarea
0292be4a 571#define tridentfb_imageblit cfb_imageblit
1da177e4
LT		 572#endif /* CONFIG_FB_TRIDENT_ACCEL */
573
1da177e4
LT		 574/*
575 * Hardware access functions
576 */
577
306fa6f6 578static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
1da177e4 579{
10172ed6 580 return vga_mm_rcrt(par->io_virt, reg);
1da177e4
LT		 581}
582
306fa6f6
KH		 583static inline void write3X4(struct tridentfb_par *par, int reg,
584 unsigned char val)
1da177e4 585{
10172ed6 586 vga_mm_wcrt(par->io_virt, reg, val);
1da177e4
LT		 587}
588
10172ed6
KH		 589static inline unsigned char read3CE(struct tridentfb_par *par,
590 unsigned char reg)
1da177e4 591{
10172ed6 592 return vga_mm_rgfx(par->io_virt, reg);
1da177e4
LT		 593}
594
306fa6f6
KH		 595static inline void writeAttr(struct tridentfb_par *par, int reg,
596 unsigned char val)
1da177e4 597{
10172ed6
KH		 598 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
599 vga_mm_wattr(par->io_virt, reg, val);
1da177e4
LT		 600}
601
306fa6f6
KH		 602static inline void write3CE(struct tridentfb_par *par, int reg,
603 unsigned char val)
1da177e4 604{
10172ed6 605 vga_mm_wgfx(par->io_virt, reg, val);
1da177e4
LT		 606}
607
13b0de49 608static void enable_mmio(struct tridentfb_par *par)
1da177e4
LT		 609{
610 /* Goto New Mode */
10172ed6 611 vga_io_rseq(0x0B);
1da177e4
LT		 612
613 /* Unprotect registers */
10172ed6 614 vga_io_wseq(NewMode1, 0x80);
13b0de49
KH		 615 if (!is_oldprotect(par->chip_id))
616 vga_io_wseq(Protection, 0x92);
245a2c2c 617
1da177e4 618 /* Enable MMIO */
245a2c2c 619 outb(PCIReg, 0x3D4);
1da177e4 620 outb(inb(0x3D5) | 0x01, 0x3D5);
e8ed857c
KH		 621}
622
306fa6f6 623static void disable_mmio(struct tridentfb_par *par)
e8ed857c 624{
e8ed857c 625 /* Goto New Mode */
10172ed6 626 vga_mm_rseq(par->io_virt, 0x0B);
e8ed857c
KH		 627
628 /* Unprotect registers */
10172ed6 629 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
13b0de49
KH		 630 if (!is_oldprotect(par->chip_id))
631 vga_mm_wseq(par->io_virt, Protection, 0x92);
e8ed857c
KH		 632
633 /* Disable MMIO */
306fa6f6
KH		 634 t_outb(par, PCIReg, 0x3D4);
635 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
1da177e4
LT		 636}
637
5cf13845 638static inline void crtc_unlock(struct tridentfb_par *par)
306fa6f6 639{
10172ed6
KH		 640 write3X4(par, VGA_CRTC_V_SYNC_END,
641 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
306fa6f6 642}
1da177e4
LT		 643
644/* Return flat panel's maximum x resolution */
306fa6f6 645static int __devinit get_nativex(struct tridentfb_par *par)
1da177e4 646{
245a2c2c 647 int x, y, tmp;
1da177e4
LT		 648
649 if (nativex)
650 return nativex;
651
306fa6f6 652 tmp = (read3CE(par, VertStretch) >> 4) & 3;
1da177e4
LT		 653
654 switch (tmp) {
245a2c2c
KH		 655 case 0:
656 x = 1280; y = 1024;
657 break;
658 case 2:
659 x = 1024; y = 768;
660 break;
661 case 3:
662 x = 800; y = 600;
663 break;
664 case 4:
665 x = 1400; y = 1050;
666 break;
667 case 1:
668 default:
669 x = 640; y = 480;
670 break;
1da177e4
LT		 671 }
672
673 output("%dx%d flat panel found\n", x, y);
674 return x;
675}
676
677/* Set pitch */
5cf13845 678static inline void set_lwidth(struct tridentfb_par *par, int width)
1da177e4 679{
10172ed6 680 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
306fa6f6
KH		 681 write3X4(par, AddColReg,
682 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
1da177e4
LT		 683}
684
685/* For resolutions smaller than FP resolution stretch */
306fa6f6 686static void screen_stretch(struct tridentfb_par *par)
1da177e4 687{
122e8ad3 688 if (par->chip_id != CYBERBLADEXPAi1)
306fa6f6 689 write3CE(par, BiosReg, 0);
245a2c2c 690 else
306fa6f6
KH		 691 write3CE(par, BiosReg, 8);
692 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
693 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
1da177e4
LT		 694}
695
696/* For resolutions smaller than FP resolution center */
5cf13845 697static inline void screen_center(struct tridentfb_par *par)
1da177e4 698{
306fa6f6
KH		 699 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
700 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
1da177e4
LT		 701}
702
703/* Address of first shown pixel in display memory */
306fa6f6 704static void set_screen_start(struct tridentfb_par *par, int base)
1da177e4 705{
306fa6f6 706 u8 tmp;
10172ed6
KH		 707 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
708 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
306fa6f6
KH		 709 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
710 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
711 tmp = read3X4(par, CRTHiOrd) & 0xF8;
712 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
1da177e4
LT		 713}
714
1da177e4 715/* Set dotclock frequency */
306fa6f6 716static void set_vclk(struct tridentfb_par *par, unsigned long freq)
1da177e4 717{
245a2c2c 718 int m, n, k;
6bdf1035
KH		 719 unsigned long fi, d, di;
720 unsigned char best_m = 0, best_n = 0, best_k = 0;
721 unsigned char hi, lo;
6280fd4f 722 unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
1da177e4 723
3f275ea3 724 d = 20000;
6280fd4f
KH		 725 for (k = shift; k >= 0; k--)
726 for (m = 1; m < 32; m++) {
727 n = ((m + 2) << shift) - 8;
34dec243 728 for (n = (n < 0 ? 0 : n); n < 122; n++) {
3f275ea3 729 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
34dec243 730 di = abs(fi - freq);
6280fd4f 731 if (di < d || (di == d && k == best_k)) {
245a2c2c 732 d = di;
6bdf1035
KH		 733 best_n = n;
734 best_m = m;
735 best_k = k;
245a2c2c 736 }
3f275ea3
KH		 737 if (fi > freq)
738 break;
245a2c2c 739 }
34dec243 740 }
6bdf1035
KH		 741
742 if (is_oldclock(par->chip_id)) {
743 lo = best_n | (best_m << 7);
744 hi = (best_m >> 1) | (best_k << 4);
745 } else {
746 lo = best_n;
747 hi = best_m | (best_k << 6);
748 }
749
122e8ad3 750 if (is3Dchip(par->chip_id)) {
10172ed6
KH		 751 vga_mm_wseq(par->io_virt, ClockHigh, hi);
752 vga_mm_wseq(par->io_virt, ClockLow, lo);
1da177e4 753 } else {
c1724fec
KH		 754 t_outb(par, lo, 0x43C8);
755 t_outb(par, hi, 0x43C9);
1da177e4 756 }
245a2c2c 757 debug("VCLK = %X %X\n", hi, lo);
1da177e4
LT		 758}
759
760/* Set number of lines for flat panels*/
306fa6f6 761static void set_number_of_lines(struct tridentfb_par *par, int lines)
1da177e4 762{
306fa6f6 763 int tmp = read3CE(par, CyberEnhance) & 0x8F;
1da177e4
LT		 764 if (lines > 1024)
765 tmp |= 0x50;
766 else if (lines > 768)
767 tmp |= 0x30;
768 else if (lines > 600)
769 tmp |= 0x20;
770 else if (lines > 480)
771 tmp |= 0x10;
306fa6f6 772 write3CE(par, CyberEnhance, tmp);
1da177e4
LT		 773}
774
775/*
776 * If we see that FP is active we assume we have one.
6eed8e1e 777 * Otherwise we have a CRT display. User can override.
1da177e4 778 */
6eed8e1e 779static int __devinit is_flatpanel(struct tridentfb_par *par)
1da177e4
LT		 780{
781 if (fp)
6eed8e1e 782 return 1;
122e8ad3 783 if (crt || !iscyber(par->chip_id))
6eed8e1e
KH		 784 return 0;
785 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
1da177e4
LT		 786}
787
788/* Try detecting the video memory size */
306fa6f6 789static unsigned int __devinit get_memsize(struct tridentfb_par *par)
1da177e4
LT		 790{
791 unsigned char tmp, tmp2;
792 unsigned int k;
793
794 /* If memory size provided by user */
795 if (memsize)
796 k = memsize * Kb;
797 else
122e8ad3 798 switch (par->chip_id) {
245a2c2c
KH		 799 case CYBER9525DVD:
800 k = 2560 * Kb;
801 break;
1da177e4 802 default:
306fa6f6 803 tmp = read3X4(par, SPR) & 0x0F;
1da177e4
LT		 804 switch (tmp) {
805
245a2c2c 806 case 0x01:
b614ce8b 807 k = 512 * Kb;
245a2c2c
KH		 808 break;
809 case 0x02:
810 k = 6 * Mb; /* XP */
811 break;
812 case 0x03:
813 k = 1 * Mb;
814 break;
815 case 0x04:
816 k = 8 * Mb;
817 break;
818 case 0x06:
819 k = 10 * Mb; /* XP */
820 break;
821 case 0x07:
822 k = 2 * Mb;
823 break;
824 case 0x08:
825 k = 12 * Mb; /* XP */
826 break;
827 case 0x0A:
828 k = 14 * Mb; /* XP */
829 break;
830 case 0x0C:
831 k = 16 * Mb; /* XP */
832 break;
833 case 0x0E: /* XP */
834
10172ed6 835 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
245a2c2c
KH		 836 switch (tmp2) {
837 case 0x00:
838 k = 20 * Mb;
839 break;
840 case 0x01:
841 k = 24 * Mb;
842 break;
843 case 0x10:
844 k = 28 * Mb;
845 break;
846 case 0x11:
847 k = 32 * Mb;
848 break;
849 default:
850 k = 1 * Mb;
851 break;
852 }
853 break;
854
855 case 0x0F:
856 k = 4 * Mb;
857 break;
858 default:
859 k = 1 * Mb;
1da177e4 860 break;
1da177e4 861 }
245a2c2c 862 }
1da177e4
LT		 863
864 k -= memdiff * Kb;
245a2c2c 865 output("framebuffer size = %d Kb\n", k / Kb);
1da177e4
LT		 866 return k;
867}
868
869/* See if we can handle the video mode described in var */
245a2c2c
KH		 870static int tridentfb_check_var(struct fb_var_screeninfo *var,
871 struct fb_info *info)
1da177e4 872{
6eed8e1e 873 struct tridentfb_par *par = info->par;
1da177e4 874 int bpp = var->bits_per_pixel;
bcac2d5f 875 int line_length;
74a933fe 876 int ramdac = 230000; /* 230MHz for most 3D chips */
1da177e4
LT		 877 debug("enter\n");
878
879 /* check color depth */
245a2c2c 880 if (bpp == 24)
1da177e4 881 bpp = var->bits_per_pixel = 32;
49b1f4b4
KH		 882 if (bpp != 8 && bpp != 16 && bpp != 32)
883 return -EINVAL;
54f019e5
KH		 884 if (par->chip_id == TGUI9440 && bpp == 32)
885 return -EINVAL;
245a2c2c 886 /* check whether resolution fits on panel and in memory */
6eed8e1e 887 if (par->flatpanel && nativex && var->xres > nativex)
1da177e4 888 return -EINVAL;
74a933fe
KH		 889 /* various resolution checks */
890 var->xres = (var->xres + 7) & ~0x7;
49b1f4b4 891 if (var->xres > var->xres_virtual)
74a933fe 892 var->xres_virtual = var->xres;
49b1f4b4
KH		 893 if (var->yres > var->yres_virtual)
894 var->yres_virtual = var->yres;
895 if (var->xres_virtual > 4095 || var->yres > 2048)
896 return -EINVAL;
897 /* prevent from position overflow for acceleration */
898 if (var->yres_virtual > 0xffff)
899 return -EINVAL;
bcac2d5f 900 line_length = var->xres_virtual * bpp / 8;
01a2d9ed
KH		 901
902 if (!is3Dchip(par->chip_id) &&
903 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
bcac2d5f
KH		 904 /* acceleration requires line length to be power of 2 */
905 if (line_length <= 512)
906 var->xres_virtual = 512 * 8 / bpp;
907 else if (line_length <= 1024)
908 var->xres_virtual = 1024 * 8 / bpp;
909 else if (line_length <= 2048)
910 var->xres_virtual = 2048 * 8 / bpp;
911 else if (line_length <= 4096)
912 var->xres_virtual = 4096 * 8 / bpp;
913 else if (line_length <= 8192)
914 var->xres_virtual = 8192 * 8 / bpp;
49b1f4b4
KH		 915 else
916 return -EINVAL;
bcac2d5f
KH		 917
918 line_length = var->xres_virtual * bpp / 8;
919 }
01a2d9ed 920
f330c4b1
KH		 921 /* datasheet specifies how to set panning only up to 4 MB */
922 if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
923 var->yres_virtual = ((4 << 20) / line_length) + var->yres;
924
bcac2d5f 925 if (line_length * var->yres_virtual > info->fix.smem_len)
1da177e4
LT		 926 return -EINVAL;
927
928 switch (bpp) {
245a2c2c
KH		 929 case 8:
930 var->red.offset = 0;
a4af1798
KH		 931 var->red.length = 8;
932 var->green = var->red;
933 var->blue = var->red;
245a2c2c
KH		 934 break;
935 case 16:
936 var->red.offset = 11;
937 var->green.offset = 5;
938 var->blue.offset = 0;
939 var->red.length = 5;
940 var->green.length = 6;
941 var->blue.length = 5;
942 break;
943 case 32:
944 var->red.offset = 16;
945 var->green.offset = 8;
946 var->blue.offset = 0;
947 var->red.length = 8;
948 var->green.length = 8;
949 var->blue.length = 8;
950 break;
951 default:
952 return -EINVAL;
1da177e4 953 }
74a933fe
KH		 954
955 if (is_xp(par->chip_id))
956 ramdac = 350000;
957
958 switch (par->chip_id) {
959 case TGUI9440:
54f019e5 960 ramdac = (bpp >= 16) ? 45000 : 90000;
74a933fe
KH		 961 break;
962 case CYBER9320:
963 case TGUI9660:
964 ramdac = 135000;
965 break;
966 case PROVIDIA9685:
967 case CYBER9388:
968 case CYBER9382:
969 case CYBER9385:
970 ramdac = 170000;
971 break;
972 }
973
974 /* The clock is doubled for 32 bpp */
975 if (bpp == 32)
976 ramdac /= 2;
977
978 if (PICOS2KHZ(var->pixclock) > ramdac)
979 return -EINVAL;
980
1da177e4
LT		 981 debug("exit\n");
982
983 return 0;
984
985}
245a2c2c 986
1da177e4
LT		 987/* Pan the display */
988static int tridentfb_pan_display(struct fb_var_screeninfo *var,
245a2c2c 989 struct fb_info *info)
1da177e4 990{
306fa6f6 991 struct tridentfb_par *par = info->par;
1da177e4
LT		 992 unsigned int offset;
993
994 debug("enter\n");
bcac2d5f 995 offset = (var->xoffset + (var->yoffset * var->xres_virtual))
245a2c2c 996 * var->bits_per_pixel / 32;
306fa6f6 997 set_screen_start(par, offset);
1da177e4
LT		 998 debug("exit\n");
999 return 0;
1000}
1001
5cf13845 1002static inline void shadowmode_on(struct tridentfb_par *par)
306fa6f6
KH		 1003{
1004 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1005}
1006
5cf13845 1007static inline void shadowmode_off(struct tridentfb_par *par)
306fa6f6
KH		 1008{
1009 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
1010}
1da177e4
LT		 1011
1012/* Set the hardware to the requested video mode */
1013static int tridentfb_set_par(struct fb_info *info)
1014{
5cf13845 1015 struct tridentfb_par *par = info->par;
245a2c2c
KH		 1016 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
1017 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
1018 struct fb_var_screeninfo *var = &info->var;
1da177e4
LT		 1019 int bpp = var->bits_per_pixel;
1020 unsigned char tmp;
3f275ea3
KH		 1021 unsigned long vclk;
1022
1da177e4 1023 debug("enter\n");
245a2c2c 1024 hdispend = var->xres / 8 - 1;
34dec243
KH		 1025 hsyncstart = (var->xres + var->right_margin) / 8;
1026 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
7f762d23
KH		 1027 htotal = (var->xres + var->left_margin + var->right_margin +
1028 var->hsync_len) / 8 - 5;
0e73a47f 1029 hblankstart = hdispend + 1;
7f762d23 1030 hblankend = htotal + 3;
1da177e4 1031
1da177e4
LT		 1032 vdispend = var->yres - 1;
1033 vsyncstart = var->yres + var->lower_margin;
7f762d23
KH		 1034 vsyncend = vsyncstart + var->vsync_len;
1035 vtotal = var->upper_margin + vsyncend - 2;
0e73a47f 1036 vblankstart = vdispend + 1;
7f762d23 1037 vblankend = vtotal;
1da177e4 1038
34dec243
KH		 1039 if (info->var.vmode & FB_VMODE_INTERLACED) {
1040 vtotal /= 2;
1041 vdispend /= 2;
1042 vsyncstart /= 2;
1043 vsyncend /= 2;
1044 vblankstart /= 2;
1045 vblankend /= 2;
1046 }
1047
13b0de49 1048 enable_mmio(par);
306fa6f6
KH		 1049 crtc_unlock(par);
1050 write3CE(par, CyberControl, 8);
34dec243
KH		 1051 tmp = 0xEB;
1052 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1053 tmp &= ~0x40;
1054 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1055 tmp &= ~0x80;
1da177e4 1056
6eed8e1e 1057 if (par->flatpanel && var->xres < nativex) {
1da177e4
LT		 1058 /*
1059 * on flat panels with native size larger
1060 * than requested resolution decide whether
1061 * we stretch or center
1062 */
34dec243 1063 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1da177e4 1064
306fa6f6 1065 shadowmode_on(par);
1da177e4 1066
245a2c2c 1067 if (center)
306fa6f6 1068 screen_center(par);
1da177e4 1069 else if (stretch)
306fa6f6 1070 screen_stretch(par);
1da177e4
LT		 1071
1072 } else {
34dec243 1073 t_outb(par, tmp, VGA_MIS_W);
306fa6f6 1074 write3CE(par, CyberControl, 8);
1da177e4
LT		 1075 }
1076
1077 /* vertical timing values */
10172ed6
KH		 1078 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1079 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1080 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1081 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1082 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
7f762d23 1083 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1da177e4
LT		 1084
1085 /* horizontal timing values */
10172ed6
KH		 1086 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1087 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1088 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1089 write3X4(par, VGA_CRTC_H_SYNC_END,
306fa6f6 1090 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
10172ed6 1091 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
7f762d23 1092 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1da177e4
LT		 1093
1094 /* higher bits of vertical timing values */
1095 tmp = 0x10;
1096 if (vtotal & 0x100) tmp |= 0x01;
1097 if (vdispend & 0x100) tmp |= 0x02;
1098 if (vsyncstart & 0x100) tmp |= 0x04;
1099 if (vblankstart & 0x100) tmp |= 0x08;
1100
1101 if (vtotal & 0x200) tmp |= 0x20;
1102 if (vdispend & 0x200) tmp |= 0x40;
1103 if (vsyncstart & 0x200) tmp |= 0x80;
10172ed6 1104 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1da177e4 1105
7f762d23
KH		 1106 tmp = read3X4(par, CRTHiOrd) & 0x07;
1107 tmp |= 0x08; /* line compare bit 10 */
1da177e4
LT		 1108 if (vtotal & 0x400) tmp |= 0x80;
1109 if (vblankstart & 0x400) tmp |= 0x40;
1110 if (vsyncstart & 0x400) tmp |= 0x20;
1111 if (vdispend & 0x400) tmp |= 0x10;
306fa6f6 1112 write3X4(par, CRTHiOrd, tmp);
1da177e4 1113
7f762d23
KH		 1114 tmp = (htotal >> 8) & 0x01;
1115 tmp |= (hdispend >> 7) & 0x02;
1116 tmp |= (hsyncstart >> 5) & 0x08;
1117 tmp |= (hblankstart >> 4) & 0x10;
306fa6f6 1118 write3X4(par, HorizOverflow, tmp);
245a2c2c 1119
1da177e4
LT		 1120 tmp = 0x40;
1121 if (vblankstart & 0x200) tmp |= 0x20;
245a2c2c 1122//FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
10172ed6 1123 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1da177e4 1124
10172ed6
KH		 1125 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1126 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1127 write3X4(par, VGA_CRTC_MODE, 0xC3);
1da177e4 1128
306fa6f6 1129 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1da177e4 1130
245a2c2c 1131 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
306fa6f6
KH		 1132 /* enable access extended memory */
1133 write3X4(par, CRTCModuleTest, tmp);
34dec243
KH		 1134 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1135 if (info->var.vmode & FB_VMODE_INTERLACED)
1136 tmp |= 0x4;
1137 write3CE(par, MiscIntContReg, tmp);
1da177e4 1138
306fa6f6
KH		 1139 /* enable GE for text acceleration */
1140 write3X4(par, GraphEngReg, 0x80);
1da177e4 1141
1da177e4 1142 switch (bpp) {
245a2c2c
KH		 1143 case 8:
1144 tmp = 0x00;
1145 break;
1146 case 16:
1147 tmp = 0x05;
1148 break;
1149 case 24:
1150 tmp = 0x29;
1151 break;
1152 case 32:
1153 tmp = 0x09;
1154 break;
1da177e4
LT		 1155 }
1156
306fa6f6 1157 write3X4(par, PixelBusReg, tmp);
1da177e4 1158
0e73a47f
KH		 1159 tmp = read3X4(par, DRAMControl);
1160 if (!is_oldprotect(par->chip_id))
1161 tmp |= 0x10;
122e8ad3 1162 if (iscyber(par->chip_id))
245a2c2c 1163 tmp |= 0x20;
306fa6f6 1164 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1da177e4 1165
306fa6f6 1166 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
0e73a47f
KH		 1167 if (!is_xp(par->chip_id))
1168 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
306fa6f6 1169 /* MMIO & PCI read and write burst enable */
13b0de49 1170 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
a0d92256 1171 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1da177e4 1172
10172ed6
KH		 1173 vga_mm_wseq(par->io_virt, 0, 3);
1174 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
306fa6f6 1175 /* enable 4 maps because needed in chain4 mode */
10172ed6
KH		 1176 vga_mm_wseq(par->io_virt, 2, 0x0F);
1177 vga_mm_wseq(par->io_virt, 3, 0);
1178 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1da177e4 1179
54f019e5
KH		 1180 /* convert from picoseconds to kHz */
1181 vclk = PICOS2KHZ(info->var.pixclock);
1182
306fa6f6 1183 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
65e93e03 1184 tmp = read3CE(par, MiscExtFunc) & 0xF0;
54f019e5 1185 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
65e93e03 1186 tmp |= 8;
54f019e5
KH		 1187 vclk *= 2;
1188 }
1189 set_vclk(par, vclk);
65e93e03 1190 write3CE(par, MiscExtFunc, tmp | 0x12);
306fa6f6
KH		 1191 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1192 write3CE(par, 0x6, 0x05); /* graphics mode */
1193 write3CE(par, 0x7, 0x0F); /* planes? */
1da177e4 1194
306fa6f6
KH		 1195 /* graphics mode and support 256 color modes */
1196 writeAttr(par, 0x10, 0x41);
1197 writeAttr(par, 0x12, 0x0F); /* planes */
1198 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1da177e4 1199
245a2c2c
KH		 1200 /* colors */
1201 for (tmp = 0; tmp < 0x10; tmp++)
306fa6f6 1202 writeAttr(par, tmp, tmp);
10172ed6
KH		 1203 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1204 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1da177e4
LT		 1205
1206 switch (bpp) {
245a2c2c
KH		 1207 case 8:
1208 tmp = 0;
1209 break;
245a2c2c
KH		 1210 case 16:
1211 tmp = 0x30;
1212 break;
1213 case 24:
1214 case 32:
1215 tmp = 0xD0;
1216 break;
1da177e4
LT		 1217 }
1218
10172ed6
KH		 1219 t_inb(par, VGA_PEL_IW);
1220 t_inb(par, VGA_PEL_MSK);
1221 t_inb(par, VGA_PEL_MSK);
1222 t_inb(par, VGA_PEL_MSK);
1223 t_inb(par, VGA_PEL_MSK);
1224 t_outb(par, tmp, VGA_PEL_MSK);
1225 t_inb(par, VGA_PEL_IW);
1da177e4 1226
6eed8e1e 1227 if (par->flatpanel)
306fa6f6 1228 set_number_of_lines(par, info->var.yres);
bcac2d5f
KH		 1229 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1230 set_lwidth(par, info->fix.line_length / 8);
01a2d9ed
KH		 1231
1232 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1233 par->init_accel(par, info->var.xres_virtual, bpp);
2c86a0c2 1234
1da177e4 1235 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
245a2c2c 1236 info->cmap.len = (bpp == 8) ? 256 : 16;
1da177e4
LT		 1237 debug("exit\n");
1238 return 0;
1239}
1240
1241/* Set one color register */
1242static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
245a2c2c
KH		 1243 unsigned blue, unsigned transp,
1244 struct fb_info *info)
1da177e4
LT		 1245{
1246 int bpp = info->var.bits_per_pixel;
306fa6f6 1247 struct tridentfb_par *par = info->par;
1da177e4
LT		 1248
1249 if (regno >= info->cmap.len)
1250 return 1;
1251
973d9ab2 1252 if (bpp == 8) {
10172ed6
KH		 1253 t_outb(par, 0xFF, VGA_PEL_MSK);
1254 t_outb(par, regno, VGA_PEL_IW);
1da177e4 1255
10172ed6
KH		 1256 t_outb(par, red >> 10, VGA_PEL_D);
1257 t_outb(par, green >> 10, VGA_PEL_D);
1258 t_outb(par, blue >> 10, VGA_PEL_D);
1da177e4 1259
973d9ab2
AD		 1260 } else if (regno < 16) {
1261 if (bpp == 16) { /* RGB 565 */
1262 u32 col;
1263
1264 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1265 ((blue & 0xF800) >> 11);
1266 col |= col << 16;
1267 ((u32 *)(info->pseudo_palette))[regno] = col;
1268 } else if (bpp == 32) /* ARGB 8888 */
5cf13845 1269 ((u32 *)info->pseudo_palette)[regno] =
245a2c2c
KH		 1270 ((transp & 0xFF00) << 16) |
1271 ((red & 0xFF00) << 8) |
973d9ab2 1272 ((green & 0xFF00)) |
245a2c2c 1273 ((blue & 0xFF00) >> 8);
973d9ab2 1274 }
1da177e4 1275
1da177e4
LT		 1276 return 0;
1277}
1278
5cf13845 1279/* Try blanking the screen. For flat panels it does nothing */
1da177e4
LT		 1280static int tridentfb_blank(int blank_mode, struct fb_info *info)
1281{
245a2c2c 1282 unsigned char PMCont, DPMSCont;
306fa6f6 1283 struct tridentfb_par *par = info->par;
1da177e4
LT		 1284
1285 debug("enter\n");
6eed8e1e 1286 if (par->flatpanel)
1da177e4 1287 return 0;
306fa6f6
KH		 1288 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1289 PMCont = t_inb(par, 0x83C6) & 0xFC;
1290 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
245a2c2c 1291 switch (blank_mode) {
1da177e4
LT		 1292 case FB_BLANK_UNBLANK:
1293 /* Screen: On, HSync: On, VSync: On */
1294 case FB_BLANK_NORMAL:
1295 /* Screen: Off, HSync: On, VSync: On */
1296 PMCont |= 0x03;
1297 DPMSCont |= 0x00;
1298 break;
1299 case FB_BLANK_HSYNC_SUSPEND:
1300 /* Screen: Off, HSync: Off, VSync: On */
1301 PMCont |= 0x02;
1302 DPMSCont |= 0x01;
1303 break;
1304 case FB_BLANK_VSYNC_SUSPEND:
1305 /* Screen: Off, HSync: On, VSync: Off */
1306 PMCont |= 0x02;
1307 DPMSCont |= 0x02;
1308 break;
1309 case FB_BLANK_POWERDOWN:
1310 /* Screen: Off, HSync: Off, VSync: Off */
1311 PMCont |= 0x00;
1312 DPMSCont |= 0x03;
1313 break;
245a2c2c 1314 }
1da177e4 1315
306fa6f6
KH		 1316 write3CE(par, PowerStatus, DPMSCont);
1317 t_outb(par, 4, 0x83C8);
1318 t_outb(par, PMCont, 0x83C6);
1da177e4
LT		 1319
1320 debug("exit\n");
1321
1322 /* let fbcon do a softblank for us */
1323 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1324}
1325
245a2c2c
KH		 1326static struct fb_ops tridentfb_ops = {
1327 .owner = THIS_MODULE,
1328 .fb_setcolreg = tridentfb_setcolreg,
1329 .fb_pan_display = tridentfb_pan_display,
1330 .fb_blank = tridentfb_blank,
1331 .fb_check_var = tridentfb_check_var,
1332 .fb_set_par = tridentfb_set_par,
1333 .fb_fillrect = tridentfb_fillrect,
1334 .fb_copyarea = tridentfb_copyarea,
0292be4a 1335 .fb_imageblit = tridentfb_imageblit,
49b1f4b4
KH		 1336#ifdef CONFIG_FB_TRIDENT_ACCEL
1337 .fb_sync = tridentfb_sync,
bcac2d5f 1338#endif
245a2c2c
KH		 1339};
1340
e09ed099
KH		 1341static int __devinit trident_pci_probe(struct pci_dev *dev,
1342 const struct pci_device_id *id)
1da177e4
LT		 1343{
1344 int err;
1345 unsigned char revision;
e09ed099
KH		 1346 struct fb_info *info;
1347 struct tridentfb_par *default_par;
122e8ad3
KH		 1348 int chip3D;
1349 int chip_id;
1da177e4
LT		 1350
1351 err = pci_enable_device(dev);
1352 if (err)
1353 return err;
1354
e09ed099
KH		 1355 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1356 if (!info)
1357 return -ENOMEM;
1358 default_par = info->par;
1359
1da177e4
LT		 1360 chip_id = id->device;
1361
01a2d9ed
KH		 1362#ifndef CONFIG_FB_TRIDENT_ACCEL
1363 noaccel = 1;
1364#endif
9fa68eae 1365
1da177e4 1366 /* If PCI id is 0x9660 then further detect chip type */
245a2c2c 1367
1da177e4 1368 if (chip_id == TGUI9660) {
10172ed6 1369 revision = vga_io_rseq(RevisionID);
245a2c2c 1370
1da177e4 1371 switch (revision) {
0e73a47f
KH		 1372 case 0x21:
1373 chip_id = PROVIDIA9685;
1374 break;
245a2c2c
KH		 1375 case 0x22:
1376 case 0x23:
1377 chip_id = CYBER9397;
1378 break;
1379 case 0x2A:
1380 chip_id = CYBER9397DVD;
1381 break;
1382 case 0x30:
1383 case 0x33:
1384 case 0x34:
1385 case 0x35:
1386 case 0x38:
1387 case 0x3A:
1388 case 0xB3:
1389 chip_id = CYBER9385;
1390 break;
1391 case 0x40 ... 0x43:
1392 chip_id = CYBER9382;
1393 break;
1394 case 0x4A:
1395 chip_id = CYBER9388;
1396 break;
1397 default:
1398 break;
1da177e4
LT		 1399 }
1400 }
1401
1402 chip3D = is3Dchip(chip_id);
1da177e4
LT		 1403
1404 if (is_xp(chip_id)) {
d9cad04b
KH		 1405 default_par->init_accel = xp_init_accel;
1406 default_par->wait_engine = xp_wait_engine;
1407 default_par->fill_rect = xp_fill_rect;
1408 default_par->copy_rect = xp_copy_rect;
01a2d9ed 1409 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
245a2c2c 1410 } else if (is_blade(chip_id)) {
d9cad04b
KH		 1411 default_par->init_accel = blade_init_accel;
1412 default_par->wait_engine = blade_wait_engine;
1413 default_par->fill_rect = blade_fill_rect;
1414 default_par->copy_rect = blade_copy_rect;
0292be4a 1415 default_par->image_blit = blade_image_blit;
01a2d9ed 1416 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
bcac2d5f 1417 } else if (chip3D) { /* 3DImage family left */
d9cad04b
KH		 1418 default_par->init_accel = image_init_accel;
1419 default_par->wait_engine = image_wait_engine;
1420 default_par->fill_rect = image_fill_rect;
1421 default_par->copy_rect = image_copy_rect;
01a2d9ed 1422 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
bcac2d5f
KH		 1423 } else { /* TGUI 9440/96XX family */
1424 default_par->init_accel = tgui_init_accel;
1425 default_par->wait_engine = xp_wait_engine;
1426 default_par->fill_rect = tgui_fill_rect;
1427 default_par->copy_rect = tgui_copy_rect;
01a2d9ed 1428 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1da177e4
LT		 1429 }
1430
122e8ad3
KH		 1431 default_par->chip_id = chip_id;
1432
1da177e4 1433 /* setup MMIO region */
245a2c2c 1434 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
5cf13845 1435 tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1da177e4 1436
5cf13845
KH		 1437 if (!request_mem_region(tridentfb_fix.mmio_start,
1438 tridentfb_fix.mmio_len, "tridentfb")) {
1da177e4 1439 debug("request_region failed!\n");
3876ae8b 1440 framebuffer_release(info);
1da177e4
LT		 1441 return -1;
1442 }
1443
e09ed099
KH		 1444 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1445 tridentfb_fix.mmio_len);
1da177e4 1446
e09ed099 1447 if (!default_par->io_virt) {
1da177e4 1448 debug("ioremap failed\n");
e8ed857c
KH		 1449 err = -1;
1450 goto out_unmap1;
1da177e4
LT		 1451 }
1452
13b0de49 1453 enable_mmio(default_par);
bcac2d5f 1454
1da177e4 1455 /* setup framebuffer memory */
245a2c2c 1456 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
e09ed099 1457 tridentfb_fix.smem_len = get_memsize(default_par);
245a2c2c 1458
5cf13845
KH		 1459 if (!request_mem_region(tridentfb_fix.smem_start,
1460 tridentfb_fix.smem_len, "tridentfb")) {
1da177e4 1461 debug("request_mem_region failed!\n");
e09ed099 1462 disable_mmio(info->par);
a02f6402 1463 err = -1;
e8ed857c 1464 goto out_unmap1;
1da177e4
LT		 1465 }
1466
e09ed099
KH		 1467 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1468 tridentfb_fix.smem_len);
1da177e4 1469
e09ed099 1470 if (!info->screen_base) {
1da177e4 1471 debug("ioremap failed\n");
a02f6402 1472 err = -1;
e8ed857c 1473 goto out_unmap2;
1da177e4
LT		 1474 }
1475
6eed8e1e 1476 default_par->flatpanel = is_flatpanel(default_par);
1da177e4 1477
6eed8e1e 1478 if (default_par->flatpanel)
e09ed099 1479 nativex = get_nativex(default_par);
1da177e4 1480
e09ed099
KH		 1481 info->fix = tridentfb_fix;
1482 info->fbops = &tridentfb_ops;
aa0aa8ab 1483 info->pseudo_palette = default_par->pseudo_pal;
1da177e4 1484
e09ed099 1485 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
01a2d9ed
KH		 1486 if (!noaccel && default_par->init_accel) {
1487 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1488 info->flags |= FBINFO_HWACCEL_COPYAREA;
1489 info->flags |= FBINFO_HWACCEL_FILLRECT;
1490 } else
1491 info->flags |= FBINFO_HWACCEL_DISABLED;
1492
0292be4a
KH		 1493 info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
1494 if (!info->pixmap.addr) {
1495 err = -ENOMEM;
1496 goto out_unmap2;
1497 }
1498
1499 info->pixmap.size = 4096;
1500 info->pixmap.buf_align = 4;
1501 info->pixmap.scan_align = 1;
1502 info->pixmap.access_align = 32;
1503 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1504
1505 if (default_par->image_blit) {
1506 info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
1507 info->pixmap.scan_align = 4;
1508 }
1509
1510 if (noaccel) {
1511 printk(KERN_DEBUG "disabling acceleration\n");
1512 info->flags |= FBINFO_HWACCEL_DISABLED;
1513 info->pixmap.scan_align = 1;
1514 }
1515
ea8ee55c 1516 if (!fb_find_mode(&info->var, info,
07f41e45 1517 mode_option, NULL, 0, NULL, bpp)) {
a02f6402 1518 err = -EINVAL;
e8ed857c 1519 goto out_unmap2;
a02f6402 1520 }
e09ed099 1521 err = fb_alloc_cmap(&info->cmap, 256, 0);
e8ed857c
KH		 1522 if (err < 0)
1523 goto out_unmap2;
1524
ea8ee55c 1525 info->var.activate |= FB_ACTIVATE_NOW;
e09ed099
KH		 1526 info->device = &dev->dev;
1527 if (register_framebuffer(info) < 0) {
5cf13845 1528 printk(KERN_ERR "tridentfb: could not register framebuffer\n");
e09ed099 1529 fb_dealloc_cmap(&info->cmap);
a02f6402 1530 err = -EINVAL;
e8ed857c 1531 goto out_unmap2;
1da177e4
LT		 1532 }
1533 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
ea8ee55c
KH		 1534 info->node, info->fix.id, info->var.xres,
1535 info->var.yres, info->var.bits_per_pixel);
e09ed099
KH		 1536
1537 pci_set_drvdata(dev, info);
1da177e4 1538 return 0;
a02f6402 1539
e8ed857c 1540out_unmap2:
0292be4a 1541 kfree(info->pixmap.addr);
e09ed099
KH		 1542 if (info->screen_base)
1543 iounmap(info->screen_base);
e8ed857c 1544 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
e09ed099 1545 disable_mmio(info->par);
e8ed857c 1546out_unmap1:
e09ed099
KH		 1547 if (default_par->io_virt)
1548 iounmap(default_par->io_virt);
e8ed857c 1549 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
e09ed099 1550 framebuffer_release(info);
a02f6402 1551 return err;
1da177e4
LT		 1552}
1553
245a2c2c 1554static void __devexit trident_pci_remove(struct pci_dev *dev)
1da177e4 1555{
e09ed099
KH		 1556 struct fb_info *info = pci_get_drvdata(dev);
1557 struct tridentfb_par *par = info->par;
1558
1559 unregister_framebuffer(info);
1da177e4 1560 iounmap(par->io_virt);
e09ed099 1561 iounmap(info->screen_base);
1da177e4 1562 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
e8ed857c 1563 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
e09ed099 1564 pci_set_drvdata(dev, NULL);
0292be4a 1565 kfree(info->pixmap.addr);
e09ed099 1566 framebuffer_release(info);
1da177e4
LT		 1567}
1568
1569/* List of boards that we are trying to support */
1570static struct pci_device_id trident_devices[] = {
245a2c2c
KH		 1571 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1572 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1573 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1574 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1575 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1576 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1577 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1578 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
a0d92256 1579 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
245a2c2c
KH		 1580 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1581 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1582 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1583 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1584 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1585 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1586 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1587 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1588 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1589 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1590 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1591 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4 1592 {0,}
245a2c2c
KH		 1593};
1594
1595MODULE_DEVICE_TABLE(pci, trident_devices);
1da177e4
LT		 1596
1597static struct pci_driver tridentfb_pci_driver = {
245a2c2c
KH		 1598 .name = "tridentfb",
1599 .id_table = trident_devices,
1600 .probe = trident_pci_probe,
1601 .remove = __devexit_p(trident_pci_remove)
1da177e4
LT		 1602};
1603
1604/*
1605 * Parse user specified options (`video=trident:')
1606 * example:
245a2c2c 1607 * video=trident:800x600,bpp=16,noaccel
1da177e4
LT		 1608 */
1609#ifndef MODULE
07f41e45 1610static int __init tridentfb_setup(char *options)
1da177e4 1611{
245a2c2c 1612 char *opt;
1da177e4
LT		 1613 if (!options || !*options)
1614 return 0;
245a2c2c
KH		 1615 while ((opt = strsep(&options, ",")) != NULL) {
1616 if (!*opt)
1617 continue;
1618 if (!strncmp(opt, "noaccel", 7))
1da177e4 1619 noaccel = 1;
245a2c2c 1620 else if (!strncmp(opt, "fp", 2))
6eed8e1e 1621 fp = 1;
245a2c2c 1622 else if (!strncmp(opt, "crt", 3))
6eed8e1e 1623 fp = 0;
245a2c2c
KH		 1624 else if (!strncmp(opt, "bpp=", 4))
1625 bpp = simple_strtoul(opt + 4, NULL, 0);
1626 else if (!strncmp(opt, "center", 6))
1da177e4 1627 center = 1;
245a2c2c 1628 else if (!strncmp(opt, "stretch", 7))
1da177e4 1629 stretch = 1;
245a2c2c
KH		 1630 else if (!strncmp(opt, "memsize=", 8))
1631 memsize = simple_strtoul(opt + 8, NULL, 0);
1632 else if (!strncmp(opt, "memdiff=", 8))
1633 memdiff = simple_strtoul(opt + 8, NULL, 0);
1634 else if (!strncmp(opt, "nativex=", 8))
1635 nativex = simple_strtoul(opt + 8, NULL, 0);
1da177e4 1636 else
07f41e45 1637 mode_option = opt;
1da177e4
LT		 1638 }
1639 return 0;
1640}
1641#endif
1642
1643static int __init tridentfb_init(void)
1644{
1645#ifndef MODULE
1646 char *option = NULL;
1647
1648 if (fb_get_options("tridentfb", &option))
1649 return -ENODEV;
1650 tridentfb_setup(option);
1651#endif
1da177e4
LT		 1652 return pci_register_driver(&tridentfb_pci_driver);
1653}
1654
1655static void __exit tridentfb_exit(void)
1656{
1657 pci_unregister_driver(&tridentfb_pci_driver);
1658}
1659
1da177e4
LT		 1660module_init(tridentfb_init);
1661module_exit(tridentfb_exit);
1662
1663MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1664MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1665MODULE_LICENSE("GPL");
1666
Linux 6.x block layer and io_uring tree(s)