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[PATCH] vt: proper prototypes for some console functions
[linux-2.6-block.git] / drivers / video / sstfb.c
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1da177e4
LT		 1/*
2 * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
3 *
4 * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
5 *
6 * Created 15 Jan 2000 by Ghozlane Toumi
7 *
8 * Contributions (and many thanks) :
9 *
10 * 03/2001 James Simmons <jsimmons@infradead.org>
11 * 04/2001 Paul Mundt <lethal@chaoticdreams.org>
12 * 05/2001 Urs Ganse <ursg@uni.de>
13 * (initial work on voodoo2 port, interlace)
14 * 09/2002 Helge Deller <deller@gmx.de>
15 * (enable driver on big-endian machines (hppa), ioctl fixes)
16 * 12/2002 Helge Deller <deller@gmx.de>
17 * (port driver to new frambuffer infrastructure)
18 * 01/2003 Helge Deller <deller@gmx.de>
19 * (initial work on fb hardware acceleration for voodoo2)
20 *
21 */
22
23/*
24 * The voodoo1 has the following memory mapped address space:
25 * 0x000000 - 0x3fffff : registers (4MB)
26 * 0x400000 - 0x7fffff : linear frame buffer (4MB)
27 * 0x800000 - 0xffffff : texture memory (8MB)
28 */
29
30/*
31 * misc notes, TODOs, toASKs, and deep thoughts
32
33-TODO: at one time or another test that the mode is acceptable by the monitor
34-ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
c30fe7f7 35 which one should i use ? is there any preferred one ? It seems ARGB is
1da177e4
LT		 36 the one ...
37-TODO: in set_var check the validity of timings (hsync vsync)...
38-TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via
39 a nop command. so it's ok as long as the commands we pass don't go
40 through the fifo. warning: issuing a nop command seems to need pci_fifo
41-FIXME: in case of failure in the init sequence, be sure we return to a safe
42 state.
43-FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20)
44 */
45
46/*
47 * debug info
48 * SST_DEBUG : enable debugging
49 * SST_DEBUG_REG : debug registers
50 * 0 : no debug
51 * 1 : dac calls, [un]set_bits, FbiInit
52 * 2 : insane debug level (log every register read/write)
53 * SST_DEBUG_FUNC : functions
54 * 0 : no debug
55 * 1 : function call / debug ioctl
56 * 2 : variables
57 * 3 : flood . you don't want to do that. trust me.
58 * SST_DEBUG_VAR : debug display/var structs
59 * 0 : no debug
60 * 1 : dumps display, fb_var
61 *
62 * sstfb specific ioctls:
63 * toggle vga (0x46db) : toggle vga_pass_through
64 * fill fb (0x46dc) : fills fb
65 * test disp (0x46de) : draws a test image
66 */
67
68#undef SST_DEBUG
69
70/* enable 24/32 bpp functions ? (completely untested!) */
71#undef EN_24_32_BPP
72
73/*
74 Default video mode .
75 0 800x600@60 took from glide
76 1 640x480@75 took from glide
77 2 1024x768@76 std fb.mode
78 3 640x480@60 glide default */
79#define DEFAULT_MODE 3
80
81/*
82 * Includes
83 */
84
1da177e4
LT		 85#include <linux/string.h>
86#include <linux/kernel.h>
87#include <linux/module.h>
88#include <linux/fb.h>
89#include <linux/pci.h>
90#include <linux/delay.h>
91#include <linux/init.h>
92#include <linux/slab.h>
93#include <asm/io.h>
94#include <asm/ioctl.h>
95#include <asm/uaccess.h>
96#include <video/sstfb.h>
97
98
99/* initialized by setup */
100
101static int vgapass; /* enable Vga passthrough cable */
102static int mem; /* mem size in MB, 0 = autodetect */
103static int clipping = 1; /* use clipping (slower, safer) */
104static int gfxclk; /* force FBI freq in Mhz . Dangerous */
105static int slowpci; /* slow PCI settings */
106
107static char *mode_option __devinitdata;
108
109enum {
110 ID_VOODOO1 = 0,
111 ID_VOODOO2 = 1,
112};
113
114#define IS_VOODOO2(par) ((par)->type == ID_VOODOO2)
115
116static struct sst_spec voodoo_spec[] __devinitdata = {
117 { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 },
118 { .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 },
119};
120
121static struct fb_var_screeninfo sstfb_default =
122#if ( DEFAULT_MODE == 0 )
123 { /* 800x600@60, 16 bpp .borowed from glide/sst1/include/sst1init.h */
124 800, 600, 800, 600, 0, 0, 16, 0,
125 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
126 0, 0, -1, -1, 0,
127 25000, 86, 41, 23, 1, 127, 4,
128 0, FB_VMODE_NONINTERLACED };
129#elif ( DEFAULT_MODE == 1 )
130 {/* 640x480@75, 16 bpp .borowed from glide/sst1/include/sst1init.h */
131 640, 480, 640, 480, 0, 0, 16, 0,
132 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
133 0, 0, -1, -1, 0,
134 31746, 118, 17, 16, 1, 63, 3,
135 0, FB_VMODE_NONINTERLACED };
136#elif ( DEFAULT_MODE == 2 )
137 { /* 1024x768@76 took from my /etc/fb.modes */
138 1024, 768, 1024, 768,0, 0, 16,0,
139 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
140 0, 0, -1, -1, 0,
141 11764, 208, 8, 36, 16, 120, 3 ,
142 0, FB_VMODE_NONINTERLACED };
143#elif ( DEFAULT_MODE == 3 )
144 { /* 640x480@60 , 16bpp glide default ?*/
145 640, 480, 640, 480, 0, 0, 16, 0,
146 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
147 0, 0, -1, -1, 0,
148 39721 , 38, 26 , 25 ,18 , 96 ,2,
149 0, FB_VMODE_NONINTERLACED };
150#elif
151 #error "Invalid DEFAULT_MODE value !"
152#endif
153
154
155/*
156 * debug functions
157 */
158
159static void sstfb_drawdebugimage(struct fb_info *info);
160static int sstfb_dump_regs(struct fb_info *info);
161
162
163#if (SST_DEBUG_REG > 0)
164static void sst_dbg_print_read_reg(u32 reg, u32 val) {
165 const char *regname;
166 switch (reg) {
167 case FBIINIT0: regname = "FbiInit0"; break;
168 case FBIINIT1: regname = "FbiInit1"; break;
169 case FBIINIT2: regname = "FbiInit2"; break;
170 case FBIINIT3: regname = "FbiInit3"; break;
171 case FBIINIT4: regname = "FbiInit4"; break;
172 case FBIINIT5: regname = "FbiInit5"; break;
173 case FBIINIT6: regname = "FbiInit6"; break;
174 default: regname = NULL; break;
175 }
176 if (regname == NULL)
177 r_ddprintk("sst_read(%#x): %#x\n", reg, val);
178 else
179 r_dprintk(" sst_read(%s): %#x\n", regname, val);
180}
181
182static void sst_dbg_print_write_reg(u32 reg, u32 val) {
183 const char *regname;
184 switch (reg) {
185 case FBIINIT0: regname = "FbiInit0"; break;
186 case FBIINIT1: regname = "FbiInit1"; break;
187 case FBIINIT2: regname = "FbiInit2"; break;
188 case FBIINIT3: regname = "FbiInit3"; break;
189 case FBIINIT4: regname = "FbiInit4"; break;
190 case FBIINIT5: regname = "FbiInit5"; break;
191 case FBIINIT6: regname = "FbiInit6"; break;
192 default: regname = NULL; break;
193 }
194 if (regname == NULL)
195 r_ddprintk("sst_write(%#x, %#x)\n", reg, val);
196 else
197 r_dprintk(" sst_write(%s, %#x)\n", regname, val);
198}
199#else /* (SST_DEBUG_REG > 0) */
200# define sst_dbg_print_read_reg(reg, val) do {} while(0)
201# define sst_dbg_print_write_reg(reg, val) do {} while(0)
202#endif /* (SST_DEBUG_REG > 0) */
203
204/*
205 * hardware access functions
206 */
207
208/* register access */
209#define sst_read(reg) __sst_read(par->mmio_vbase, reg)
210#define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val)
211#define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val)
212#define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val)
213#define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg)
214#define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val)
215#define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg)
216#define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val)
217
218static inline u32 __sst_read(u8 __iomem *vbase, u32 reg)
219{
220 u32 ret = readl(vbase + reg);
221 sst_dbg_print_read_reg(reg, ret);
222 return ret;
223}
224
225static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val)
226{
227 sst_dbg_print_write_reg(reg, val);
228 writel(val, vbase + reg);
229}
230
231static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val)
232{
233 r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val);
234 __sst_write(vbase, reg, __sst_read(vbase, reg) | val);
235}
236
237static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val)
238{
239 r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val);
240 __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val);
241}
242
243/*
244 * wait for the fbi chip. ASK: what happens if the fbi is stuck ?
245 *
246 * the FBI is supposed to be ready if we receive 5 time
247 * in a row a "idle" answer to our requests
248 */
249
250#define sst_wait_idle() __sst_wait_idle(par->mmio_vbase)
251
252static int __sst_wait_idle(u8 __iomem *vbase)
253{
254 int count = 0;
255
256 /* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */
257
258 while(1) {
259 if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) {
260 f_dddprintk("status: busy\n");
261/* FIXME basicaly, this is a busy wait. maybe not that good. oh well;
262 * this is a small loop after all.
263 * Or maybe we should use mdelay() or udelay() here instead ? */
264 count = 0;
265 } else {
266 count++;
267 f_dddprintk("status: idle(%d)\n", count);
268 }
269 if (count >= 5) return 1;
270/* XXX do something to avoid hanging the machine if the voodoo is out */
271 }
272}
273
274
275/* dac access */
276/* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */
277static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg)
278{
279 u8 ret;
280
281 reg &= 0x07;
282 __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD );
283 __sst_wait_idle(vbase);
284 /* udelay(10); */
285 ret = __sst_read(vbase, DAC_READ) & 0xff;
286 r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret);
287
288 return ret;
289}
290
291static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val)
292{
293 r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val);
294 reg &= 0x07;
295 __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val);
296}
297
298/* indexed access to ti/att dacs */
299static u32 __dac_i_read(u8 __iomem *vbase, u8 reg)
300{
301 u32 ret;
302
303 __sst_dac_write(vbase, DACREG_ADDR_I, reg);
304 ret = __sst_dac_read(vbase, DACREG_DATA_I);
305 r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret);
306 return ret;
307}
308static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val)
309{
310 r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val);
311 __sst_dac_write(vbase, DACREG_ADDR_I, reg);
312 __sst_dac_write(vbase, DACREG_DATA_I, val);
313}
314
315/* compute the m,n,p , returns the real freq
316 * (ics datasheet : N <-> N1 , P <-> N2)
317 *
318 * Fout= Fref * (M+2)/( 2^P * (N+2))
319 * we try to get close to the asked freq
320 * with P as high, and M as low as possible
321 * range:
322 * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63
323 * ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31
324 * we'll use the lowest limitation, should be precise enouth
325 */
326static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t)
327{
328 int m, m2, n, p, best_err, fout;
329 int best_n = -1;
330 int best_m = -1;
331
332 best_err = freq;
333 p = 3;
334 /* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/
335 while (((1 << p) * freq > VCO_MAX) && (p >= 0))
336 p--;
337 if (p == -1)
338 return -EINVAL;
339 for (n = 1; n < 32; n++) {
340 /* calc 2 * m so we can round it later*/
341 m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ;
342
343 m = (m2 % 2 ) ? m2/2+1 : m2/2 ;
344 if (m >= 128)
345 break;
346 fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2));
347 if ((abs(fout - freq) < best_err) && (m > 0)) {
348 best_n = n;
349 best_m = m;
350 best_err = abs(fout - freq);
351 /* we get the lowest m , allowing 0.5% error in freq*/
352 if (200*best_err < freq) break;
353 }
354 }
355 if (best_n == -1) /* unlikely, but who knows ? */
356 return -EINVAL;
357 t->p = p;
358 t->n = best_n;
359 t->m = best_m;
360 *freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2));
361 f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n",
362 t->m, t->n, t->p, *freq_out);
363 return 0;
364}
365
366/*
367 * clear lfb screen
368 */
369static void sstfb_clear_screen(struct fb_info *info)
370{
371 /* clear screen */
372 fb_memset(info->screen_base, 0, info->fix.smem_len);
373}
374
375
376/**
377 * sstfb_check_var - Optional function. Validates a var passed in.
378 * @var: frame buffer variable screen structure
379 * @info: frame buffer structure that represents a single frame buffer
380 */
381static int sstfb_check_var(struct fb_var_screeninfo *var,
382 struct fb_info *info)
383{
7227576f 384 struct sstfb_par *par = info->par;
1da177e4
LT		 385 int hSyncOff = var->xres + var->right_margin + var->left_margin;
386 int vSyncOff = var->yres + var->lower_margin + var->upper_margin;
387 int vBackPorch = var->left_margin, yDim = var->yres;
388 int vSyncOn = var->vsync_len;
389 int tiles_in_X, real_length;
390 unsigned int freq;
391
392 if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) {
393 eprintk("Pixclock at %ld KHZ out of range\n",
394 PICOS2KHZ(var->pixclock));
395 return -EINVAL;
396 }
397 var->pixclock = KHZ2PICOS(freq);
398
399 if (var->vmode & FB_VMODE_INTERLACED)
400 vBackPorch += (vBackPorch % 2);
401 if (var->vmode & FB_VMODE_DOUBLE) {
402 vBackPorch <<= 1;
403 yDim <<=1;
404 vSyncOn <<=1;
405 vSyncOff <<=1;
406 }
407
408 switch (var->bits_per_pixel) {
409 case 0 ... 16 :
410 var->bits_per_pixel = 16;
411 break;
412#ifdef EN_24_32_BPP
413 case 17 ... 24 :
414 var->bits_per_pixel = 24;
415 break;
416 case 25 ... 32 :
417 var->bits_per_pixel = 32;
418 break;
419#endif
420 default :
421 eprintk("Unsupported bpp %d\n", var->bits_per_pixel);
422 return -EINVAL;
423 }
424
425 /* validity tests */
426 if ((var->xres <= 1) || (yDim <= 0 )
427 || (var->hsync_len <= 1)
428 || (hSyncOff <= 1)
429 || (var->left_margin <= 2)
430 || (vSyncOn <= 0)
431 || (vSyncOff <= 0)
432 || (vBackPorch <= 0)) {
433 return -EINVAL;
434 }
435
436 if (IS_VOODOO2(par)) {
437 /* Voodoo 2 limits */
438 tiles_in_X = (var->xres + 63 ) / 64 * 2;
439
440 if (((var->xres - 1) >= POW2(11)) || (yDim >= POW2(11))) {
441 eprintk("Unsupported resolution %dx%d\n",
442 var->xres, var->yres);
443 return -EINVAL;
444 }
445
446 if (((var->hsync_len-1) >= POW2(9))
447 || ((hSyncOff-1) >= POW2(11))
448 || ((var->left_margin - 2) >= POW2(9))
449 || (vSyncOn >= POW2(13))
450 || (vSyncOff >= POW2(13))
451 || (vBackPorch >= POW2(9))
452 || (tiles_in_X >= POW2(6))
453 || (tiles_in_X <= 0)) {
454 eprintk("Unsupported Timings\n");
455 return -EINVAL;
456 }
457 } else {
458 /* Voodoo limits */
459 tiles_in_X = (var->xres + 63 ) / 64;
460
461 if (var->vmode) {
462 eprintk("Interlace/Doublescan not supported %#x\n",
463 var->vmode);
464 return -EINVAL;
465 }
466 if (((var->xres - 1) >= POW2(10)) || (var->yres >= POW2(10))) {
467 eprintk("Unsupported resolution %dx%d\n",
468 var->xres, var->yres);
469 return -EINVAL;
470 }
471 if (((var->hsync_len - 1) >= POW2(8))
472 || ((hSyncOff-1) >= POW2(10))
473 || ((var->left_margin - 2) >= POW2(8))
474 || (vSyncOn >= POW2(12))
475 || (vSyncOff >= POW2(12))
476 || (vBackPorch >= POW2(8))
477 || (tiles_in_X >= POW2(4))
478 || (tiles_in_X <= 0)) {
479 eprintk("Unsupported Timings\n");
480 return -EINVAL;
481 }
482 }
483
484 /* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */
485 /* FIXME: i don't like this... looks wrong */
486 real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 )
487 * ((var->bits_per_pixel == 16) ? 2 : 4);
488
489 if ((real_length * yDim) > info->fix.smem_len) {
490 eprintk("Not enough video memory\n");
491 return -ENOMEM;
492 }
493
494 var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT);
495 var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE);
496 var->xoffset = 0;
497 var->yoffset = 0;
498 var->height = -1;
499 var->width = -1;
500
501 /*
502 * correct the color bit fields
503 */
504 /* var->{red|green|blue}.msb_right = 0; */
505
506 switch (var->bits_per_pixel) {
507 case 16: /* RGB 565 LfbMode 0 */
508 var->red.length = 5;
509 var->green.length = 6;
510 var->blue.length = 5;
511 var->transp.length = 0;
512
513 var->red.offset = 11;
514 var->green.offset = 5;
515 var->blue.offset = 0;
516 var->transp.offset = 0;
517 break;
518#ifdef EN_24_32_BPP
519 case 24: /* RGB 888 LfbMode 4 */
520 case 32: /* ARGB 8888 LfbMode 5 */
521 var->red.length = 8;
522 var->green.length = 8;
523 var->blue.length = 8;
524 var->transp.length = 0;
525
526 var->red.offset = 16;
527 var->green.offset = 8;
528 var->blue.offset = 0;
529 var->transp.offset = 0; /* in 24bpp we fake a 32 bpp mode */
530 break;
531#endif
532 default:
533 return -EINVAL;
534 }
535 return 0;
536}
537
538/**
539 * sstfb_set_par - Optional function. Alters the hardware state.
540 * @info: frame buffer structure that represents a single frame buffer
541 */
542static int sstfb_set_par(struct fb_info *info)
543{
7227576f 544 struct sstfb_par *par = info->par;
1da177e4
LT		 545 u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0;
546 struct pci_dev *sst_dev = par->dev;
547 unsigned int freq;
548 int ntiles;
549
550 par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin;
551
552 par->yDim = info->var.yres;
553 par->vSyncOn = info->var.vsync_len;
554 par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin;
555 par->vBackPorch = info->var.upper_margin;
556
557 /* We need par->pll */
558 sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll);
559
560 if (info->var.vmode & FB_VMODE_INTERLACED)
561 par->vBackPorch += (par->vBackPorch % 2);
562 if (info->var.vmode & FB_VMODE_DOUBLE) {
563 par->vBackPorch <<= 1;
564 par->yDim <<=1;
565 par->vSyncOn <<=1;
566 par->vSyncOff <<=1;
567 }
568
569 if (IS_VOODOO2(par)) {
570 /* voodoo2 has 32 pixel wide tiles , BUT stange things
571 happen with odd number of tiles */
572 par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2;
573 } else {
574 /* voodoo1 has 64 pixels wide tiles. */
575 par->tiles_in_X = (info->var.xres + 63 ) / 64;
576 }
577
578 f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n");
579 f_ddprintk("%-7d %-8d %-7d %-8d\n",
580 info->var.hsync_len, par->hSyncOff,
581 par->vSyncOn, par->vSyncOff);
582 f_ddprintk("left_margin upper_margin xres yres Freq\n");
583 f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n",
584 info->var.left_margin, info->var.upper_margin,
585 info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock));
586
587 sst_write(NOPCMD, 0);
588 sst_wait_idle();
589 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
590 sst_set_bits(FBIINIT1, VIDEO_RESET);
591 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
592 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
593 sst_wait_idle();
594
595 /*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */
596
597 sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2));
598 sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1));
599 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1));
600 sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn);
601
602 fbiinit2 = sst_read(FBIINIT2);
603 fbiinit3 = sst_read(FBIINIT3);
604
605 /* everything is reset. we enable fbiinit2/3 remap : dac acces ok */
606 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
607 PCI_EN_INIT_WR | PCI_REMAP_DAC );
608
609 par->dac_sw.set_vidmod(info, info->var.bits_per_pixel);
610
611 /* set video clock */
612 par->dac_sw.set_pll(info, &par->pll, VID_CLOCK);
613
614 /* disable fbiinit2/3 remap */
615 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
616 PCI_EN_INIT_WR);
617
618 /* restore fbiinit2/3 */
619 sst_write(FBIINIT2,fbiinit2);
620 sst_write(FBIINIT3,fbiinit3);
621
622 fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK)
623 | EN_DATA_OE
624 | EN_BLANK_OE
625 | EN_HVSYNC_OE
626 | EN_DCLK_OE
627 /* | (15 << TILES_IN_X_SHIFT) */
628 | SEL_INPUT_VCLK_2X
629 /* | (2 << VCLK_2X_SEL_DEL_SHIFT)
630 | (2 << VCLK_DEL_SHIFT) */;
631/* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28)
632 in (near) future set them accordingly to revision + resolution (cf glide)
633 first understand what it stands for :)
634 FIXME: there are some artefacts... check for the vclk_in_delay
635 lets try with 6ns delay in both vclk_out & in...
636 doh... they're still there :\
637*/
638
639 ntiles = par->tiles_in_X;
640 if (IS_VOODOO2(par)) {
641 fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT
642 | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT;
643/* as the only value of importance for us in fbiinit6 is tiles in X (lsb),
644 and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just
645 write our value. BTW due to the dac unable to read odd number of tiles, this
646 field is always null ... */
647 fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT;
648 }
649 else
650 fbiinit1 |= ntiles << TILES_IN_X_SHIFT;
651
652 switch (info->var.bits_per_pixel) {
653 case 16:
654 fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL;
655 break;
656#ifdef EN_24_32_BPP
657 case 24:
658 case 32:
659 /* sst_set_bits(FBIINIT1, SEL_SOURCE_VCLK_2X_DIV2 | EN_24BPP);*/
660 fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL | EN_24BPP;
661 break;
662#endif
663 default:
664 return -EINVAL;
665 }
666 sst_write(FBIINIT1, fbiinit1);
667 if (IS_VOODOO2(par)) {
668 sst_write(FBIINIT6, fbiinit6);
669 fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ;
670 if (info->var.vmode & FB_VMODE_INTERLACED)
671 fbiinit5 |= INTERLACE;
672 if (info->var.vmode & FB_VMODE_DOUBLE)
673 fbiinit5 |= VDOUBLESCAN;
674 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
675 fbiinit5 |= HSYNC_HIGH;
676 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
677 fbiinit5 |= VSYNC_HIGH;
678 sst_write(FBIINIT5, fbiinit5);
679 }
680 sst_wait_idle();
681 sst_unset_bits(FBIINIT1, VIDEO_RESET);
682 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
683 sst_set_bits(FBIINIT2, EN_DRAM_REFRESH);
684 /* disables fbiinit writes */
685 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
686
687 /* set lfbmode : set mode + front buffer for reads/writes
688 + disable pipeline */
689 switch (info->var.bits_per_pixel) {
690 case 16:
691 lfbmode = LFB_565;
692 break;
693#ifdef EN_24_32_BPP
694 case 24:
695 lfbmode = LFB_888;
696 break;
697 case 32:
698 lfbmode = LFB_8888;
699 break;
700#endif
701 default:
702 return -EINVAL;
703 }
704
705#if defined(__BIG_ENDIAN)
706 /* Enable byte-swizzle functionality in hardware.
707 * With this enabled, all our read- and write-accesses to
708 * the voodoo framebuffer can be done in native format, and
709 * the hardware will automatically convert it to little-endian.
710 * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */
711 lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR |
712 LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD );
713#endif
714
715 if (clipping) {
716 sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE);
717 /*
718 * Set "clipping" dimensions. If clipping is disabled and
719 * writes to offscreen areas of the framebuffer are performed,
720 * the "behaviour is undefined" (_very_ undefined) - Urs
721 */
722 /* btw, it requires enabling pixel pipeline in LFBMODE .
723 off screen read/writes will just wrap and read/print pixels
724 on screen. Ugly but not that dangerous */
725 f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n",
726 info->var.xres - 1, par->yDim - 1);
727
728 sst_write(CLIP_LEFT_RIGHT, info->var.xres);
729 sst_write(CLIP_LOWY_HIGHY, par->yDim);
730 sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE);
731 } else {
732 /* no clipping : direct access, no pipeline */
733 sst_write(LFBMODE, lfbmode);
734 }
735 return 0;
736}
737
738/**
739 * sstfb_setcolreg - Optional function. Sets a color register.
740 * @regno: hardware colormap register
741 * @red: frame buffer colormap structure
742 * @green: The green value which can be up to 16 bits wide
743 * @blue: The blue value which can be up to 16 bits wide.
744 * @transp: If supported the alpha value which can be up to 16 bits wide.
745 * @info: frame buffer info structure
746 */
747static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
748 u_int transp, struct fb_info *info)
749{
7227576f 750 struct sstfb_par *par = info->par;
1da177e4
LT		 751 u32 col;
752
753 f_dddprintk("sstfb_setcolreg\n");
754 f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n",
755 regno, red, green, blue, transp);
7227576f
AD		 756 if (regno > 15)
757 return 0;
1da177e4
LT		 758
759 red >>= (16 - info->var.red.length);
760 green >>= (16 - info->var.green.length);
761 blue >>= (16 - info->var.blue.length);
762 transp >>= (16 - info->var.transp.length);
763 col = (red << info->var.red.offset)
764 | (green << info->var.green.offset)
765 | (blue << info->var.blue.offset)
766 | (transp << info->var.transp.offset);
767
7227576f 768 par->palette[regno] = col;
1da177e4
LT		 769
770 return 0;
771}
772
67a6680d 773static int sstfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1da177e4 774{
7227576f 775 struct sstfb_par *par = info->par;
1da177e4
LT		 776 struct pci_dev *sst_dev = par->dev;
777 u32 fbiinit0, tmp, val;
778 u_long p;
779
780 switch (cmd) {
781
782 /* dump current FBIINIT values to system log */
783 case _IO('F', 0xdb): /* 0x46db */
784 return sstfb_dump_regs(info);
785
786 /* fills lfb with #arg pixels */
787 case _IOW('F', 0xdc, u32): /* 0x46dc */
788 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
789 return -EFAULT;
790 if (val > info->fix.smem_len)
791 val = info->fix.smem_len;
792 printk("filling %#x \n", val);
793 for (p=0 ; p<val; p+=2)
794 writew(p >> 6, info->screen_base + p);
795 return 0;
796
797 /* change VGA pass_through mode */
798 case _IOW('F', 0xdd, u32): /* 0x46dd */
799 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
800 return -EFAULT;
801 pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp);
802 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
803 tmp | PCI_EN_INIT_WR );
804 fbiinit0 = sst_read (FBIINIT0);
805 if (val) {
806 sst_write(FBIINIT0, fbiinit0 & ~EN_VGA_PASSTHROUGH);
807 iprintk("Disabling VGA pass-through\n");
808 } else {
809 sst_write(FBIINIT0, fbiinit0 | EN_VGA_PASSTHROUGH);
810 iprintk("Enabling VGA pass-through\n");
811 }
812 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp);
813 return 0;
814
815 /* draw test image */
816 case _IO('F', 0xde): /* 0x46de */
817 f_dprintk("test color display at %d bpp\n",
818 info->var.bits_per_pixel);
819 sstfb_drawdebugimage(info);
820 return 0;
821 }
822 return -EINVAL;
823}
824
825
826/*
827 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only
828 */
829#if 0
830static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
831{
7227576f 832 struct sstfb_par *par = info->par;
1da177e4
LT		 833 u32 stride = info->fix.line_length;
834
835 if (!IS_VOODOO2(par))
836 return;
837
838 sst_write(BLTSRCBASEADDR, 0);
839 sst_write(BLTDSTBASEADDR, 0);
840 sst_write(BLTROP, BLTROP_COPY);
841 sst_write(BLTXYSTRIDES, stride | (stride << 16));
842 sst_write(BLTSRCXY, area->sx | (area->sy << 16));
843 sst_write(BLTDSTXY, area->dx | (area->dy << 16));
844 sst_write(BLTSIZE, area->width | (area->height << 16));
845 sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT |
846 (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) );
847 sst_wait_idle();
848}
849#endif
850
851
852/*
853 * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only
854 */
855static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
856{
7227576f 857 struct sstfb_par *par = info->par;
1da177e4
LT		 858 u32 stride = info->fix.line_length;
859
860 if (!IS_VOODOO2(par))
861 return;
862
863 sst_write(BLTCLIPX, info->var.xres);
864 sst_write(BLTCLIPY, info->var.yres);
865
866 sst_write(BLTDSTBASEADDR, 0);
867 sst_write(BLTCOLOR, rect->color);
868 sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR);
869 sst_write(BLTXYSTRIDES, stride | (stride << 16));
870 sst_write(BLTDSTXY, rect->dx | (rect->dy << 16));
871 sst_write(BLTSIZE, rect->width | (rect->height << 16));
872 sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT
873 | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) );
874 sst_wait_idle();
875}
876
877
878
879/*
880 * get lfb size
881 */
882static int __devinit sst_get_memsize(struct fb_info *info, __u32 *memsize)
883{
884 u8 __iomem *fbbase_virt = info->screen_base;
885
886 /* force memsize */
887 if ((mem >= 1 ) && (mem <= 4)) {
888 *memsize = (mem * 0x100000);
889 iprintk("supplied memsize: %#x\n", *memsize);
890 return 1;
891 }
892
893 writel(0xdeadbeef, fbbase_virt);
894 writel(0xdeadbeef, fbbase_virt+0x100000);
895 writel(0xdeadbeef, fbbase_virt+0x200000);
896 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
897 readl(fbbase_virt), readl(fbbase_virt + 0x100000),
898 readl(fbbase_virt + 0x200000));
899
900 writel(0xabcdef01, fbbase_virt);
901
902 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
903 readl(fbbase_virt), readl(fbbase_virt + 0x100000),
904 readl(fbbase_virt + 0x200000));
905
906 /* checks for 4mb lfb, then 2, then defaults to 1 */
907 if (readl(fbbase_virt + 0x200000) == 0xdeadbeef)
908 *memsize = 0x400000;
909 else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef)
910 *memsize = 0x200000;
911 else
912 *memsize = 0x100000;
913 f_ddprintk("detected memsize: %dMB\n", *memsize >> 20);
914 return 1;
915}
916
917
918/*
919 * DAC detection routines
920 */
921
922/* fbi should be idle, and fifo emty and mem disabled */
923/* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */
924
925static int __devinit sst_detect_att(struct fb_info *info)
926{
7227576f 927 struct sstfb_par *par = info->par;
1da177e4
LT		 928 int i, mir, dir;
929
930 for (i=0; i<3; i++) {
931 sst_dac_write(DACREG_WMA, 0); /* backdoor */
932 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
933 sst_dac_read(DACREG_RMR);
934 sst_dac_read(DACREG_RMR);
935 sst_dac_read(DACREG_RMR);
936 /* the fifth time, CR0 is read */
937 sst_dac_read(DACREG_RMR);
938 /* the 6th, manufacturer id register */
939 mir = sst_dac_read(DACREG_RMR);
940 /*the 7th, device ID register */
941 dir = sst_dac_read(DACREG_RMR);
942 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
943 if ((mir == DACREG_MIR_ATT ) && (dir == DACREG_DIR_ATT)) {
944 return 1;
945 }
946 }
947 return 0;
948}
949
950static int __devinit sst_detect_ti(struct fb_info *info)
951{
7227576f 952 struct sstfb_par *par = info->par;
1da177e4
LT		 953 int i, mir, dir;
954
955 for (i = 0; i<3; i++) {
956 sst_dac_write(DACREG_WMA, 0); /* backdoor */
957 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
958 sst_dac_read(DACREG_RMR);
959 sst_dac_read(DACREG_RMR);
960 sst_dac_read(DACREG_RMR);
961 /* the fifth time, CR0 is read */
962 sst_dac_read(DACREG_RMR);
963 /* the 6th, manufacturer id register */
964 mir = sst_dac_read(DACREG_RMR);
965 /*the 7th, device ID register */
966 dir = sst_dac_read(DACREG_RMR);
967 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
968 if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) {
969 return 1;
970 }
971 }
972 return 0;
973}
974
975/*
976 * try to detect ICS5342 ramdac
977 * we get the 1st byte (M value) of preset f1,f7 and fB
978 * why those 3 ? mmmh... for now, i'll do it the glide way...
979 * and ask questions later. anyway, it seems that all the freq registers are
980 * realy at their default state (cf specs) so i ask again, why those 3 regs ?
981 * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for
982 * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be
983 * touched...
984 * is it realy safe ? how can i reset this ramdac ? geee...
985 */
986static int __devinit sst_detect_ics(struct fb_info *info)
987{
7227576f 988 struct sstfb_par *par = info->par;
1da177e4
LT		 989 int m_clk0_1, m_clk0_7, m_clk1_b;
990 int n_clk0_1, n_clk0_7, n_clk1_b;
991 int i;
992
993 for (i = 0; i<5; i++ ) {
994 sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */
995 m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
996 n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
997 sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */
998 m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
999 n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
1000 sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */
1001 m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
1002 n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
1003 f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n",
1004 m_clk0_1, m_clk0_7, m_clk1_b);
1005 f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n",
1006 n_clk0_1, n_clk0_7, n_clk1_b);
1007 if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI)
1008 && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI)
1009 && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) {
1010 return 1;
1011 }
1012 }
1013 return 0;
1014}
1015
1016
1017/*
1018 * gfx, video, pci fifo should be reset, dram refresh disabled
1019 * see detect_dac
1020 */
1021
1022static int sst_set_pll_att_ti(struct fb_info *info,
1023 const struct pll_timing *t, const int clock)
1024{
7227576f 1025 struct sstfb_par *par = info->par;
1da177e4
LT		 1026 u8 cr0, cc;
1027
1028 /* enable indexed mode */
1029 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1030 sst_dac_read(DACREG_RMR); /* 1 time: RMR */
1031 sst_dac_read(DACREG_RMR); /* 2 RMR */
1032 sst_dac_read(DACREG_RMR); /* 3 // */
1033 sst_dac_read(DACREG_RMR); /* 4 // */
1034 cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */
1035
1036 sst_dac_write(DACREG_WMA, 0);
1037 sst_dac_read(DACREG_RMR);
1038 sst_dac_read(DACREG_RMR);
1039 sst_dac_read(DACREG_RMR);
1040 sst_dac_read(DACREG_RMR);
1041 sst_dac_write(DACREG_RMR, (cr0 & 0xf0)
1042 | DACREG_CR0_EN_INDEXED
1043 | DACREG_CR0_8BIT
1044 | DACREG_CR0_PWDOWN );
1045 /* so, now we are in indexed mode . dunno if its common, but
1046 i find this way of doing things a little bit weird :p */
1047
1048 udelay(300);
1049 cc = dac_i_read(DACREG_CC_I);
1050 switch (clock) {
1051 case VID_CLOCK:
1052 dac_i_write(DACREG_AC0_I, t->m);
1053 dac_i_write(DACREG_AC1_I, t->p << 6 | t->n);
1054 dac_i_write(DACREG_CC_I,
1055 (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C);
1056 break;
1057 case GFX_CLOCK:
1058 dac_i_write(DACREG_BD0_I, t->m);
1059 dac_i_write(DACREG_BD1_I, t->p << 6 | t->n);
1060 dac_i_write(DACREG_CC_I,
1061 (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D);
1062 break;
1063 default:
1064 dprintk("%s: wrong clock code '%d'\n",
1065 __FUNCTION__, clock);
1066 return 0;
1067 }
1068 udelay(300);
1069
1070 /* power up the dac & return to "normal" non-indexed mode */
1071 dac_i_write(DACREG_CR0_I,
1072 cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED);
1073 return 1;
1074}
1075
1076static int sst_set_pll_ics(struct fb_info *info,
1077 const struct pll_timing *t, const int clock)
1078{
7227576f 1079 struct sstfb_par *par = info->par;
1da177e4
LT		 1080 u8 pll_ctrl;
1081
1082 sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL);
1083 pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA);
1084 switch(clock) {
1085 case VID_CLOCK:
1086 sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */
1087 sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1088 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1089 /* selects freq f0 for clock 0 */
1090 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1091 sst_dac_write(DACREG_ICS_PLLDATA,
1092 (pll_ctrl & 0xd8)
1093 | DACREG_ICS_CLK0
1094 | DACREG_ICS_CLK0_0);
1095 break;
1096 case GFX_CLOCK :
1097 sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */
1098 sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1099 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1100 /* selects freq fA for clock 1 */
1101 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1102 sst_dac_write(DACREG_ICS_PLLDATA,
1103 (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A);
1104 break;
1105 default:
1106 dprintk("%s: wrong clock code '%d'\n",
1107 __FUNCTION__, clock);
1108 return 0;
1109 }
1110 udelay(300);
1111 return 1;
1112}
1113
1114static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp)
1115{
7227576f 1116 struct sstfb_par *par = info->par;
1da177e4
LT		 1117 u8 cr0;
1118
1119 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1120 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
1121 sst_dac_read(DACREG_RMR);
1122 sst_dac_read(DACREG_RMR);
1123 sst_dac_read(DACREG_RMR);
1124 /* the fifth time, CR0 is read */
1125 cr0 = sst_dac_read(DACREG_RMR);
1126
1127 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1128 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
1129 sst_dac_read(DACREG_RMR);
1130 sst_dac_read(DACREG_RMR);
1131 sst_dac_read(DACREG_RMR);
1132 /* cr0 */
1133 switch(bpp) {
1134 case 16:
1135 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
1136 break;
1137#ifdef EN_24_32_BPP
1138 case 24:
1139 case 32:
1140 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_24BPP);
1141 break;
1142#endif
1143 default:
1144 dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp);
1145 break;
1146 }
1147}
1148
1149static void sst_set_vidmod_ics(struct fb_info *info, const int bpp)
1150{
7227576f 1151 struct sstfb_par *par = info->par;
1da177e4
LT		 1152
1153 switch(bpp) {
1154 case 16:
1155 sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP);
1156 break;
1157#ifdef EN_24_32_BPP
1158 case 24:
1159 case 32:
1160 sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_24BPP);
1161 break;
1162#endif
1163 default:
1164 dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp);
1165 break;
1166 }
1167}
1168
1169/*
1170 * detect dac type
1171 * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset,
1172 * dram refresh disabled, FbiInit remaped.
1173 * TODO: mmh.. maybe i shoud put the "prerequisite" in the func ...
1174 */
1175
1176
1177static struct dac_switch dacs[] __devinitdata = {
1178 { .name = "TI TVP3409",
1179 .detect = sst_detect_ti,
1180 .set_pll = sst_set_pll_att_ti,
1181 .set_vidmod = sst_set_vidmod_att_ti },
1182
1183 { .name = "AT&T ATT20C409",
1184 .detect = sst_detect_att,
1185 .set_pll = sst_set_pll_att_ti,
1186 .set_vidmod = sst_set_vidmod_att_ti },
1187 { .name = "ICS ICS5342",
1188 .detect = sst_detect_ics,
1189 .set_pll = sst_set_pll_ics,
1190 .set_vidmod = sst_set_vidmod_ics },
1191};
1192
1193static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
1194{
1195 int i, ret = 0;
d1ae418e
TK		 1196
1197 for (i = 0; i < ARRAY_SIZE(dacs); i++) {
1da177e4 1198 ret = dacs[i].detect(info);
d1ae418e
TK		 1199 if (ret)
1200 break;
1da177e4
LT		 1201 }
1202 if (!ret)
1203 return 0;
1204 f_dprintk("%s found %s\n", __FUNCTION__, dacs[i].name);
1205 par->dac_sw = dacs[i];
1206 return 1;
1207}
1208
1209/*
1210 * Internal Routines
1211 */
1212static int __devinit sst_init(struct fb_info *info, struct sstfb_par *par)
1213{
1214 u32 fbiinit0, fbiinit1, fbiinit4;
1215 struct pci_dev *dev = par->dev;
1216 struct pll_timing gfx_timings;
1217 struct sst_spec *spec;
1218 int Fout;
1219
1220 spec = &voodoo_spec[par->type];
1221 f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 "
1222 " fbiinit6\n");
1223 f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n",
1224 sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2),
1225 sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6));
1226 /* disable video clock */
1227 pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0);
1228
1229 /* enable writing to init registers, disable pci fifo */
1230 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1231 /* reset video */
1232 sst_set_bits(FBIINIT1, VIDEO_RESET);
1233 sst_wait_idle();
1234 /* reset gfx + pci fifo */
1235 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1236 sst_wait_idle();
1237
1238 /* unreset fifo */
1239 /*sst_unset_bits(FBIINIT0, FIFO_RESET);
1240 sst_wait_idle();*/
1241 /* unreset FBI */
1242 /*sst_unset_bits(FBIINIT0, FBI_RESET);
1243 sst_wait_idle();*/
1244
1245 /* disable dram refresh */
1246 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1247 sst_wait_idle();
1248 /* remap fbinit2/3 to dac */
1249 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1250 PCI_EN_INIT_WR | PCI_REMAP_DAC );
1251 /* detect dac type */
1252 if (!sst_detect_dactype(info, par)) {
1253 eprintk("Unknown dac type\n");
1254 //FIXME watch it: we are not in a safe state, bad bad bad.
1255 return 0;
1256 }
1257
1258 /* set graphic clock */
1259 par->gfx_clock = spec->default_gfx_clock;
1260 if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) {
1261 iprintk("Using supplied graphic freq : %dMHz\n", gfxclk);
1262 par->gfx_clock = gfxclk *1000;
1263 } else if (gfxclk) {
1264 wprintk ("%dMhz is way out of spec! Using default\n", gfxclk);
1265 }
1266
1267 sst_calc_pll(par->gfx_clock, &Fout, &gfx_timings);
1268 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1269
1270 /* disable fbiinit remap */
1271 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1272 PCI_EN_INIT_WR| PCI_EN_FIFO_WR );
1273 /* defaults init registers */
1274 /* FbiInit0: unreset gfx, unreset fifo */
1275 fbiinit0 = FBIINIT0_DEFAULT;
1276 fbiinit1 = FBIINIT1_DEFAULT;
1277 fbiinit4 = FBIINIT4_DEFAULT;
1278 if (vgapass)
1279 fbiinit0 &= ~EN_VGA_PASSTHROUGH;
1280 else
1281 fbiinit0 |= EN_VGA_PASSTHROUGH;
1282 if (slowpci) {
1283 fbiinit1 |= SLOW_PCI_WRITES;
1284 fbiinit4 |= SLOW_PCI_READS;
1285 } else {
1286 fbiinit1 &= ~SLOW_PCI_WRITES;
1287 fbiinit4 &= ~SLOW_PCI_READS;
1288 }
1289 sst_write(FBIINIT0, fbiinit0);
1290 sst_wait_idle();
1291 sst_write(FBIINIT1, fbiinit1);
1292 sst_wait_idle();
1293 sst_write(FBIINIT2, FBIINIT2_DEFAULT);
1294 sst_wait_idle();
1295 sst_write(FBIINIT3, FBIINIT3_DEFAULT);
1296 sst_wait_idle();
1297 sst_write(FBIINIT4, fbiinit4);
1298 sst_wait_idle();
1299 if (IS_VOODOO2(par)) {
1300 sst_write(FBIINIT6, FBIINIT6_DEFAULT);
1301 sst_wait_idle();
1302 }
1303
1304 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
1305 pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0);
1306 return 1;
1307}
1308
1309static void __devexit sst_shutdown(struct fb_info *info)
1310{
7227576f 1311 struct sstfb_par *par = info->par;
1da177e4
LT		 1312 struct pci_dev *dev = par->dev;
1313 struct pll_timing gfx_timings;
1314 int Fout;
1315
1316 /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */
1317 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1318 sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING);
1319 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1320 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1321 sst_wait_idle();
1322 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1323 PCI_EN_INIT_WR | PCI_REMAP_DAC);
1324 /* set 20Mhz gfx clock */
1325 sst_calc_pll(20000, &Fout, &gfx_timings);
1326 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1327 /* TODO maybe shutdown the dac, vrefresh and so on... */
1328 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1329 PCI_EN_INIT_WR);
1330 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | EN_VGA_PASSTHROUGH);
1331 pci_write_config_dword(dev, PCI_VCLK_DISABLE,0);
1332 /* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct
1333 * from start ? */
1334 pci_write_config_dword(dev, PCI_INIT_ENABLE, 0);
1335
1336}
1337
1338/*
1339 * Interface to the world
1340 */
1341#ifndef MODULE
1342static int __init sstfb_setup(char *options)
1343{
1344 char *this_opt;
1345
1346 if (!options || !*options)
1347 return 0;
1348
1349 while ((this_opt = strsep(&options, ",")) != NULL) {
1350 if (!*this_opt) continue;
1351
1352 f_ddprintk("option %s\n", this_opt);
1353
1354 if (!strcmp(this_opt, "vganopass"))
1355 vgapass = 0;
1356 else if (!strcmp(this_opt, "vgapass"))
1357 vgapass = 1;
1358 else if (!strcmp(this_opt, "clipping"))
1359 clipping = 1;
1360 else if (!strcmp(this_opt, "noclipping"))
1361 clipping = 0;
1362 else if (!strcmp(this_opt, "fastpci"))
1363 slowpci = 0;
1364 else if (!strcmp(this_opt, "slowpci"))
1365 slowpci = 1;
1366 else if (!strncmp(this_opt, "mem:",4))
1367 mem = simple_strtoul (this_opt+4, NULL, 0);
1368 else if (!strncmp(this_opt, "gfxclk:",7))
1369 gfxclk = simple_strtoul (this_opt+7, NULL, 0);
1370 else
1371 mode_option = this_opt;
1372 }
1373 return 0;
1374}
1375#endif
1376
1377static struct fb_ops sstfb_ops = {
1378 .owner = THIS_MODULE,
1379 .fb_check_var = sstfb_check_var,
1380 .fb_set_par = sstfb_set_par,
1381 .fb_setcolreg = sstfb_setcolreg,
1382 .fb_fillrect = cfb_fillrect, /* sstfb_fillrect */
1383 .fb_copyarea = cfb_copyarea, /* sstfb_copyarea */
1384 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 1385 .fb_ioctl = sstfb_ioctl,
1386};
1387
1388static int __devinit sstfb_probe(struct pci_dev *pdev,
1389 const struct pci_device_id *id)
1390{
1391 struct fb_info *info;
1392 struct fb_fix_screeninfo *fix;
1393 struct sstfb_par *par;
1394 struct sst_spec *spec;
1395 int err;
1396
1da177e4
LT		 1397 /* Enable device in PCI config. */
1398 if ((err=pci_enable_device(pdev))) {
1399 eprintk("cannot enable device\n");
1400 return err;
1401 }
1402
1403 /* Allocate the fb and par structures. */
7227576f
AD		 1404 info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev);
1405 if (!info)
1da177e4 1406 return -ENOMEM;
7227576f
AD		 1407
1408 pci_set_drvdata(pdev, info);
1da177e4 1409
7227576f 1410 par = info->par;
1da177e4
LT		 1411 fix = &info->fix;
1412
1413 par->type = id->driver_data;
1414 spec = &voodoo_spec[par->type];
1415 f_ddprintk("found device : %s\n", spec->name);
1416
1417 par->dev = pdev;
1418 pci_read_config_byte(pdev, PCI_REVISION_ID, &par->revision);
1419
1420 fix->mmio_start = pci_resource_start(pdev,0);
1421 fix->mmio_len = 0x400000;
1422 fix->smem_start = fix->mmio_start + 0x400000;
1423
1424 if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) {
1425 eprintk("cannot reserve mmio memory\n");
1426 goto fail_mmio_mem;
1427 }
1428
1429 if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) {
1430 eprintk("cannot reserve fb memory\n");
1431 goto fail_fb_mem;
1432 }
1433
1434 par->mmio_vbase = ioremap_nocache(fix->mmio_start,
1435 fix->mmio_len);
1436 if (!par->mmio_vbase) {
1437 eprintk("cannot remap register area %#lx\n",
1438 fix->mmio_start);
1439 goto fail_mmio_remap;
1440 }
1441 info->screen_base = ioremap_nocache(fix->smem_start, 0x400000);
1442 if (!info->screen_base) {
1443 eprintk("cannot remap framebuffer %#lx\n",
1444 fix->smem_start);
1445 goto fail_fb_remap;
1446 }
1447
1448 if (!sst_init(info, par)) {
1449 eprintk("Init failed\n");
1450 goto fail;
1451 }
1452 sst_get_memsize(info, &fix->smem_len);
1453 strlcpy(fix->id, spec->name, sizeof(fix->id));
1454
1455 iprintk("%s (revision %d) with %s dac\n",
1456 fix->id, par->revision, par->dac_sw.name);
1457 iprintk("framebuffer at %#lx, mapped to 0x%p, size %dMB\n",
1458 fix->smem_start, info->screen_base,
1459 fix->smem_len >> 20);
1460
1461 f_ddprintk("regbase_virt: %#lx\n", par->mmio_vbase);
1462 f_ddprintk("membase_phys: %#lx\n", fix->smem_start);
1463 f_ddprintk("fbbase_virt: %p\n", info->screen_base);
1464
1465 info->flags = FBINFO_DEFAULT;
1466 info->fbops = &sstfb_ops;
7227576f 1467 info->pseudo_palette = par->palette;
1da177e4
LT		 1468
1469 fix->type = FB_TYPE_PACKED_PIXELS;
1470 fix->visual = FB_VISUAL_TRUECOLOR;
1471 fix->accel = FB_ACCEL_NONE; /* FIXME */
1472 /*
1473 * According to the specs, the linelength must be of 1024 *pixels*
1474 * and the 24bpp mode is in fact a 32 bpp mode.
1475 */
1476 fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */
1477
1478 if ( mode_option &&
1479 fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16)) {
1480 eprintk("can't set supplied video mode. Using default\n");
1481 info->var = sstfb_default;
1482 } else
1483 info->var = sstfb_default;
1484
1485 if (sstfb_check_var(&info->var, info)) {
1486 eprintk("invalid default video mode.\n");
1487 goto fail;
1488 }
1489
1490 if (sstfb_set_par(info)) {
1491 eprintk("can't set default video mode.\n");
1492 goto fail;
1493 }
1494
1495 fb_alloc_cmap(&info->cmap, 256, 0);
1496
1497 /* register fb */
1498 info->device = &pdev->dev;
1499 if (register_framebuffer(info) < 0) {
1500 eprintk("can't register framebuffer.\n");
1501 goto fail;
1502 }
1503
1504 if (1) /* set to 0 to see an initial bitmap instead */
1505 sstfb_clear_screen(info);
1506 else
1507 sstfb_drawdebugimage(info);
1508
1509 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%p\n",
1510 info->node, fix->id, info->screen_base);
1511
1512 return 0;
1513
1514fail:
1515 iounmap(info->screen_base);
1516fail_fb_remap:
1517 iounmap(par->mmio_vbase);
1518fail_mmio_remap:
1519 release_mem_region(fix->smem_start, 0x400000);
1520fail_fb_mem:
1521 release_mem_region(fix->mmio_start, info->fix.mmio_len);
1522fail_mmio_mem:
7227576f 1523 framebuffer_release(info);
1da177e4
LT		 1524 return -ENXIO; /* no voodoo detected */
1525}
1526
1527static void __devexit sstfb_remove(struct pci_dev *pdev)
1528{
1529 struct sstfb_par *par;
1530 struct fb_info *info;
1531
1532 info = pci_get_drvdata(pdev);
7227576f 1533 par = info->par;
1da177e4
LT		 1534
1535 sst_shutdown(info);
1536 unregister_framebuffer(info);
1537 iounmap(info->screen_base);
1538 iounmap(par->mmio_vbase);
1539 release_mem_region(info->fix.smem_start, 0x400000);
1540 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
7227576f 1541 framebuffer_release(info);
1da177e4
LT		 1542}
1543
1544
1545static struct pci_device_id sstfb_id_tbl[] = {
1546 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO,
1547 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_VOODOO1 },
1548 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2,
1549 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_VOODOO2 },
1550 { 0 },
1551};
1552
1553static struct pci_driver sstfb_driver = {
1554 .name = "sstfb",
1555 .id_table = sstfb_id_tbl,
1556 .probe = sstfb_probe,
1557 .remove = __devexit_p(sstfb_remove),
1558};
1559
1560
1561static int __devinit sstfb_init(void)
1562{
1563#ifndef MODULE
1564 char *option = NULL;
1565
1566 if (fb_get_options("sstfb", &option))
1567 return -ENODEV;
1568 sstfb_setup(option);
1569#endif
1570 return pci_register_driver(&sstfb_driver);
1571}
1572
1573#ifdef MODULE
1574static void __devexit sstfb_exit(void)
1575{
1576 pci_unregister_driver(&sstfb_driver);
1577}
1578#endif
1579
1580
1581/*
1582 * testing and debugging functions
1583 */
1584
1585static int sstfb_dump_regs(struct fb_info *info)
1586{
1587#ifdef SST_DEBUG
1588 static struct { u32 reg ; const char *reg_name;} pci_regs[] = {
1589 { PCI_INIT_ENABLE, "initenable"},
1590 { PCI_VCLK_ENABLE, "enable vclk"},
1591 { PCI_VCLK_DISABLE, "disable vclk"},
1592 };
1593
1594 static struct { u32 reg ; const char *reg_name;} sst_regs[] = {
1595 {FBIINIT0,"fbiinit0"},
1596 {FBIINIT1,"fbiinit1"},
1597 {FBIINIT2,"fbiinit2"},
1598 {FBIINIT3,"fbiinit3"},
1599 {FBIINIT4,"fbiinit4"},
1600 {FBIINIT5,"fbiinit5"},
1601 {FBIINIT6,"fbiinit6"},
1602 {FBIINIT7,"fbiinit7"},
1603 {LFBMODE,"lfbmode"},
1604 {FBZMODE,"fbzmode"},
1605 };
1606
d1ae418e
TK		 1607 const int pci_s = ARRAY_SIZE(pci_regs);
1608 const int sst_s = ARRAY_SIZE(sst_regs);
7227576f 1609 struct sstfb_par *par = info->par;
1da177e4
LT		 1610 struct pci_dev *dev = par->dev;
1611 u32 pci_res[pci_s];
1612 u32 sst_res[sst_s];
1613 int i;
1614
1615 for (i=0; i<pci_s; i++) {
1616 pci_read_config_dword(dev, pci_regs[i].reg, &pci_res[i]);
1617 }
1618 for (i=0; i<sst_s; i++) {
1619 sst_res[i] = sst_read(sst_regs[i].reg);
1620 }
1621
1622 dprintk("hardware register dump:\n");
1623 for (i=0; i<pci_s; i++) {
1624 dprintk("%s %0#10x\n", pci_regs[i].reg_name, pci_res[i]);
1625 }
1626 for (i=0; i<sst_s; i++) {
1627 dprintk("%s %0#10x\n", sst_regs[i].reg_name, sst_res[i]);
1628 }
1629 return 0;
1630#else
1631 return -EINVAL;
1632#endif
1633}
1634
1635static void sstfb_fillrect_softw( struct fb_info *info, const struct fb_fillrect *rect)
1636{
1637 u8 __iomem *fbbase_virt = info->screen_base;
1638 int x, y, w = info->var.bits_per_pixel == 16 ? 2 : 4;
1639 u32 color = rect->color, height = rect->height;
1640 u8 __iomem *p;
1641
1642 if (w==2) color |= color<<16;
1643 for (y=rect->dy; height; y++, height--) {
1644 p = fbbase_virt + y*info->fix.line_length + rect->dx*w;
1645 x = rect->width;
1646 if (w==2) x>>=1;
1647 while (x) {
1648 writel(color, p);
1649 p += 4;
1650 x--;
1651 }
1652 }
1653}
1654
1655static void sstfb_drawrect_XY( struct fb_info *info, int x, int y,
1656 int w, int h, int color, int hwfunc)
1657{
1658 struct fb_fillrect rect;
1659 rect.dx = x;
1660 rect.dy = y;
1661 rect.height = h;
1662 rect.width = w;
1663 rect.color = color;
1664 rect.rop = ROP_COPY;
1665 if (hwfunc)
1666 sstfb_fillrect(info, &rect);
1667 else
1668 sstfb_fillrect_softw(info, &rect);
1669}
1670
1671/* print some squares on the fb */
1672static void sstfb_drawdebugimage(struct fb_info *info)
1673{
1674 static int idx;
1675
1676 /* clear screen */
1677 sstfb_clear_screen(info);
1678
1679 idx = (idx+1) & 1;
1680
1681 /* white rect */
1682 sstfb_drawrect_XY(info, 0, 0, 50, 50, 0xffff, idx);
1683
1684 /* blue rect */
1685 sstfb_drawrect_XY(info, 50, 50, 50, 50, 0x001f, idx);
1686
1687 /* green rect */
1688 sstfb_drawrect_XY(info, 100, 100, 80, 80, 0x07e0, idx);
1689
1690 /* red rect */
1691 sstfb_drawrect_XY(info, 250, 250, 120, 100, 0xf800, idx);
1692}
1693
1694module_init(sstfb_init);
1695
1696#ifdef MODULE
1697module_exit(sstfb_exit);
1698#endif
1699
1700MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>");
1701MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards");
1702MODULE_LICENSE("GPL");
1703
1704module_param(mem, int, 0);
1705MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)");
1706module_param(vgapass, bool, 0);
1707MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)");
1708module_param(clipping, bool, 0);
1709MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)");
1710module_param(gfxclk, int, 0);
1711MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
1712module_param(slowpci, bool, 0);
1713MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)");
1714
Linux 6.x block layer and io_uring tree(s)