Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer | |
3 | * | |
4 | * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net> | |
5 | * | |
6 | * Created 15 Jan 2000 by Ghozlane Toumi | |
7 | * | |
8 | * Contributions (and many thanks) : | |
9 | * | |
10 | * 03/2001 James Simmons <jsimmons@infradead.org> | |
11 | * 04/2001 Paul Mundt <lethal@chaoticdreams.org> | |
12 | * 05/2001 Urs Ganse <ursg@uni.de> | |
13 | * (initial work on voodoo2 port, interlace) | |
14 | * 09/2002 Helge Deller <deller@gmx.de> | |
15 | * (enable driver on big-endian machines (hppa), ioctl fixes) | |
16 | * 12/2002 Helge Deller <deller@gmx.de> | |
17 | * (port driver to new frambuffer infrastructure) | |
18 | * 01/2003 Helge Deller <deller@gmx.de> | |
19 | * (initial work on fb hardware acceleration for voodoo2) | |
b98fc9a3 AC |
20 | * 08/2006 Alan Cox <alan@redhat.com> |
21 | * Remove never finished and bogus 24/32bit support | |
22 | * Clean up macro abuse | |
23 | * Minor tidying for format. | |
1da177e4 LT |
24 | */ |
25 | ||
26 | /* | |
27 | * The voodoo1 has the following memory mapped address space: | |
28 | * 0x000000 - 0x3fffff : registers (4MB) | |
29 | * 0x400000 - 0x7fffff : linear frame buffer (4MB) | |
30 | * 0x800000 - 0xffffff : texture memory (8MB) | |
31 | */ | |
32 | ||
33 | /* | |
34 | * misc notes, TODOs, toASKs, and deep thoughts | |
35 | ||
36 | -TODO: at one time or another test that the mode is acceptable by the monitor | |
37 | -ASK: Can I choose different ordering for the color bitfields (rgba argb ...) | |
c30fe7f7 | 38 | which one should i use ? is there any preferred one ? It seems ARGB is |
1da177e4 LT |
39 | the one ... |
40 | -TODO: in set_var check the validity of timings (hsync vsync)... | |
41 | -TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via | |
42 | a nop command. so it's ok as long as the commands we pass don't go | |
43 | through the fifo. warning: issuing a nop command seems to need pci_fifo | |
44 | -FIXME: in case of failure in the init sequence, be sure we return to a safe | |
45 | state. | |
b98fc9a3 | 46 | - FIXME: Use accelerator for 2D scroll |
1da177e4 LT |
47 | -FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20) |
48 | */ | |
49 | ||
50 | /* | |
51 | * debug info | |
52 | * SST_DEBUG : enable debugging | |
53 | * SST_DEBUG_REG : debug registers | |
54 | * 0 : no debug | |
55 | * 1 : dac calls, [un]set_bits, FbiInit | |
56 | * 2 : insane debug level (log every register read/write) | |
57 | * SST_DEBUG_FUNC : functions | |
58 | * 0 : no debug | |
59 | * 1 : function call / debug ioctl | |
60 | * 2 : variables | |
61 | * 3 : flood . you don't want to do that. trust me. | |
62 | * SST_DEBUG_VAR : debug display/var structs | |
63 | * 0 : no debug | |
64 | * 1 : dumps display, fb_var | |
65 | * | |
66 | * sstfb specific ioctls: | |
67 | * toggle vga (0x46db) : toggle vga_pass_through | |
68 | * fill fb (0x46dc) : fills fb | |
69 | * test disp (0x46de) : draws a test image | |
70 | */ | |
71 | ||
72 | #undef SST_DEBUG | |
73 | ||
1da177e4 LT |
74 | /* |
75 | Default video mode . | |
76 | 0 800x600@60 took from glide | |
77 | 1 640x480@75 took from glide | |
78 | 2 1024x768@76 std fb.mode | |
79 | 3 640x480@60 glide default */ | |
80 | #define DEFAULT_MODE 3 | |
81 | ||
82 | /* | |
83 | * Includes | |
84 | */ | |
85 | ||
1da177e4 LT |
86 | #include <linux/string.h> |
87 | #include <linux/kernel.h> | |
88 | #include <linux/module.h> | |
89 | #include <linux/fb.h> | |
90 | #include <linux/pci.h> | |
91 | #include <linux/delay.h> | |
92 | #include <linux/init.h> | |
93 | #include <linux/slab.h> | |
94 | #include <asm/io.h> | |
95 | #include <asm/ioctl.h> | |
96 | #include <asm/uaccess.h> | |
97 | #include <video/sstfb.h> | |
98 | ||
99 | ||
100 | /* initialized by setup */ | |
101 | ||
102 | static int vgapass; /* enable Vga passthrough cable */ | |
103 | static int mem; /* mem size in MB, 0 = autodetect */ | |
104 | static int clipping = 1; /* use clipping (slower, safer) */ | |
105 | static int gfxclk; /* force FBI freq in Mhz . Dangerous */ | |
106 | static int slowpci; /* slow PCI settings */ | |
107 | ||
108 | static char *mode_option __devinitdata; | |
109 | ||
110 | enum { | |
111 | ID_VOODOO1 = 0, | |
112 | ID_VOODOO2 = 1, | |
113 | }; | |
114 | ||
115 | #define IS_VOODOO2(par) ((par)->type == ID_VOODOO2) | |
116 | ||
117 | static struct sst_spec voodoo_spec[] __devinitdata = { | |
118 | { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 }, | |
119 | { .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 }, | |
120 | }; | |
121 | ||
122 | static struct fb_var_screeninfo sstfb_default = | |
123 | #if ( DEFAULT_MODE == 0 ) | |
124 | { /* 800x600@60, 16 bpp .borowed from glide/sst1/include/sst1init.h */ | |
125 | 800, 600, 800, 600, 0, 0, 16, 0, | |
126 | {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, | |
127 | 0, 0, -1, -1, 0, | |
128 | 25000, 86, 41, 23, 1, 127, 4, | |
129 | 0, FB_VMODE_NONINTERLACED }; | |
130 | #elif ( DEFAULT_MODE == 1 ) | |
131 | {/* 640x480@75, 16 bpp .borowed from glide/sst1/include/sst1init.h */ | |
132 | 640, 480, 640, 480, 0, 0, 16, 0, | |
133 | {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, | |
134 | 0, 0, -1, -1, 0, | |
135 | 31746, 118, 17, 16, 1, 63, 3, | |
136 | 0, FB_VMODE_NONINTERLACED }; | |
137 | #elif ( DEFAULT_MODE == 2 ) | |
138 | { /* 1024x768@76 took from my /etc/fb.modes */ | |
139 | 1024, 768, 1024, 768,0, 0, 16,0, | |
140 | {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, | |
141 | 0, 0, -1, -1, 0, | |
142 | 11764, 208, 8, 36, 16, 120, 3 , | |
143 | 0, FB_VMODE_NONINTERLACED }; | |
144 | #elif ( DEFAULT_MODE == 3 ) | |
145 | { /* 640x480@60 , 16bpp glide default ?*/ | |
146 | 640, 480, 640, 480, 0, 0, 16, 0, | |
147 | {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, | |
148 | 0, 0, -1, -1, 0, | |
149 | 39721 , 38, 26 , 25 ,18 , 96 ,2, | |
150 | 0, FB_VMODE_NONINTERLACED }; | |
151 | #elif | |
152 | #error "Invalid DEFAULT_MODE value !" | |
153 | #endif | |
154 | ||
155 | ||
156 | /* | |
157 | * debug functions | |
158 | */ | |
159 | ||
160 | static void sstfb_drawdebugimage(struct fb_info *info); | |
161 | static int sstfb_dump_regs(struct fb_info *info); | |
162 | ||
163 | ||
164 | #if (SST_DEBUG_REG > 0) | |
165 | static void sst_dbg_print_read_reg(u32 reg, u32 val) { | |
166 | const char *regname; | |
167 | switch (reg) { | |
168 | case FBIINIT0: regname = "FbiInit0"; break; | |
169 | case FBIINIT1: regname = "FbiInit1"; break; | |
170 | case FBIINIT2: regname = "FbiInit2"; break; | |
171 | case FBIINIT3: regname = "FbiInit3"; break; | |
172 | case FBIINIT4: regname = "FbiInit4"; break; | |
173 | case FBIINIT5: regname = "FbiInit5"; break; | |
174 | case FBIINIT6: regname = "FbiInit6"; break; | |
175 | default: regname = NULL; break; | |
176 | } | |
177 | if (regname == NULL) | |
178 | r_ddprintk("sst_read(%#x): %#x\n", reg, val); | |
179 | else | |
180 | r_dprintk(" sst_read(%s): %#x\n", regname, val); | |
181 | } | |
182 | ||
183 | static void sst_dbg_print_write_reg(u32 reg, u32 val) { | |
184 | const char *regname; | |
185 | switch (reg) { | |
186 | case FBIINIT0: regname = "FbiInit0"; break; | |
187 | case FBIINIT1: regname = "FbiInit1"; break; | |
188 | case FBIINIT2: regname = "FbiInit2"; break; | |
189 | case FBIINIT3: regname = "FbiInit3"; break; | |
190 | case FBIINIT4: regname = "FbiInit4"; break; | |
191 | case FBIINIT5: regname = "FbiInit5"; break; | |
192 | case FBIINIT6: regname = "FbiInit6"; break; | |
193 | default: regname = NULL; break; | |
194 | } | |
195 | if (regname == NULL) | |
196 | r_ddprintk("sst_write(%#x, %#x)\n", reg, val); | |
197 | else | |
198 | r_dprintk(" sst_write(%s, %#x)\n", regname, val); | |
199 | } | |
200 | #else /* (SST_DEBUG_REG > 0) */ | |
201 | # define sst_dbg_print_read_reg(reg, val) do {} while(0) | |
202 | # define sst_dbg_print_write_reg(reg, val) do {} while(0) | |
203 | #endif /* (SST_DEBUG_REG > 0) */ | |
204 | ||
205 | /* | |
206 | * hardware access functions | |
207 | */ | |
208 | ||
209 | /* register access */ | |
210 | #define sst_read(reg) __sst_read(par->mmio_vbase, reg) | |
211 | #define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val) | |
212 | #define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val) | |
213 | #define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val) | |
214 | #define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg) | |
215 | #define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val) | |
216 | #define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg) | |
217 | #define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val) | |
218 | ||
219 | static inline u32 __sst_read(u8 __iomem *vbase, u32 reg) | |
220 | { | |
221 | u32 ret = readl(vbase + reg); | |
222 | sst_dbg_print_read_reg(reg, ret); | |
223 | return ret; | |
224 | } | |
225 | ||
226 | static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val) | |
227 | { | |
228 | sst_dbg_print_write_reg(reg, val); | |
229 | writel(val, vbase + reg); | |
230 | } | |
231 | ||
232 | static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val) | |
233 | { | |
234 | r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val); | |
235 | __sst_write(vbase, reg, __sst_read(vbase, reg) | val); | |
236 | } | |
237 | ||
238 | static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val) | |
239 | { | |
240 | r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val); | |
241 | __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val); | |
242 | } | |
243 | ||
244 | /* | |
245 | * wait for the fbi chip. ASK: what happens if the fbi is stuck ? | |
246 | * | |
247 | * the FBI is supposed to be ready if we receive 5 time | |
248 | * in a row a "idle" answer to our requests | |
249 | */ | |
250 | ||
251 | #define sst_wait_idle() __sst_wait_idle(par->mmio_vbase) | |
252 | ||
253 | static int __sst_wait_idle(u8 __iomem *vbase) | |
254 | { | |
255 | int count = 0; | |
256 | ||
257 | /* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */ | |
258 | ||
259 | while(1) { | |
260 | if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) { | |
261 | f_dddprintk("status: busy\n"); | |
262 | /* FIXME basicaly, this is a busy wait. maybe not that good. oh well; | |
263 | * this is a small loop after all. | |
264 | * Or maybe we should use mdelay() or udelay() here instead ? */ | |
265 | count = 0; | |
266 | } else { | |
267 | count++; | |
268 | f_dddprintk("status: idle(%d)\n", count); | |
269 | } | |
270 | if (count >= 5) return 1; | |
271 | /* XXX do something to avoid hanging the machine if the voodoo is out */ | |
272 | } | |
273 | } | |
274 | ||
275 | ||
276 | /* dac access */ | |
277 | /* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */ | |
278 | static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg) | |
279 | { | |
280 | u8 ret; | |
281 | ||
282 | reg &= 0x07; | |
283 | __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD ); | |
284 | __sst_wait_idle(vbase); | |
285 | /* udelay(10); */ | |
286 | ret = __sst_read(vbase, DAC_READ) & 0xff; | |
287 | r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret); | |
288 | ||
289 | return ret; | |
290 | } | |
291 | ||
292 | static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val) | |
293 | { | |
294 | r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val); | |
295 | reg &= 0x07; | |
296 | __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val); | |
297 | } | |
298 | ||
299 | /* indexed access to ti/att dacs */ | |
300 | static u32 __dac_i_read(u8 __iomem *vbase, u8 reg) | |
301 | { | |
302 | u32 ret; | |
303 | ||
304 | __sst_dac_write(vbase, DACREG_ADDR_I, reg); | |
305 | ret = __sst_dac_read(vbase, DACREG_DATA_I); | |
306 | r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret); | |
307 | return ret; | |
308 | } | |
309 | static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val) | |
310 | { | |
311 | r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val); | |
312 | __sst_dac_write(vbase, DACREG_ADDR_I, reg); | |
313 | __sst_dac_write(vbase, DACREG_DATA_I, val); | |
314 | } | |
315 | ||
316 | /* compute the m,n,p , returns the real freq | |
317 | * (ics datasheet : N <-> N1 , P <-> N2) | |
318 | * | |
319 | * Fout= Fref * (M+2)/( 2^P * (N+2)) | |
320 | * we try to get close to the asked freq | |
321 | * with P as high, and M as low as possible | |
322 | * range: | |
323 | * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63 | |
324 | * ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31 | |
325 | * we'll use the lowest limitation, should be precise enouth | |
326 | */ | |
327 | static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t) | |
328 | { | |
329 | int m, m2, n, p, best_err, fout; | |
330 | int best_n = -1; | |
331 | int best_m = -1; | |
332 | ||
333 | best_err = freq; | |
334 | p = 3; | |
335 | /* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/ | |
336 | while (((1 << p) * freq > VCO_MAX) && (p >= 0)) | |
337 | p--; | |
338 | if (p == -1) | |
339 | return -EINVAL; | |
340 | for (n = 1; n < 32; n++) { | |
341 | /* calc 2 * m so we can round it later*/ | |
342 | m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ; | |
343 | ||
344 | m = (m2 % 2 ) ? m2/2+1 : m2/2 ; | |
345 | if (m >= 128) | |
346 | break; | |
347 | fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2)); | |
348 | if ((abs(fout - freq) < best_err) && (m > 0)) { | |
349 | best_n = n; | |
350 | best_m = m; | |
351 | best_err = abs(fout - freq); | |
352 | /* we get the lowest m , allowing 0.5% error in freq*/ | |
353 | if (200*best_err < freq) break; | |
354 | } | |
355 | } | |
356 | if (best_n == -1) /* unlikely, but who knows ? */ | |
357 | return -EINVAL; | |
358 | t->p = p; | |
359 | t->n = best_n; | |
360 | t->m = best_m; | |
361 | *freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2)); | |
362 | f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n", | |
363 | t->m, t->n, t->p, *freq_out); | |
364 | return 0; | |
365 | } | |
366 | ||
367 | /* | |
368 | * clear lfb screen | |
369 | */ | |
370 | static void sstfb_clear_screen(struct fb_info *info) | |
371 | { | |
372 | /* clear screen */ | |
373 | fb_memset(info->screen_base, 0, info->fix.smem_len); | |
374 | } | |
375 | ||
376 | ||
377 | /** | |
378 | * sstfb_check_var - Optional function. Validates a var passed in. | |
379 | * @var: frame buffer variable screen structure | |
380 | * @info: frame buffer structure that represents a single frame buffer | |
b98fc9a3 AC |
381 | * |
382 | * Limit to the abilities of a single chip as SLI is not supported | |
383 | * by this driver. | |
1da177e4 | 384 | */ |
b98fc9a3 | 385 | |
1da177e4 LT |
386 | static int sstfb_check_var(struct fb_var_screeninfo *var, |
387 | struct fb_info *info) | |
388 | { | |
7227576f | 389 | struct sstfb_par *par = info->par; |
1da177e4 LT |
390 | int hSyncOff = var->xres + var->right_margin + var->left_margin; |
391 | int vSyncOff = var->yres + var->lower_margin + var->upper_margin; | |
392 | int vBackPorch = var->left_margin, yDim = var->yres; | |
393 | int vSyncOn = var->vsync_len; | |
394 | int tiles_in_X, real_length; | |
395 | unsigned int freq; | |
396 | ||
397 | if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) { | |
b98fc9a3 | 398 | printk(KERN_ERR "sstfb: Pixclock at %ld KHZ out of range\n", |
1da177e4 LT |
399 | PICOS2KHZ(var->pixclock)); |
400 | return -EINVAL; | |
401 | } | |
402 | var->pixclock = KHZ2PICOS(freq); | |
403 | ||
404 | if (var->vmode & FB_VMODE_INTERLACED) | |
405 | vBackPorch += (vBackPorch % 2); | |
406 | if (var->vmode & FB_VMODE_DOUBLE) { | |
407 | vBackPorch <<= 1; | |
408 | yDim <<=1; | |
409 | vSyncOn <<=1; | |
410 | vSyncOff <<=1; | |
411 | } | |
412 | ||
413 | switch (var->bits_per_pixel) { | |
414 | case 0 ... 16 : | |
415 | var->bits_per_pixel = 16; | |
416 | break; | |
1da177e4 | 417 | default : |
b98fc9a3 | 418 | printk(KERN_ERR "sstfb: Unsupported bpp %d\n", var->bits_per_pixel); |
1da177e4 LT |
419 | return -EINVAL; |
420 | } | |
421 | ||
422 | /* validity tests */ | |
b98fc9a3 AC |
423 | if (var->xres <= 1 || yDim <= 0 || var->hsync_len <= 1 || |
424 | hSyncOff <= 1 || var->left_margin <= 2 || vSyncOn <= 0 || | |
425 | vSyncOff <= 0 || vBackPorch <= 0) { | |
1da177e4 LT |
426 | return -EINVAL; |
427 | } | |
428 | ||
429 | if (IS_VOODOO2(par)) { | |
430 | /* Voodoo 2 limits */ | |
431 | tiles_in_X = (var->xres + 63 ) / 64 * 2; | |
432 | ||
b98fc9a3 AC |
433 | if (var->xres > POW2(11) || yDim >= POW2(11)) { |
434 | printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n", | |
1da177e4 LT |
435 | var->xres, var->yres); |
436 | return -EINVAL; | |
437 | } | |
438 | ||
b98fc9a3 AC |
439 | if (var->hsync_len > POW2(9) || hSyncOff > POW2(11) || |
440 | var->left_margin - 2 >= POW2(9) || vSyncOn >= POW2(13) || | |
441 | vSyncOff >= POW2(13) || vBackPorch >= POW2(9) || | |
442 | tiles_in_X >= POW2(6) || tiles_in_X <= 0) { | |
443 | printk(KERN_ERR "sstfb: Unsupported timings\n"); | |
1da177e4 LT |
444 | return -EINVAL; |
445 | } | |
446 | } else { | |
447 | /* Voodoo limits */ | |
448 | tiles_in_X = (var->xres + 63 ) / 64; | |
449 | ||
450 | if (var->vmode) { | |
b98fc9a3 | 451 | printk(KERN_ERR "sstfb: Interlace/doublescan not supported %#x\n", |
1da177e4 LT |
452 | var->vmode); |
453 | return -EINVAL; | |
454 | } | |
b98fc9a3 AC |
455 | if (var->xres > POW2(10) || var->yres >= POW2(10)) { |
456 | printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n", | |
1da177e4 LT |
457 | var->xres, var->yres); |
458 | return -EINVAL; | |
459 | } | |
b98fc9a3 AC |
460 | if (var->hsync_len > POW2(8) || hSyncOff - 1 > POW2(10) || |
461 | var->left_margin - 2 >= POW2(8) || vSyncOn >= POW2(12) || | |
462 | vSyncOff >= POW2(12) || vBackPorch >= POW2(8) || | |
463 | tiles_in_X >= POW2(4) || tiles_in_X <= 0) { | |
464 | printk(KERN_ERR "sstfb: Unsupported timings\n"); | |
1da177e4 LT |
465 | return -EINVAL; |
466 | } | |
467 | } | |
468 | ||
469 | /* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */ | |
470 | /* FIXME: i don't like this... looks wrong */ | |
471 | real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 ) | |
472 | * ((var->bits_per_pixel == 16) ? 2 : 4); | |
473 | ||
b98fc9a3 AC |
474 | if (real_length * yDim > info->fix.smem_len) { |
475 | printk(KERN_ERR "sstfb: Not enough video memory\n"); | |
1da177e4 LT |
476 | return -ENOMEM; |
477 | } | |
478 | ||
479 | var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT); | |
480 | var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE); | |
481 | var->xoffset = 0; | |
482 | var->yoffset = 0; | |
483 | var->height = -1; | |
484 | var->width = -1; | |
485 | ||
486 | /* | |
487 | * correct the color bit fields | |
488 | */ | |
489 | /* var->{red|green|blue}.msb_right = 0; */ | |
490 | ||
491 | switch (var->bits_per_pixel) { | |
492 | case 16: /* RGB 565 LfbMode 0 */ | |
493 | var->red.length = 5; | |
494 | var->green.length = 6; | |
495 | var->blue.length = 5; | |
496 | var->transp.length = 0; | |
497 | ||
498 | var->red.offset = 11; | |
499 | var->green.offset = 5; | |
500 | var->blue.offset = 0; | |
501 | var->transp.offset = 0; | |
502 | break; | |
1da177e4 LT |
503 | default: |
504 | return -EINVAL; | |
505 | } | |
506 | return 0; | |
507 | } | |
508 | ||
509 | /** | |
510 | * sstfb_set_par - Optional function. Alters the hardware state. | |
511 | * @info: frame buffer structure that represents a single frame buffer | |
512 | */ | |
513 | static int sstfb_set_par(struct fb_info *info) | |
514 | { | |
7227576f | 515 | struct sstfb_par *par = info->par; |
1da177e4 LT |
516 | u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0; |
517 | struct pci_dev *sst_dev = par->dev; | |
518 | unsigned int freq; | |
519 | int ntiles; | |
520 | ||
521 | par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin; | |
522 | ||
523 | par->yDim = info->var.yres; | |
524 | par->vSyncOn = info->var.vsync_len; | |
525 | par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin; | |
526 | par->vBackPorch = info->var.upper_margin; | |
527 | ||
528 | /* We need par->pll */ | |
529 | sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll); | |
530 | ||
531 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
532 | par->vBackPorch += (par->vBackPorch % 2); | |
533 | if (info->var.vmode & FB_VMODE_DOUBLE) { | |
534 | par->vBackPorch <<= 1; | |
535 | par->yDim <<=1; | |
536 | par->vSyncOn <<=1; | |
537 | par->vSyncOff <<=1; | |
538 | } | |
539 | ||
540 | if (IS_VOODOO2(par)) { | |
541 | /* voodoo2 has 32 pixel wide tiles , BUT stange things | |
542 | happen with odd number of tiles */ | |
543 | par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2; | |
544 | } else { | |
545 | /* voodoo1 has 64 pixels wide tiles. */ | |
546 | par->tiles_in_X = (info->var.xres + 63 ) / 64; | |
547 | } | |
548 | ||
549 | f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n"); | |
550 | f_ddprintk("%-7d %-8d %-7d %-8d\n", | |
551 | info->var.hsync_len, par->hSyncOff, | |
552 | par->vSyncOn, par->vSyncOff); | |
553 | f_ddprintk("left_margin upper_margin xres yres Freq\n"); | |
554 | f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n", | |
555 | info->var.left_margin, info->var.upper_margin, | |
556 | info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock)); | |
557 | ||
558 | sst_write(NOPCMD, 0); | |
559 | sst_wait_idle(); | |
560 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); | |
561 | sst_set_bits(FBIINIT1, VIDEO_RESET); | |
562 | sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); | |
563 | sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); | |
564 | sst_wait_idle(); | |
565 | ||
566 | /*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */ | |
567 | ||
568 | sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2)); | |
569 | sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1)); | |
570 | sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1)); | |
571 | sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn); | |
572 | ||
573 | fbiinit2 = sst_read(FBIINIT2); | |
574 | fbiinit3 = sst_read(FBIINIT3); | |
575 | ||
576 | /* everything is reset. we enable fbiinit2/3 remap : dac acces ok */ | |
577 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, | |
578 | PCI_EN_INIT_WR | PCI_REMAP_DAC ); | |
579 | ||
580 | par->dac_sw.set_vidmod(info, info->var.bits_per_pixel); | |
581 | ||
582 | /* set video clock */ | |
583 | par->dac_sw.set_pll(info, &par->pll, VID_CLOCK); | |
584 | ||
585 | /* disable fbiinit2/3 remap */ | |
586 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, | |
587 | PCI_EN_INIT_WR); | |
588 | ||
589 | /* restore fbiinit2/3 */ | |
590 | sst_write(FBIINIT2,fbiinit2); | |
591 | sst_write(FBIINIT3,fbiinit3); | |
592 | ||
593 | fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK) | |
594 | | EN_DATA_OE | |
595 | | EN_BLANK_OE | |
596 | | EN_HVSYNC_OE | |
597 | | EN_DCLK_OE | |
598 | /* | (15 << TILES_IN_X_SHIFT) */ | |
599 | | SEL_INPUT_VCLK_2X | |
600 | /* | (2 << VCLK_2X_SEL_DEL_SHIFT) | |
601 | | (2 << VCLK_DEL_SHIFT) */; | |
602 | /* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28) | |
603 | in (near) future set them accordingly to revision + resolution (cf glide) | |
604 | first understand what it stands for :) | |
605 | FIXME: there are some artefacts... check for the vclk_in_delay | |
606 | lets try with 6ns delay in both vclk_out & in... | |
607 | doh... they're still there :\ | |
608 | */ | |
609 | ||
610 | ntiles = par->tiles_in_X; | |
611 | if (IS_VOODOO2(par)) { | |
612 | fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT | |
613 | | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT; | |
614 | /* as the only value of importance for us in fbiinit6 is tiles in X (lsb), | |
615 | and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just | |
616 | write our value. BTW due to the dac unable to read odd number of tiles, this | |
617 | field is always null ... */ | |
618 | fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT; | |
619 | } | |
620 | else | |
621 | fbiinit1 |= ntiles << TILES_IN_X_SHIFT; | |
622 | ||
623 | switch (info->var.bits_per_pixel) { | |
624 | case 16: | |
625 | fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL; | |
626 | break; | |
1da177e4 LT |
627 | default: |
628 | return -EINVAL; | |
629 | } | |
630 | sst_write(FBIINIT1, fbiinit1); | |
631 | if (IS_VOODOO2(par)) { | |
632 | sst_write(FBIINIT6, fbiinit6); | |
633 | fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ; | |
634 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
635 | fbiinit5 |= INTERLACE; | |
636 | if (info->var.vmode & FB_VMODE_DOUBLE) | |
637 | fbiinit5 |= VDOUBLESCAN; | |
638 | if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) | |
639 | fbiinit5 |= HSYNC_HIGH; | |
640 | if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) | |
641 | fbiinit5 |= VSYNC_HIGH; | |
642 | sst_write(FBIINIT5, fbiinit5); | |
643 | } | |
644 | sst_wait_idle(); | |
645 | sst_unset_bits(FBIINIT1, VIDEO_RESET); | |
646 | sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET); | |
647 | sst_set_bits(FBIINIT2, EN_DRAM_REFRESH); | |
648 | /* disables fbiinit writes */ | |
649 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR); | |
650 | ||
651 | /* set lfbmode : set mode + front buffer for reads/writes | |
652 | + disable pipeline */ | |
653 | switch (info->var.bits_per_pixel) { | |
654 | case 16: | |
655 | lfbmode = LFB_565; | |
656 | break; | |
1da177e4 LT |
657 | default: |
658 | return -EINVAL; | |
659 | } | |
660 | ||
661 | #if defined(__BIG_ENDIAN) | |
662 | /* Enable byte-swizzle functionality in hardware. | |
663 | * With this enabled, all our read- and write-accesses to | |
664 | * the voodoo framebuffer can be done in native format, and | |
665 | * the hardware will automatically convert it to little-endian. | |
666 | * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */ | |
667 | lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR | | |
668 | LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD ); | |
669 | #endif | |
670 | ||
671 | if (clipping) { | |
672 | sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE); | |
673 | /* | |
674 | * Set "clipping" dimensions. If clipping is disabled and | |
675 | * writes to offscreen areas of the framebuffer are performed, | |
676 | * the "behaviour is undefined" (_very_ undefined) - Urs | |
677 | */ | |
678 | /* btw, it requires enabling pixel pipeline in LFBMODE . | |
679 | off screen read/writes will just wrap and read/print pixels | |
680 | on screen. Ugly but not that dangerous */ | |
681 | f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n", | |
682 | info->var.xres - 1, par->yDim - 1); | |
683 | ||
684 | sst_write(CLIP_LEFT_RIGHT, info->var.xres); | |
685 | sst_write(CLIP_LOWY_HIGHY, par->yDim); | |
686 | sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE); | |
687 | } else { | |
688 | /* no clipping : direct access, no pipeline */ | |
689 | sst_write(LFBMODE, lfbmode); | |
690 | } | |
691 | return 0; | |
692 | } | |
693 | ||
694 | /** | |
695 | * sstfb_setcolreg - Optional function. Sets a color register. | |
696 | * @regno: hardware colormap register | |
697 | * @red: frame buffer colormap structure | |
698 | * @green: The green value which can be up to 16 bits wide | |
699 | * @blue: The blue value which can be up to 16 bits wide. | |
700 | * @transp: If supported the alpha value which can be up to 16 bits wide. | |
701 | * @info: frame buffer info structure | |
702 | */ | |
703 | static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
704 | u_int transp, struct fb_info *info) | |
705 | { | |
7227576f | 706 | struct sstfb_par *par = info->par; |
1da177e4 LT |
707 | u32 col; |
708 | ||
709 | f_dddprintk("sstfb_setcolreg\n"); | |
710 | f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n", | |
711 | regno, red, green, blue, transp); | |
7227576f AD |
712 | if (regno > 15) |
713 | return 0; | |
1da177e4 LT |
714 | |
715 | red >>= (16 - info->var.red.length); | |
716 | green >>= (16 - info->var.green.length); | |
717 | blue >>= (16 - info->var.blue.length); | |
718 | transp >>= (16 - info->var.transp.length); | |
719 | col = (red << info->var.red.offset) | |
720 | | (green << info->var.green.offset) | |
721 | | (blue << info->var.blue.offset) | |
722 | | (transp << info->var.transp.offset); | |
723 | ||
7227576f | 724 | par->palette[regno] = col; |
1da177e4 LT |
725 | |
726 | return 0; | |
727 | } | |
728 | ||
67a6680d | 729 | static int sstfb_ioctl(struct fb_info *info, u_int cmd, u_long arg) |
1da177e4 | 730 | { |
7227576f | 731 | struct sstfb_par *par = info->par; |
1da177e4 LT |
732 | struct pci_dev *sst_dev = par->dev; |
733 | u32 fbiinit0, tmp, val; | |
734 | u_long p; | |
735 | ||
736 | switch (cmd) { | |
737 | ||
738 | /* dump current FBIINIT values to system log */ | |
739 | case _IO('F', 0xdb): /* 0x46db */ | |
740 | return sstfb_dump_regs(info); | |
741 | ||
742 | /* fills lfb with #arg pixels */ | |
743 | case _IOW('F', 0xdc, u32): /* 0x46dc */ | |
744 | if (copy_from_user(&val, (void __user *)arg, sizeof(val))) | |
745 | return -EFAULT; | |
746 | if (val > info->fix.smem_len) | |
747 | val = info->fix.smem_len; | |
b98fc9a3 | 748 | for (p = 0 ; p < val; p += 2) |
1da177e4 LT |
749 | writew(p >> 6, info->screen_base + p); |
750 | return 0; | |
751 | ||
752 | /* change VGA pass_through mode */ | |
753 | case _IOW('F', 0xdd, u32): /* 0x46dd */ | |
754 | if (copy_from_user(&val, (void __user *)arg, sizeof(val))) | |
755 | return -EFAULT; | |
756 | pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp); | |
757 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, | |
758 | tmp | PCI_EN_INIT_WR ); | |
759 | fbiinit0 = sst_read (FBIINIT0); | |
b98fc9a3 | 760 | if (val) |
1da177e4 | 761 | sst_write(FBIINIT0, fbiinit0 & ~EN_VGA_PASSTHROUGH); |
b98fc9a3 | 762 | else |
1da177e4 | 763 | sst_write(FBIINIT0, fbiinit0 | EN_VGA_PASSTHROUGH); |
1da177e4 LT |
764 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp); |
765 | return 0; | |
766 | ||
767 | /* draw test image */ | |
768 | case _IO('F', 0xde): /* 0x46de */ | |
769 | f_dprintk("test color display at %d bpp\n", | |
770 | info->var.bits_per_pixel); | |
771 | sstfb_drawdebugimage(info); | |
772 | return 0; | |
773 | } | |
774 | return -EINVAL; | |
775 | } | |
776 | ||
777 | ||
778 | /* | |
779 | * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only | |
780 | */ | |
781 | #if 0 | |
782 | static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) | |
783 | { | |
7227576f | 784 | struct sstfb_par *par = info->par; |
1da177e4 LT |
785 | u32 stride = info->fix.line_length; |
786 | ||
787 | if (!IS_VOODOO2(par)) | |
788 | return; | |
789 | ||
790 | sst_write(BLTSRCBASEADDR, 0); | |
791 | sst_write(BLTDSTBASEADDR, 0); | |
792 | sst_write(BLTROP, BLTROP_COPY); | |
793 | sst_write(BLTXYSTRIDES, stride | (stride << 16)); | |
794 | sst_write(BLTSRCXY, area->sx | (area->sy << 16)); | |
795 | sst_write(BLTDSTXY, area->dx | (area->dy << 16)); | |
796 | sst_write(BLTSIZE, area->width | (area->height << 16)); | |
797 | sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT | | |
798 | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) ); | |
799 | sst_wait_idle(); | |
800 | } | |
801 | #endif | |
802 | ||
803 | ||
804 | /* | |
805 | * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only | |
806 | */ | |
807 | static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
808 | { | |
7227576f | 809 | struct sstfb_par *par = info->par; |
1da177e4 LT |
810 | u32 stride = info->fix.line_length; |
811 | ||
812 | if (!IS_VOODOO2(par)) | |
813 | return; | |
814 | ||
815 | sst_write(BLTCLIPX, info->var.xres); | |
816 | sst_write(BLTCLIPY, info->var.yres); | |
817 | ||
818 | sst_write(BLTDSTBASEADDR, 0); | |
819 | sst_write(BLTCOLOR, rect->color); | |
820 | sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR); | |
821 | sst_write(BLTXYSTRIDES, stride | (stride << 16)); | |
822 | sst_write(BLTDSTXY, rect->dx | (rect->dy << 16)); | |
823 | sst_write(BLTSIZE, rect->width | (rect->height << 16)); | |
824 | sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT | |
825 | | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) ); | |
826 | sst_wait_idle(); | |
827 | } | |
828 | ||
829 | ||
830 | ||
831 | /* | |
832 | * get lfb size | |
833 | */ | |
834 | static int __devinit sst_get_memsize(struct fb_info *info, __u32 *memsize) | |
835 | { | |
836 | u8 __iomem *fbbase_virt = info->screen_base; | |
837 | ||
838 | /* force memsize */ | |
b98fc9a3 | 839 | if (mem >= 1 && mem <= 4) { |
1da177e4 | 840 | *memsize = (mem * 0x100000); |
b98fc9a3 | 841 | printk(KERN_INFO "supplied memsize: %#x\n", *memsize); |
1da177e4 LT |
842 | return 1; |
843 | } | |
844 | ||
845 | writel(0xdeadbeef, fbbase_virt); | |
846 | writel(0xdeadbeef, fbbase_virt+0x100000); | |
847 | writel(0xdeadbeef, fbbase_virt+0x200000); | |
848 | f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n", | |
849 | readl(fbbase_virt), readl(fbbase_virt + 0x100000), | |
850 | readl(fbbase_virt + 0x200000)); | |
851 | ||
852 | writel(0xabcdef01, fbbase_virt); | |
853 | ||
854 | f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n", | |
855 | readl(fbbase_virt), readl(fbbase_virt + 0x100000), | |
856 | readl(fbbase_virt + 0x200000)); | |
857 | ||
858 | /* checks for 4mb lfb, then 2, then defaults to 1 */ | |
859 | if (readl(fbbase_virt + 0x200000) == 0xdeadbeef) | |
860 | *memsize = 0x400000; | |
861 | else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef) | |
862 | *memsize = 0x200000; | |
863 | else | |
864 | *memsize = 0x100000; | |
865 | f_ddprintk("detected memsize: %dMB\n", *memsize >> 20); | |
866 | return 1; | |
867 | } | |
868 | ||
869 | ||
870 | /* | |
871 | * DAC detection routines | |
872 | */ | |
873 | ||
874 | /* fbi should be idle, and fifo emty and mem disabled */ | |
875 | /* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */ | |
876 | ||
877 | static int __devinit sst_detect_att(struct fb_info *info) | |
878 | { | |
7227576f | 879 | struct sstfb_par *par = info->par; |
1da177e4 LT |
880 | int i, mir, dir; |
881 | ||
b98fc9a3 | 882 | for (i = 0; i < 3; i++) { |
1da177e4 LT |
883 | sst_dac_write(DACREG_WMA, 0); /* backdoor */ |
884 | sst_dac_read(DACREG_RMR); /* read 4 times RMR */ | |
885 | sst_dac_read(DACREG_RMR); | |
886 | sst_dac_read(DACREG_RMR); | |
887 | sst_dac_read(DACREG_RMR); | |
888 | /* the fifth time, CR0 is read */ | |
889 | sst_dac_read(DACREG_RMR); | |
890 | /* the 6th, manufacturer id register */ | |
891 | mir = sst_dac_read(DACREG_RMR); | |
892 | /*the 7th, device ID register */ | |
893 | dir = sst_dac_read(DACREG_RMR); | |
894 | f_ddprintk("mir: %#x, dir: %#x\n", mir, dir); | |
b98fc9a3 | 895 | if (mir == DACREG_MIR_ATT && dir == DACREG_DIR_ATT) { |
1da177e4 LT |
896 | return 1; |
897 | } | |
898 | } | |
899 | return 0; | |
900 | } | |
901 | ||
902 | static int __devinit sst_detect_ti(struct fb_info *info) | |
903 | { | |
7227576f | 904 | struct sstfb_par *par = info->par; |
1da177e4 LT |
905 | int i, mir, dir; |
906 | ||
907 | for (i = 0; i<3; i++) { | |
908 | sst_dac_write(DACREG_WMA, 0); /* backdoor */ | |
909 | sst_dac_read(DACREG_RMR); /* read 4 times RMR */ | |
910 | sst_dac_read(DACREG_RMR); | |
911 | sst_dac_read(DACREG_RMR); | |
912 | sst_dac_read(DACREG_RMR); | |
913 | /* the fifth time, CR0 is read */ | |
914 | sst_dac_read(DACREG_RMR); | |
915 | /* the 6th, manufacturer id register */ | |
916 | mir = sst_dac_read(DACREG_RMR); | |
917 | /*the 7th, device ID register */ | |
918 | dir = sst_dac_read(DACREG_RMR); | |
919 | f_ddprintk("mir: %#x, dir: %#x\n", mir, dir); | |
920 | if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) { | |
921 | return 1; | |
922 | } | |
923 | } | |
924 | return 0; | |
925 | } | |
926 | ||
927 | /* | |
928 | * try to detect ICS5342 ramdac | |
929 | * we get the 1st byte (M value) of preset f1,f7 and fB | |
930 | * why those 3 ? mmmh... for now, i'll do it the glide way... | |
931 | * and ask questions later. anyway, it seems that all the freq registers are | |
932 | * realy at their default state (cf specs) so i ask again, why those 3 regs ? | |
933 | * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for | |
934 | * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be | |
935 | * touched... | |
936 | * is it realy safe ? how can i reset this ramdac ? geee... | |
937 | */ | |
938 | static int __devinit sst_detect_ics(struct fb_info *info) | |
939 | { | |
7227576f | 940 | struct sstfb_par *par = info->par; |
1da177e4 LT |
941 | int m_clk0_1, m_clk0_7, m_clk1_b; |
942 | int n_clk0_1, n_clk0_7, n_clk1_b; | |
943 | int i; | |
944 | ||
945 | for (i = 0; i<5; i++ ) { | |
946 | sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */ | |
947 | m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA); | |
948 | n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA); | |
949 | sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */ | |
950 | m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA); | |
951 | n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA); | |
952 | sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */ | |
953 | m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA); | |
954 | n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA); | |
955 | f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n", | |
956 | m_clk0_1, m_clk0_7, m_clk1_b); | |
957 | f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n", | |
958 | n_clk0_1, n_clk0_7, n_clk1_b); | |
959 | if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI) | |
960 | && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI) | |
961 | && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) { | |
962 | return 1; | |
963 | } | |
964 | } | |
965 | return 0; | |
966 | } | |
967 | ||
968 | ||
969 | /* | |
970 | * gfx, video, pci fifo should be reset, dram refresh disabled | |
971 | * see detect_dac | |
972 | */ | |
973 | ||
974 | static int sst_set_pll_att_ti(struct fb_info *info, | |
975 | const struct pll_timing *t, const int clock) | |
976 | { | |
7227576f | 977 | struct sstfb_par *par = info->par; |
1da177e4 LT |
978 | u8 cr0, cc; |
979 | ||
980 | /* enable indexed mode */ | |
981 | sst_dac_write(DACREG_WMA, 0); /* backdoor */ | |
982 | sst_dac_read(DACREG_RMR); /* 1 time: RMR */ | |
983 | sst_dac_read(DACREG_RMR); /* 2 RMR */ | |
984 | sst_dac_read(DACREG_RMR); /* 3 // */ | |
985 | sst_dac_read(DACREG_RMR); /* 4 // */ | |
986 | cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */ | |
987 | ||
988 | sst_dac_write(DACREG_WMA, 0); | |
989 | sst_dac_read(DACREG_RMR); | |
990 | sst_dac_read(DACREG_RMR); | |
991 | sst_dac_read(DACREG_RMR); | |
992 | sst_dac_read(DACREG_RMR); | |
993 | sst_dac_write(DACREG_RMR, (cr0 & 0xf0) | |
994 | | DACREG_CR0_EN_INDEXED | |
995 | | DACREG_CR0_8BIT | |
996 | | DACREG_CR0_PWDOWN ); | |
997 | /* so, now we are in indexed mode . dunno if its common, but | |
998 | i find this way of doing things a little bit weird :p */ | |
999 | ||
1000 | udelay(300); | |
1001 | cc = dac_i_read(DACREG_CC_I); | |
1002 | switch (clock) { | |
1003 | case VID_CLOCK: | |
1004 | dac_i_write(DACREG_AC0_I, t->m); | |
1005 | dac_i_write(DACREG_AC1_I, t->p << 6 | t->n); | |
1006 | dac_i_write(DACREG_CC_I, | |
1007 | (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C); | |
1008 | break; | |
1009 | case GFX_CLOCK: | |
1010 | dac_i_write(DACREG_BD0_I, t->m); | |
1011 | dac_i_write(DACREG_BD1_I, t->p << 6 | t->n); | |
1012 | dac_i_write(DACREG_CC_I, | |
1013 | (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D); | |
1014 | break; | |
1015 | default: | |
1016 | dprintk("%s: wrong clock code '%d'\n", | |
1017 | __FUNCTION__, clock); | |
1018 | return 0; | |
1019 | } | |
1020 | udelay(300); | |
1021 | ||
1022 | /* power up the dac & return to "normal" non-indexed mode */ | |
1023 | dac_i_write(DACREG_CR0_I, | |
1024 | cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED); | |
1025 | return 1; | |
1026 | } | |
1027 | ||
1028 | static int sst_set_pll_ics(struct fb_info *info, | |
1029 | const struct pll_timing *t, const int clock) | |
1030 | { | |
7227576f | 1031 | struct sstfb_par *par = info->par; |
1da177e4 LT |
1032 | u8 pll_ctrl; |
1033 | ||
1034 | sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL); | |
1035 | pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA); | |
1036 | switch(clock) { | |
1037 | case VID_CLOCK: | |
1038 | sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */ | |
1039 | sst_dac_write(DACREG_ICS_PLLDATA, t->m); | |
1040 | sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n); | |
1041 | /* selects freq f0 for clock 0 */ | |
1042 | sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL); | |
1043 | sst_dac_write(DACREG_ICS_PLLDATA, | |
1044 | (pll_ctrl & 0xd8) | |
1045 | | DACREG_ICS_CLK0 | |
1046 | | DACREG_ICS_CLK0_0); | |
1047 | break; | |
1048 | case GFX_CLOCK : | |
1049 | sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */ | |
1050 | sst_dac_write(DACREG_ICS_PLLDATA, t->m); | |
1051 | sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n); | |
1052 | /* selects freq fA for clock 1 */ | |
1053 | sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL); | |
1054 | sst_dac_write(DACREG_ICS_PLLDATA, | |
1055 | (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A); | |
1056 | break; | |
1057 | default: | |
1058 | dprintk("%s: wrong clock code '%d'\n", | |
1059 | __FUNCTION__, clock); | |
1060 | return 0; | |
1061 | } | |
1062 | udelay(300); | |
1063 | return 1; | |
1064 | } | |
1065 | ||
1066 | static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp) | |
1067 | { | |
7227576f | 1068 | struct sstfb_par *par = info->par; |
1da177e4 LT |
1069 | u8 cr0; |
1070 | ||
1071 | sst_dac_write(DACREG_WMA, 0); /* backdoor */ | |
1072 | sst_dac_read(DACREG_RMR); /* read 4 times RMR */ | |
1073 | sst_dac_read(DACREG_RMR); | |
1074 | sst_dac_read(DACREG_RMR); | |
1075 | sst_dac_read(DACREG_RMR); | |
1076 | /* the fifth time, CR0 is read */ | |
1077 | cr0 = sst_dac_read(DACREG_RMR); | |
1078 | ||
1079 | sst_dac_write(DACREG_WMA, 0); /* backdoor */ | |
1080 | sst_dac_read(DACREG_RMR); /* read 4 times RMR */ | |
1081 | sst_dac_read(DACREG_RMR); | |
1082 | sst_dac_read(DACREG_RMR); | |
1083 | sst_dac_read(DACREG_RMR); | |
1084 | /* cr0 */ | |
1085 | switch(bpp) { | |
1086 | case 16: | |
1087 | sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP); | |
1088 | break; | |
1da177e4 LT |
1089 | default: |
1090 | dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp); | |
1091 | break; | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | static void sst_set_vidmod_ics(struct fb_info *info, const int bpp) | |
1096 | { | |
7227576f | 1097 | struct sstfb_par *par = info->par; |
1da177e4 LT |
1098 | |
1099 | switch(bpp) { | |
1100 | case 16: | |
1101 | sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP); | |
1102 | break; | |
1da177e4 LT |
1103 | default: |
1104 | dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp); | |
1105 | break; | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | /* | |
1110 | * detect dac type | |
1111 | * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset, | |
1112 | * dram refresh disabled, FbiInit remaped. | |
1113 | * TODO: mmh.. maybe i shoud put the "prerequisite" in the func ... | |
1114 | */ | |
1115 | ||
1116 | ||
1117 | static struct dac_switch dacs[] __devinitdata = { | |
1118 | { .name = "TI TVP3409", | |
1119 | .detect = sst_detect_ti, | |
1120 | .set_pll = sst_set_pll_att_ti, | |
1121 | .set_vidmod = sst_set_vidmod_att_ti }, | |
1122 | ||
1123 | { .name = "AT&T ATT20C409", | |
1124 | .detect = sst_detect_att, | |
1125 | .set_pll = sst_set_pll_att_ti, | |
1126 | .set_vidmod = sst_set_vidmod_att_ti }, | |
1127 | { .name = "ICS ICS5342", | |
1128 | .detect = sst_detect_ics, | |
1129 | .set_pll = sst_set_pll_ics, | |
1130 | .set_vidmod = sst_set_vidmod_ics }, | |
1131 | }; | |
1132 | ||
1133 | static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par) | |
1134 | { | |
1135 | int i, ret = 0; | |
d1ae418e TK |
1136 | |
1137 | for (i = 0; i < ARRAY_SIZE(dacs); i++) { | |
1da177e4 | 1138 | ret = dacs[i].detect(info); |
d1ae418e TK |
1139 | if (ret) |
1140 | break; | |
1da177e4 LT |
1141 | } |
1142 | if (!ret) | |
1143 | return 0; | |
1144 | f_dprintk("%s found %s\n", __FUNCTION__, dacs[i].name); | |
1145 | par->dac_sw = dacs[i]; | |
1146 | return 1; | |
1147 | } | |
1148 | ||
1149 | /* | |
1150 | * Internal Routines | |
1151 | */ | |
1152 | static int __devinit sst_init(struct fb_info *info, struct sstfb_par *par) | |
1153 | { | |
1154 | u32 fbiinit0, fbiinit1, fbiinit4; | |
1155 | struct pci_dev *dev = par->dev; | |
1156 | struct pll_timing gfx_timings; | |
1157 | struct sst_spec *spec; | |
1158 | int Fout; | |
1159 | ||
1160 | spec = &voodoo_spec[par->type]; | |
1161 | f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 " | |
1162 | " fbiinit6\n"); | |
1163 | f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n", | |
1164 | sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2), | |
1165 | sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6)); | |
1166 | /* disable video clock */ | |
1167 | pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0); | |
1168 | ||
1169 | /* enable writing to init registers, disable pci fifo */ | |
1170 | pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); | |
1171 | /* reset video */ | |
1172 | sst_set_bits(FBIINIT1, VIDEO_RESET); | |
1173 | sst_wait_idle(); | |
1174 | /* reset gfx + pci fifo */ | |
1175 | sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); | |
1176 | sst_wait_idle(); | |
1177 | ||
1178 | /* unreset fifo */ | |
1179 | /*sst_unset_bits(FBIINIT0, FIFO_RESET); | |
1180 | sst_wait_idle();*/ | |
1181 | /* unreset FBI */ | |
1182 | /*sst_unset_bits(FBIINIT0, FBI_RESET); | |
1183 | sst_wait_idle();*/ | |
1184 | ||
1185 | /* disable dram refresh */ | |
1186 | sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); | |
1187 | sst_wait_idle(); | |
1188 | /* remap fbinit2/3 to dac */ | |
1189 | pci_write_config_dword(dev, PCI_INIT_ENABLE, | |
1190 | PCI_EN_INIT_WR | PCI_REMAP_DAC ); | |
1191 | /* detect dac type */ | |
1192 | if (!sst_detect_dactype(info, par)) { | |
b98fc9a3 | 1193 | printk(KERN_ERR "sstfb: unknown dac type.\n"); |
1da177e4 LT |
1194 | //FIXME watch it: we are not in a safe state, bad bad bad. |
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | /* set graphic clock */ | |
1199 | par->gfx_clock = spec->default_gfx_clock; | |
1200 | if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) { | |
b98fc9a3 | 1201 | printk(KERN_INFO "sstfb: Using supplied graphic freq : %dMHz\n", gfxclk); |
1da177e4 LT |
1202 | par->gfx_clock = gfxclk *1000; |
1203 | } else if (gfxclk) { | |
b98fc9a3 | 1204 | printk(KERN_WARNING "sstfb: %dMhz is way out of spec! Using default\n", gfxclk); |
1da177e4 LT |
1205 | } |
1206 | ||
1207 | sst_calc_pll(par->gfx_clock, &Fout, &gfx_timings); | |
1208 | par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK); | |
1209 | ||
1210 | /* disable fbiinit remap */ | |
1211 | pci_write_config_dword(dev, PCI_INIT_ENABLE, | |
1212 | PCI_EN_INIT_WR| PCI_EN_FIFO_WR ); | |
1213 | /* defaults init registers */ | |
1214 | /* FbiInit0: unreset gfx, unreset fifo */ | |
1215 | fbiinit0 = FBIINIT0_DEFAULT; | |
1216 | fbiinit1 = FBIINIT1_DEFAULT; | |
1217 | fbiinit4 = FBIINIT4_DEFAULT; | |
1218 | if (vgapass) | |
1219 | fbiinit0 &= ~EN_VGA_PASSTHROUGH; | |
1220 | else | |
1221 | fbiinit0 |= EN_VGA_PASSTHROUGH; | |
1222 | if (slowpci) { | |
1223 | fbiinit1 |= SLOW_PCI_WRITES; | |
1224 | fbiinit4 |= SLOW_PCI_READS; | |
1225 | } else { | |
1226 | fbiinit1 &= ~SLOW_PCI_WRITES; | |
1227 | fbiinit4 &= ~SLOW_PCI_READS; | |
1228 | } | |
1229 | sst_write(FBIINIT0, fbiinit0); | |
1230 | sst_wait_idle(); | |
1231 | sst_write(FBIINIT1, fbiinit1); | |
1232 | sst_wait_idle(); | |
1233 | sst_write(FBIINIT2, FBIINIT2_DEFAULT); | |
1234 | sst_wait_idle(); | |
1235 | sst_write(FBIINIT3, FBIINIT3_DEFAULT); | |
1236 | sst_wait_idle(); | |
1237 | sst_write(FBIINIT4, fbiinit4); | |
1238 | sst_wait_idle(); | |
1239 | if (IS_VOODOO2(par)) { | |
1240 | sst_write(FBIINIT6, FBIINIT6_DEFAULT); | |
1241 | sst_wait_idle(); | |
1242 | } | |
1243 | ||
1244 | pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR); | |
1245 | pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0); | |
1246 | return 1; | |
1247 | } | |
1248 | ||
1249 | static void __devexit sst_shutdown(struct fb_info *info) | |
1250 | { | |
7227576f | 1251 | struct sstfb_par *par = info->par; |
1da177e4 LT |
1252 | struct pci_dev *dev = par->dev; |
1253 | struct pll_timing gfx_timings; | |
1254 | int Fout; | |
1255 | ||
1256 | /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */ | |
1257 | pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); | |
1258 | sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING); | |
1259 | sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); | |
1260 | sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); | |
1261 | sst_wait_idle(); | |
1262 | pci_write_config_dword(dev, PCI_INIT_ENABLE, | |
1263 | PCI_EN_INIT_WR | PCI_REMAP_DAC); | |
1264 | /* set 20Mhz gfx clock */ | |
1265 | sst_calc_pll(20000, &Fout, &gfx_timings); | |
1266 | par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK); | |
1267 | /* TODO maybe shutdown the dac, vrefresh and so on... */ | |
1268 | pci_write_config_dword(dev, PCI_INIT_ENABLE, | |
1269 | PCI_EN_INIT_WR); | |
1270 | sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | EN_VGA_PASSTHROUGH); | |
1271 | pci_write_config_dword(dev, PCI_VCLK_DISABLE,0); | |
1272 | /* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct | |
1273 | * from start ? */ | |
1274 | pci_write_config_dword(dev, PCI_INIT_ENABLE, 0); | |
1275 | ||
1276 | } | |
1277 | ||
1278 | /* | |
1279 | * Interface to the world | |
1280 | */ | |
1281 | #ifndef MODULE | |
1282 | static int __init sstfb_setup(char *options) | |
1283 | { | |
1284 | char *this_opt; | |
1285 | ||
1286 | if (!options || !*options) | |
1287 | return 0; | |
1288 | ||
1289 | while ((this_opt = strsep(&options, ",")) != NULL) { | |
1290 | if (!*this_opt) continue; | |
1291 | ||
1292 | f_ddprintk("option %s\n", this_opt); | |
1293 | ||
1294 | if (!strcmp(this_opt, "vganopass")) | |
1295 | vgapass = 0; | |
1296 | else if (!strcmp(this_opt, "vgapass")) | |
1297 | vgapass = 1; | |
1298 | else if (!strcmp(this_opt, "clipping")) | |
1299 | clipping = 1; | |
1300 | else if (!strcmp(this_opt, "noclipping")) | |
1301 | clipping = 0; | |
1302 | else if (!strcmp(this_opt, "fastpci")) | |
1303 | slowpci = 0; | |
1304 | else if (!strcmp(this_opt, "slowpci")) | |
1305 | slowpci = 1; | |
1306 | else if (!strncmp(this_opt, "mem:",4)) | |
1307 | mem = simple_strtoul (this_opt+4, NULL, 0); | |
1308 | else if (!strncmp(this_opt, "gfxclk:",7)) | |
1309 | gfxclk = simple_strtoul (this_opt+7, NULL, 0); | |
1310 | else | |
1311 | mode_option = this_opt; | |
1312 | } | |
1313 | return 0; | |
1314 | } | |
1315 | #endif | |
1316 | ||
1317 | static struct fb_ops sstfb_ops = { | |
1318 | .owner = THIS_MODULE, | |
1319 | .fb_check_var = sstfb_check_var, | |
1320 | .fb_set_par = sstfb_set_par, | |
1321 | .fb_setcolreg = sstfb_setcolreg, | |
1322 | .fb_fillrect = cfb_fillrect, /* sstfb_fillrect */ | |
1323 | .fb_copyarea = cfb_copyarea, /* sstfb_copyarea */ | |
1324 | .fb_imageblit = cfb_imageblit, | |
1da177e4 LT |
1325 | .fb_ioctl = sstfb_ioctl, |
1326 | }; | |
1327 | ||
1328 | static int __devinit sstfb_probe(struct pci_dev *pdev, | |
1329 | const struct pci_device_id *id) | |
1330 | { | |
1331 | struct fb_info *info; | |
1332 | struct fb_fix_screeninfo *fix; | |
1333 | struct sstfb_par *par; | |
1334 | struct sst_spec *spec; | |
1335 | int err; | |
1336 | ||
1da177e4 LT |
1337 | /* Enable device in PCI config. */ |
1338 | if ((err=pci_enable_device(pdev))) { | |
b98fc9a3 | 1339 | printk(KERN_ERR "cannot enable device\n"); |
1da177e4 LT |
1340 | return err; |
1341 | } | |
1342 | ||
1343 | /* Allocate the fb and par structures. */ | |
7227576f AD |
1344 | info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev); |
1345 | if (!info) | |
1da177e4 | 1346 | return -ENOMEM; |
7227576f AD |
1347 | |
1348 | pci_set_drvdata(pdev, info); | |
1da177e4 | 1349 | |
7227576f | 1350 | par = info->par; |
1da177e4 LT |
1351 | fix = &info->fix; |
1352 | ||
1353 | par->type = id->driver_data; | |
1354 | spec = &voodoo_spec[par->type]; | |
1355 | f_ddprintk("found device : %s\n", spec->name); | |
1356 | ||
1357 | par->dev = pdev; | |
1358 | pci_read_config_byte(pdev, PCI_REVISION_ID, &par->revision); | |
1359 | ||
1360 | fix->mmio_start = pci_resource_start(pdev,0); | |
1361 | fix->mmio_len = 0x400000; | |
1362 | fix->smem_start = fix->mmio_start + 0x400000; | |
1363 | ||
1364 | if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) { | |
b98fc9a3 | 1365 | printk(KERN_ERR "sstfb: cannot reserve mmio memory\n"); |
1da177e4 LT |
1366 | goto fail_mmio_mem; |
1367 | } | |
1368 | ||
1369 | if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) { | |
b98fc9a3 | 1370 | printk(KERN_ERR "sstfb: cannot reserve fb memory\n"); |
1da177e4 LT |
1371 | goto fail_fb_mem; |
1372 | } | |
1373 | ||
1374 | par->mmio_vbase = ioremap_nocache(fix->mmio_start, | |
1375 | fix->mmio_len); | |
1376 | if (!par->mmio_vbase) { | |
b98fc9a3 | 1377 | printk(KERN_ERR "sstfb: cannot remap register area %#lx\n", |
1da177e4 LT |
1378 | fix->mmio_start); |
1379 | goto fail_mmio_remap; | |
1380 | } | |
1381 | info->screen_base = ioremap_nocache(fix->smem_start, 0x400000); | |
1382 | if (!info->screen_base) { | |
b98fc9a3 | 1383 | printk(KERN_ERR "sstfb: cannot remap framebuffer %#lx\n", |
1da177e4 LT |
1384 | fix->smem_start); |
1385 | goto fail_fb_remap; | |
1386 | } | |
1387 | ||
1388 | if (!sst_init(info, par)) { | |
b98fc9a3 | 1389 | printk(KERN_ERR "sstfb: Init failed\n"); |
1da177e4 LT |
1390 | goto fail; |
1391 | } | |
1392 | sst_get_memsize(info, &fix->smem_len); | |
1393 | strlcpy(fix->id, spec->name, sizeof(fix->id)); | |
1394 | ||
b98fc9a3 | 1395 | printk(KERN_INFO "%s (revision %d) with %s dac\n", |
1da177e4 | 1396 | fix->id, par->revision, par->dac_sw.name); |
b98fc9a3 | 1397 | printk(KERN_INFO "framebuffer at %#lx, mapped to 0x%p, size %dMB\n", |
1da177e4 LT |
1398 | fix->smem_start, info->screen_base, |
1399 | fix->smem_len >> 20); | |
1400 | ||
1401 | f_ddprintk("regbase_virt: %#lx\n", par->mmio_vbase); | |
1402 | f_ddprintk("membase_phys: %#lx\n", fix->smem_start); | |
1403 | f_ddprintk("fbbase_virt: %p\n", info->screen_base); | |
1404 | ||
1405 | info->flags = FBINFO_DEFAULT; | |
1406 | info->fbops = &sstfb_ops; | |
7227576f | 1407 | info->pseudo_palette = par->palette; |
1da177e4 LT |
1408 | |
1409 | fix->type = FB_TYPE_PACKED_PIXELS; | |
1410 | fix->visual = FB_VISUAL_TRUECOLOR; | |
1411 | fix->accel = FB_ACCEL_NONE; /* FIXME */ | |
1412 | /* | |
1413 | * According to the specs, the linelength must be of 1024 *pixels* | |
b98fc9a3 AC |
1414 | * and the 24bpp mode is in fact a 32 bpp mode (and both are in |
1415 | * fact dithered to 16bit). | |
1da177e4 LT |
1416 | */ |
1417 | fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */ | |
1418 | ||
1419 | if ( mode_option && | |
1420 | fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16)) { | |
b98fc9a3 | 1421 | printk(KERN_ERR "sstfb: can't set supplied video mode. Using default\n"); |
1da177e4 LT |
1422 | info->var = sstfb_default; |
1423 | } else | |
1424 | info->var = sstfb_default; | |
1425 | ||
1426 | if (sstfb_check_var(&info->var, info)) { | |
b98fc9a3 | 1427 | printk(KERN_ERR "sstfb: invalid default video mode.\n"); |
1da177e4 LT |
1428 | goto fail; |
1429 | } | |
1430 | ||
1431 | if (sstfb_set_par(info)) { | |
b98fc9a3 | 1432 | printk(KERN_ERR "sstfb: can't set default video mode.\n"); |
1da177e4 LT |
1433 | goto fail; |
1434 | } | |
1435 | ||
1436 | fb_alloc_cmap(&info->cmap, 256, 0); | |
1437 | ||
1438 | /* register fb */ | |
1439 | info->device = &pdev->dev; | |
1440 | if (register_framebuffer(info) < 0) { | |
b98fc9a3 | 1441 | printk(KERN_ERR "sstfb: can't register framebuffer.\n"); |
1da177e4 LT |
1442 | goto fail; |
1443 | } | |
1444 | ||
1445 | if (1) /* set to 0 to see an initial bitmap instead */ | |
1446 | sstfb_clear_screen(info); | |
1447 | else | |
1448 | sstfb_drawdebugimage(info); | |
1449 | ||
1450 | printk(KERN_INFO "fb%d: %s frame buffer device at 0x%p\n", | |
1451 | info->node, fix->id, info->screen_base); | |
1452 | ||
1453 | return 0; | |
1454 | ||
1455 | fail: | |
1456 | iounmap(info->screen_base); | |
1457 | fail_fb_remap: | |
1458 | iounmap(par->mmio_vbase); | |
1459 | fail_mmio_remap: | |
1460 | release_mem_region(fix->smem_start, 0x400000); | |
1461 | fail_fb_mem: | |
1462 | release_mem_region(fix->mmio_start, info->fix.mmio_len); | |
1463 | fail_mmio_mem: | |
7227576f | 1464 | framebuffer_release(info); |
1da177e4 LT |
1465 | return -ENXIO; /* no voodoo detected */ |
1466 | } | |
1467 | ||
1468 | static void __devexit sstfb_remove(struct pci_dev *pdev) | |
1469 | { | |
1470 | struct sstfb_par *par; | |
1471 | struct fb_info *info; | |
1472 | ||
1473 | info = pci_get_drvdata(pdev); | |
7227576f | 1474 | par = info->par; |
1da177e4 LT |
1475 | |
1476 | sst_shutdown(info); | |
1477 | unregister_framebuffer(info); | |
1478 | iounmap(info->screen_base); | |
1479 | iounmap(par->mmio_vbase); | |
1480 | release_mem_region(info->fix.smem_start, 0x400000); | |
1481 | release_mem_region(info->fix.mmio_start, info->fix.mmio_len); | |
7227576f | 1482 | framebuffer_release(info); |
1da177e4 LT |
1483 | } |
1484 | ||
1485 | ||
1486 | static struct pci_device_id sstfb_id_tbl[] = { | |
1487 | { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO, | |
1488 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_VOODOO1 }, | |
1489 | { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2, | |
1490 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_VOODOO2 }, | |
1491 | { 0 }, | |
1492 | }; | |
1493 | ||
1494 | static struct pci_driver sstfb_driver = { | |
1495 | .name = "sstfb", | |
1496 | .id_table = sstfb_id_tbl, | |
1497 | .probe = sstfb_probe, | |
1498 | .remove = __devexit_p(sstfb_remove), | |
1499 | }; | |
1500 | ||
1501 | ||
1502 | static int __devinit sstfb_init(void) | |
1503 | { | |
1504 | #ifndef MODULE | |
1505 | char *option = NULL; | |
1506 | ||
1507 | if (fb_get_options("sstfb", &option)) | |
1508 | return -ENODEV; | |
1509 | sstfb_setup(option); | |
1510 | #endif | |
1511 | return pci_register_driver(&sstfb_driver); | |
1512 | } | |
1513 | ||
1514 | #ifdef MODULE | |
1515 | static void __devexit sstfb_exit(void) | |
1516 | { | |
1517 | pci_unregister_driver(&sstfb_driver); | |
1518 | } | |
1519 | #endif | |
1520 | ||
1521 | ||
1522 | /* | |
1523 | * testing and debugging functions | |
1524 | */ | |
1525 | ||
1526 | static int sstfb_dump_regs(struct fb_info *info) | |
1527 | { | |
1528 | #ifdef SST_DEBUG | |
1529 | static struct { u32 reg ; const char *reg_name;} pci_regs[] = { | |
1530 | { PCI_INIT_ENABLE, "initenable"}, | |
1531 | { PCI_VCLK_ENABLE, "enable vclk"}, | |
1532 | { PCI_VCLK_DISABLE, "disable vclk"}, | |
1533 | }; | |
1534 | ||
1535 | static struct { u32 reg ; const char *reg_name;} sst_regs[] = { | |
1536 | {FBIINIT0,"fbiinit0"}, | |
1537 | {FBIINIT1,"fbiinit1"}, | |
1538 | {FBIINIT2,"fbiinit2"}, | |
1539 | {FBIINIT3,"fbiinit3"}, | |
1540 | {FBIINIT4,"fbiinit4"}, | |
1541 | {FBIINIT5,"fbiinit5"}, | |
1542 | {FBIINIT6,"fbiinit6"}, | |
1543 | {FBIINIT7,"fbiinit7"}, | |
1544 | {LFBMODE,"lfbmode"}, | |
1545 | {FBZMODE,"fbzmode"}, | |
1546 | }; | |
1547 | ||
d1ae418e TK |
1548 | const int pci_s = ARRAY_SIZE(pci_regs); |
1549 | const int sst_s = ARRAY_SIZE(sst_regs); | |
7227576f | 1550 | struct sstfb_par *par = info->par; |
1da177e4 LT |
1551 | struct pci_dev *dev = par->dev; |
1552 | u32 pci_res[pci_s]; | |
1553 | u32 sst_res[sst_s]; | |
1554 | int i; | |
1555 | ||
1556 | for (i=0; i<pci_s; i++) { | |
1557 | pci_read_config_dword(dev, pci_regs[i].reg, &pci_res[i]); | |
1558 | } | |
1559 | for (i=0; i<sst_s; i++) { | |
1560 | sst_res[i] = sst_read(sst_regs[i].reg); | |
1561 | } | |
1562 | ||
1563 | dprintk("hardware register dump:\n"); | |
1564 | for (i=0; i<pci_s; i++) { | |
1565 | dprintk("%s %0#10x\n", pci_regs[i].reg_name, pci_res[i]); | |
1566 | } | |
1567 | for (i=0; i<sst_s; i++) { | |
1568 | dprintk("%s %0#10x\n", sst_regs[i].reg_name, sst_res[i]); | |
1569 | } | |
1570 | return 0; | |
1571 | #else | |
1572 | return -EINVAL; | |
1573 | #endif | |
1574 | } | |
1575 | ||
1576 | static void sstfb_fillrect_softw( struct fb_info *info, const struct fb_fillrect *rect) | |
1577 | { | |
1578 | u8 __iomem *fbbase_virt = info->screen_base; | |
1579 | int x, y, w = info->var.bits_per_pixel == 16 ? 2 : 4; | |
1580 | u32 color = rect->color, height = rect->height; | |
1581 | u8 __iomem *p; | |
1582 | ||
1583 | if (w==2) color |= color<<16; | |
1584 | for (y=rect->dy; height; y++, height--) { | |
1585 | p = fbbase_virt + y*info->fix.line_length + rect->dx*w; | |
1586 | x = rect->width; | |
1587 | if (w==2) x>>=1; | |
1588 | while (x) { | |
1589 | writel(color, p); | |
1590 | p += 4; | |
1591 | x--; | |
1592 | } | |
1593 | } | |
1594 | } | |
1595 | ||
1596 | static void sstfb_drawrect_XY( struct fb_info *info, int x, int y, | |
1597 | int w, int h, int color, int hwfunc) | |
1598 | { | |
1599 | struct fb_fillrect rect; | |
1600 | rect.dx = x; | |
1601 | rect.dy = y; | |
1602 | rect.height = h; | |
1603 | rect.width = w; | |
1604 | rect.color = color; | |
1605 | rect.rop = ROP_COPY; | |
1606 | if (hwfunc) | |
1607 | sstfb_fillrect(info, &rect); | |
1608 | else | |
1609 | sstfb_fillrect_softw(info, &rect); | |
1610 | } | |
1611 | ||
1612 | /* print some squares on the fb */ | |
1613 | static void sstfb_drawdebugimage(struct fb_info *info) | |
1614 | { | |
1615 | static int idx; | |
1616 | ||
1617 | /* clear screen */ | |
1618 | sstfb_clear_screen(info); | |
1619 | ||
1620 | idx = (idx+1) & 1; | |
1621 | ||
1622 | /* white rect */ | |
1623 | sstfb_drawrect_XY(info, 0, 0, 50, 50, 0xffff, idx); | |
1624 | ||
1625 | /* blue rect */ | |
1626 | sstfb_drawrect_XY(info, 50, 50, 50, 50, 0x001f, idx); | |
1627 | ||
1628 | /* green rect */ | |
1629 | sstfb_drawrect_XY(info, 100, 100, 80, 80, 0x07e0, idx); | |
1630 | ||
1631 | /* red rect */ | |
1632 | sstfb_drawrect_XY(info, 250, 250, 120, 100, 0xf800, idx); | |
1633 | } | |
1634 | ||
1635 | module_init(sstfb_init); | |
1636 | ||
1637 | #ifdef MODULE | |
1638 | module_exit(sstfb_exit); | |
1639 | #endif | |
1640 | ||
1641 | MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>"); | |
1642 | MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards"); | |
1643 | MODULE_LICENSE("GPL"); | |
1644 | ||
1645 | module_param(mem, int, 0); | |
1646 | MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)"); | |
1647 | module_param(vgapass, bool, 0); | |
1648 | MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)"); | |
1649 | module_param(clipping, bool, 0); | |
1650 | MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)"); | |
1651 | module_param(gfxclk, int, 0); | |
1652 | MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)"); | |
1653 | module_param(slowpci, bool, 0); | |
1654 | MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)"); |