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fbdev: sh_mobile_lcdc: Return display connection state in display_on
[linux-2.6-block.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
f1f60b5f
LP		 11#include <linux/atomic.h>
12#include <linux/backlight.h>
cfb4f5d1 13#include <linux/clk.h>
f1f60b5f 14#include <linux/console.h>
cfb4f5d1 15#include <linux/dma-mapping.h>
f1f60b5f
LP		 16#include <linux/delay.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
8564557a 19#include <linux/interrupt.h>
40331b21 20#include <linux/ioctl.h>
f1f60b5f
LP		 21#include <linux/kernel.h>
22#include <linux/mm.h>
355b200b 23#include <linux/module.h>
f1f60b5f
LP		 24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/slab.h>
27#include <linux/videodev2.h>
28#include <linux/vmalloc.h>
29
225c9a8d 30#include <video/sh_mobile_lcdc.h>
8a20974f 31#include <video/sh_mobile_meram.h>
cfb4f5d1 32
6de9edd5
GL		 33#include "sh_mobile_lcdcfb.h"
34
a6f15ade
PE		 35#define SIDE_B_OFFSET 0x1000
36#define MIRROR_OFFSET 0x2000
cfb4f5d1 37
d2ecbab5
GL		 38#define MAX_XRES 1920
39#define MAX_YRES 1080
cfb4f5d1 40
f1f60b5f
LP		 41struct sh_mobile_lcdc_priv {
42 void __iomem *base;
43 int irq;
44 atomic_t hw_usecnt;
45 struct device *dev;
46 struct clk *dot_clk;
47 unsigned long lddckr;
48 struct sh_mobile_lcdc_chan ch[2];
49 struct notifier_block notifier;
50 int started;
51 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
52 struct sh_mobile_meram_info *meram_dev;
53};
54
55/* -----------------------------------------------------------------------------
56 * Registers access
57 */
58
0246c471 59static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 60 [LDDCKPAT1R] = 0x400,
61 [LDDCKPAT2R] = 0x404,
62 [LDMT1R] = 0x418,
63 [LDMT2R] = 0x41c,
64 [LDMT3R] = 0x420,
65 [LDDFR] = 0x424,
66 [LDSM1R] = 0x428,
8564557a 67 [LDSM2R] = 0x42c,
cfb4f5d1 68 [LDSA1R] = 0x430,
53b50314 69 [LDSA2R] = 0x434,
cfb4f5d1
MD		 70 [LDMLSR] = 0x438,
71 [LDHCNR] = 0x448,
72 [LDHSYNR] = 0x44c,
73 [LDVLNR] = 0x450,
74 [LDVSYNR] = 0x454,
75 [LDPMR] = 0x460,
6011bdea 76 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 77};
78
0246c471 79static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 80 [LDDCKPAT1R] = 0x408,
81 [LDDCKPAT2R] = 0x40c,
82 [LDMT1R] = 0x600,
83 [LDMT2R] = 0x604,
84 [LDMT3R] = 0x608,
85 [LDDFR] = 0x60c,
86 [LDSM1R] = 0x610,
8564557a 87 [LDSM2R] = 0x614,
cfb4f5d1
MD		 88 [LDSA1R] = 0x618,
89 [LDMLSR] = 0x620,
90 [LDHCNR] = 0x624,
91 [LDHSYNR] = 0x628,
92 [LDVLNR] = 0x62c,
93 [LDVSYNR] = 0x630,
94 [LDPMR] = 0x63c,
95};
96
a6f15ade
PE		 97static bool banked(int reg_nr)
98{
99 switch (reg_nr) {
100 case LDMT1R:
101 case LDMT2R:
102 case LDMT3R:
103 case LDDFR:
104 case LDSM1R:
105 case LDSA1R:
53b50314 106 case LDSA2R:
a6f15ade
PE		 107 case LDMLSR:
108 case LDHCNR:
109 case LDHSYNR:
110 case LDVLNR:
111 case LDVSYNR:
112 return true;
113 }
114 return false;
115}
116
f1f60b5f
LP		 117static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
118{
119 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
120}
121
cfb4f5d1
MD		 122static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
123 int reg_nr, unsigned long data)
124{
125 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 126 if (banked(reg_nr))
127 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
128 SIDE_B_OFFSET);
129}
130
131static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
132 int reg_nr, unsigned long data)
133{
134 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
135 MIRROR_OFFSET);
cfb4f5d1
MD		 136}
137
138static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
139 int reg_nr)
140{
141 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
142}
143
144static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
145 unsigned long reg_offs, unsigned long data)
146{
147 iowrite32(data, priv->base + reg_offs);
148}
149
150static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
151 unsigned long reg_offs)
152{
153 return ioread32(priv->base + reg_offs);
154}
155
156static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
157 unsigned long reg_offs,
158 unsigned long mask, unsigned long until)
159{
160 while ((lcdc_read(priv, reg_offs) & mask) != until)
161 cpu_relax();
162}
163
f1f60b5f
LP		 164/* -----------------------------------------------------------------------------
165 * Clock management
166 */
167
168static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1 169{
f1f60b5f
LP		 170 if (atomic_inc_and_test(&priv->hw_usecnt)) {
171 if (priv->dot_clk)
172 clk_enable(priv->dot_clk);
173 pm_runtime_get_sync(priv->dev);
174 if (priv->meram_dev && priv->meram_dev->pdev)
175 pm_runtime_get_sync(&priv->meram_dev->pdev->dev);
176 }
cfb4f5d1
MD		 177}
178
f1f60b5f
LP		 179static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
180{
181 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
182 if (priv->meram_dev && priv->meram_dev->pdev)
183 pm_runtime_put_sync(&priv->meram_dev->pdev->dev);
184 pm_runtime_put(priv->dev);
185 if (priv->dot_clk)
186 clk_disable(priv->dot_clk);
187 }
188}
189
0a7f17aa
LP		 190static int sh_mobile_lcdc_setup_clocks(struct sh_mobile_lcdc_priv *priv,
191 int clock_source)
f1f60b5f 192{
4774c12a 193 struct clk *clk;
f1f60b5f
LP		 194 char *str;
195
196 switch (clock_source) {
197 case LCDC_CLK_BUS:
198 str = "bus_clk";
199 priv->lddckr = LDDCKR_ICKSEL_BUS;
200 break;
201 case LCDC_CLK_PERIPHERAL:
202 str = "peripheral_clk";
203 priv->lddckr = LDDCKR_ICKSEL_MIPI;
204 break;
205 case LCDC_CLK_EXTERNAL:
206 str = NULL;
207 priv->lddckr = LDDCKR_ICKSEL_HDMI;
208 break;
209 default:
210 return -EINVAL;
211 }
212
4774c12a
LP		 213 if (str == NULL)
214 return 0;
215
0a7f17aa 216 clk = clk_get(priv->dev, str);
4774c12a 217 if (IS_ERR(clk)) {
0a7f17aa 218 dev_err(priv->dev, "cannot get dot clock %s\n", str);
4774c12a 219 return PTR_ERR(clk);
f1f60b5f
LP		 220 }
221
4774c12a 222 priv->dot_clk = clk;
f1f60b5f
LP		 223 return 0;
224}
225
226/* -----------------------------------------------------------------------------
37c5dcc2 227 * Display, panel and deferred I/O
f1f60b5f
LP		 228 */
229
cfb4f5d1
MD		 230static void lcdc_sys_write_index(void *handle, unsigned long data)
231{
232 struct sh_mobile_lcdc_chan *ch = handle;
233
ce1c0b08
LP		 234 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT);
235 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
236 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
237 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
238 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 239}
240
241static void lcdc_sys_write_data(void *handle, unsigned long data)
242{
243 struct sh_mobile_lcdc_chan *ch = handle;
244
ce1c0b08
LP		 245 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW);
246 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
247 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
248 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
249 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 250}
251
252static unsigned long lcdc_sys_read_data(void *handle)
253{
254 struct sh_mobile_lcdc_chan *ch = handle;
255
ce1c0b08
LP		 256 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR);
257 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
258 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA |
259 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
cfb4f5d1 260 udelay(1);
ce1c0b08 261 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1 262
ce1c0b08 263 return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK;
cfb4f5d1
MD		 264}
265
266struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
267 lcdc_sys_write_index,
268 lcdc_sys_write_data,
269 lcdc_sys_read_data,
270};
271
1c6a307a
PM		 272static int sh_mobile_lcdc_sginit(struct fb_info *info,
273 struct list_head *pagelist)
274{
275 struct sh_mobile_lcdc_chan *ch = info->par;
276 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
277 struct page *page;
278 int nr_pages = 0;
279
280 sg_init_table(ch->sglist, nr_pages_max);
281
282 list_for_each_entry(page, pagelist, lru)
283 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
284
285 return nr_pages;
286}
287
8564557a
MD		 288static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
289 struct list_head *pagelist)
290{
291 struct sh_mobile_lcdc_chan *ch = info->par;
afaad83b 292 struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg.panel_cfg;
8564557a
MD		 293
294 /* enable clocks before accessing hardware */
295 sh_mobile_lcdc_clk_on(ch->lcdc);
296
5c1a56b5
PM		 297 /*
298 * It's possible to get here without anything on the pagelist via
299 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
300 * invocation. In the former case, the acceleration routines are
301 * stepped in to when using the framebuffer console causing the
302 * workqueue to be scheduled without any dirty pages on the list.
303 *
304 * Despite this, a panel update is still needed given that the
305 * acceleration routines have their own methods for writing in
306 * that still need to be updated.
307 *
308 * The fsync() and empty pagelist case could be optimized for,
309 * but we don't bother, as any application exhibiting such
310 * behaviour is fundamentally broken anyways.
311 */
312 if (!list_empty(pagelist)) {
313 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
314
315 /* trigger panel update */
316 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
afaad83b
LP		 317 if (panel->start_transfer)
318 panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 319 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
5c1a56b5 320 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4 321 } else {
afaad83b
LP		 322 if (panel->start_transfer)
323 panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 324 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
ef61aae4 325 }
8564557a
MD		 326}
327
328static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
329{
330 struct fb_deferred_io *fbdefio = info->fbdefio;
331
332 if (fbdefio)
333 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
334}
335
37c5dcc2
LP		 336static void sh_mobile_lcdc_display_on(struct sh_mobile_lcdc_chan *ch)
337{
afaad83b 338 struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg.panel_cfg;
37c5dcc2 339
9a2985e7 340 if (ch->tx_dev) {
458981c3
LP		 341 int ret;
342
343 ret = ch->tx_dev->ops->display_on(ch->tx_dev);
344 if (ret < 0)
9a2985e7 345 return;
458981c3
LP		 346
347 if (ret == SH_MOBILE_LCDC_DISPLAY_DISCONNECTED)
348 ch->info->state = FBINFO_STATE_SUSPENDED;
9a2985e7
LP		 349 }
350
37c5dcc2 351 /* HDMI must be enabled before LCDC configuration */
afaad83b
LP		 352 if (panel->display_on)
353 panel->display_on();
37c5dcc2
LP		 354}
355
356static void sh_mobile_lcdc_display_off(struct sh_mobile_lcdc_chan *ch)
357{
afaad83b 358 struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg.panel_cfg;
37c5dcc2 359
afaad83b
LP		 360 if (panel->display_off)
361 panel->display_off();
9a2985e7
LP		 362
363 if (ch->tx_dev)
364 ch->tx_dev->ops->display_off(ch->tx_dev);
37c5dcc2
LP		 365}
366
f1f60b5f
LP		 367/* -----------------------------------------------------------------------------
368 * Format helpers
369 */
370
371static int sh_mobile_format_fourcc(const struct fb_var_screeninfo *var)
372{
373 if (var->grayscale > 1)
374 return var->grayscale;
375
376 switch (var->bits_per_pixel) {
377 case 16:
378 return V4L2_PIX_FMT_RGB565;
379 case 24:
380 return V4L2_PIX_FMT_BGR24;
381 case 32:
382 return V4L2_PIX_FMT_BGR32;
383 default:
384 return 0;
385 }
386}
387
388static int sh_mobile_format_is_fourcc(const struct fb_var_screeninfo *var)
389{
390 return var->grayscale > 1;
391}
392
393static bool sh_mobile_format_is_yuv(const struct fb_var_screeninfo *var)
394{
395 if (var->grayscale <= 1)
396 return false;
397
398 switch (var->grayscale) {
399 case V4L2_PIX_FMT_NV12:
400 case V4L2_PIX_FMT_NV21:
401 case V4L2_PIX_FMT_NV16:
402 case V4L2_PIX_FMT_NV61:
403 case V4L2_PIX_FMT_NV24:
404 case V4L2_PIX_FMT_NV42:
405 return true;
406
407 default:
408 return false;
409 }
410}
411
412/* -----------------------------------------------------------------------------
413 * Start, stop and IRQ
414 */
415
8564557a
MD		 416static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
417{
418 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 419 struct sh_mobile_lcdc_chan *ch;
9dd38819 420 unsigned long ldintr;
2feb075a
MD		 421 int is_sub;
422 int k;
8564557a 423
dc48665f
LP		 424 /* Acknowledge interrupts and disable further VSYNC End IRQs. */
425 ldintr = lcdc_read(priv, _LDINTR);
426 lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE);
8564557a 427
2feb075a 428 /* figure out if this interrupt is for main or sub lcd */
ce1c0b08 429 is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0;
2feb075a 430
9dd38819 431 /* wake up channel and disable clocks */
2feb075a
MD		 432 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
433 ch = &priv->ch[k];
434
435 if (!ch->enabled)
436 continue;
437
dc48665f 438 /* Frame End */
9dd38819
PE		 439 if (ldintr & LDINTR_FS) {
440 if (is_sub == lcdc_chan_is_sublcd(ch)) {
441 ch->frame_end = 1;
442 wake_up(&ch->frame_end_wait);
2feb075a 443
9dd38819
PE		 444 sh_mobile_lcdc_clk_off(priv);
445 }
446 }
447
448 /* VSYNC End */
40331b21
PE		 449 if (ldintr & LDINTR_VES)
450 complete(&ch->vsync_completion);
2feb075a
MD		 451 }
452
8564557a
MD		 453 return IRQ_HANDLED;
454}
455
cfb4f5d1
MD		 456static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
457 int start)
458{
459 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
460 int k;
461
462 /* start or stop the lcdc */
463 if (start)
ce1c0b08 464 lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO);
cfb4f5d1 465 else
ce1c0b08 466 lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO);
cfb4f5d1
MD		 467
468 /* wait until power is applied/stopped on all channels */
469 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
470 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
471 while (1) {
ce1c0b08
LP		 472 tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
473 & LDPMR_LPS;
474 if (start && tmp == LDPMR_LPS)
cfb4f5d1
MD		 475 break;
476 if (!start && tmp == 0)
477 break;
478 cpu_relax();
479 }
480
481 if (!start)
482 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
483}
484
6011bdea
GL		 485static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
486{
1c120deb
GL		 487 struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
488 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 489 u32 tmp;
490
491 tmp = ch->ldmt1r_value;
ce1c0b08
LP		 492 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL;
493 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL;
494 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0;
495 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0;
496 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0;
497 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0;
498 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0;
6011bdea
GL		 499 lcdc_write_chan(ch, LDMT1R, tmp);
500
501 /* setup SYS bus */
502 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
503 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
504
505 /* horizontal configuration */
1c120deb
GL		 506 h_total = display_var->xres + display_var->hsync_len +
507 display_var->left_margin + display_var->right_margin;
6011bdea 508 tmp = h_total / 8; /* HTCN */
1c120deb 509 tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 510 lcdc_write_chan(ch, LDHCNR, tmp);
511
1c120deb 512 hsync_pos = display_var->xres + display_var->right_margin;
6011bdea 513 tmp = hsync_pos / 8; /* HSYNP */
1c120deb 514 tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 515 lcdc_write_chan(ch, LDHSYNR, tmp);
516
517 /* vertical configuration */
1c120deb
GL		 518 tmp = display_var->yres + display_var->vsync_len +
519 display_var->upper_margin + display_var->lower_margin; /* VTLN */
520 tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
6011bdea
GL		 521 lcdc_write_chan(ch, LDVLNR, tmp);
522
1c120deb
GL		 523 tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
524 tmp |= display_var->vsync_len << 16; /* VSYNW */
6011bdea
GL		 525 lcdc_write_chan(ch, LDVSYNR, tmp);
526
527 /* Adjust horizontal synchronisation for HDMI */
1c120deb
GL		 528 display_h_total = display_var->xres + display_var->hsync_len +
529 display_var->left_margin + display_var->right_margin;
530 tmp = ((display_var->xres & 7) << 24) |
531 ((display_h_total & 7) << 16) |
532 ((display_var->hsync_len & 7) << 8) |
41e583c2 533 (hsync_pos & 7);
6011bdea
GL		 534 lcdc_write_chan(ch, LDHAJR, tmp);
535}
536
9a217e34
LP		 537/*
538 * __sh_mobile_lcdc_start - Configure and tart the LCDC
539 * @priv: LCDC device
540 *
541 * Configure all enabled channels and start the LCDC device. All external
542 * devices (clocks, MERAM, panels, ...) are not touched by this function.
543 */
544static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1
MD		 545{
546 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1 547 unsigned long tmp;
9a217e34 548 int k, m;
8564557a 549
9a217e34
LP		 550 /* Enable LCDC channels. Read data from external memory, avoid using the
551 * BEU for now.
552 */
553 lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled);
cfb4f5d1 554
9a217e34 555 /* Stop the LCDC first and disable all interrupts. */
cfb4f5d1 556 sh_mobile_lcdc_start_stop(priv, 0);
9a217e34 557 lcdc_write(priv, _LDINTR, 0);
cfb4f5d1 558
9a217e34 559 /* Configure power supply, dot clocks and start them. */
cfb4f5d1
MD		 560 tmp = priv->lddckr;
561 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
562 ch = &priv->ch[k];
9a217e34 563 if (!ch->enabled)
cfb4f5d1
MD		 564 continue;
565
9a217e34
LP		 566 /* Power supply */
567 lcdc_write_chan(ch, LDPMR, 0);
568
cfb4f5d1
MD		 569 m = ch->cfg.clock_divider;
570 if (!m)
571 continue;
572
505c7de5
LP		 573 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider
574 * denominator.
575 */
576 lcdc_write_chan(ch, LDDCKPAT1R, 0);
577 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
578
cfb4f5d1 579 if (m == 1)
ce1c0b08 580 m = LDDCKR_MOSEL;
cfb4f5d1 581 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
cfb4f5d1
MD		 582 }
583
584 lcdc_write(priv, _LDDCKR, tmp);
cfb4f5d1
MD		 585 lcdc_write(priv, _LDDCKSTPR, 0);
586 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
587
9a217e34 588 /* Setup geometry, format, frame buffer memory and operation mode. */
cfb4f5d1
MD		 589 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
590 ch = &priv->ch[k];
cfb4f5d1
MD		 591 if (!ch->enabled)
592 continue;
593
6011bdea 594 sh_mobile_lcdc_geometry(ch);
cfb4f5d1 595
edd153a3
LP		 596 switch (sh_mobile_format_fourcc(&ch->info->var)) {
597 case V4L2_PIX_FMT_RGB565:
598 tmp = LDDFR_PKF_RGB16;
599 break;
600 case V4L2_PIX_FMT_BGR24:
601 tmp = LDDFR_PKF_RGB24;
602 break;
603 case V4L2_PIX_FMT_BGR32:
604 tmp = LDDFR_PKF_ARGB32;
605 break;
606 case V4L2_PIX_FMT_NV12:
607 case V4L2_PIX_FMT_NV21:
608 tmp = LDDFR_CC | LDDFR_YF_420;
609 break;
610 case V4L2_PIX_FMT_NV16:
611 case V4L2_PIX_FMT_NV61:
612 tmp = LDDFR_CC | LDDFR_YF_422;
613 break;
614 case V4L2_PIX_FMT_NV24:
615 case V4L2_PIX_FMT_NV42:
616 tmp = LDDFR_CC | LDDFR_YF_444;
617 break;
618 }
619
620 if (sh_mobile_format_is_yuv(&ch->info->var)) {
621 switch (ch->info->var.colorspace) {
622 case V4L2_COLORSPACE_REC709:
623 tmp |= LDDFR_CF1;
53b50314 624 break;
edd153a3
LP		 625 case V4L2_COLORSPACE_JPEG:
626 tmp |= LDDFR_CF0;
53b50314
DHG		 627 break;
628 }
417d4827 629 }
7caa4342 630
9a217e34
LP		 631 lcdc_write_chan(ch, LDDFR, tmp);
632 lcdc_write_chan(ch, LDMLSR, ch->pitch);
633 lcdc_write_chan(ch, LDSA1R, ch->base_addr_y);
edd153a3 634 if (sh_mobile_format_is_yuv(&ch->info->var))
9a217e34 635 lcdc_write_chan(ch, LDSA2R, ch->base_addr_c);
7caa4342 636
9a217e34
LP		 637 /* When using deferred I/O mode, configure the LCDC for one-shot
638 * operation and enable the frame end interrupt. Otherwise use
639 * continuous read mode.
640 */
641 if (ch->ldmt1r_value & LDMT1R_IFM &&
642 ch->cfg.sys_bus_cfg.deferred_io_msec) {
643 lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
644 lcdc_write(priv, _LDINTR, LDINTR_FE);
645 } else {
646 lcdc_write_chan(ch, LDSM1R, 0);
647 }
648 }
7caa4342 649
9a217e34 650 /* Word and long word swap. */
edd153a3
LP		 651 switch (sh_mobile_format_fourcc(&priv->ch[0].info->var)) {
652 case V4L2_PIX_FMT_RGB565:
653 case V4L2_PIX_FMT_NV21:
654 case V4L2_PIX_FMT_NV61:
655 case V4L2_PIX_FMT_NV42:
656 tmp = LDDDSR_LS | LDDDSR_WS;
657 break;
658 case V4L2_PIX_FMT_BGR24:
659 case V4L2_PIX_FMT_NV12:
660 case V4L2_PIX_FMT_NV16:
661 case V4L2_PIX_FMT_NV24:
9a217e34 662 tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
edd153a3
LP		 663 break;
664 case V4L2_PIX_FMT_BGR32:
665 default:
666 tmp = LDDDSR_LS;
667 break;
9a217e34
LP		 668 }
669 lcdc_write(priv, _LDDDSR, tmp);
7caa4342 670
9a217e34
LP		 671 /* Enable the display output. */
672 lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
673 sh_mobile_lcdc_start_stop(priv, 1);
674 priv->started = 1;
675}
cfb4f5d1 676
9a217e34
LP		 677static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
678{
679 struct sh_mobile_meram_info *mdev = priv->meram_dev;
9a217e34
LP		 680 struct sh_mobile_lcdc_chan *ch;
681 unsigned long tmp;
682 int ret;
683 int k;
cfb4f5d1 684
9a217e34
LP		 685 /* enable clocks before accessing the hardware */
686 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
687 if (priv->ch[k].enabled)
688 sh_mobile_lcdc_clk_on(priv);
689 }
8564557a 690
9a217e34
LP		 691 /* reset */
692 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
693 lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
8564557a 694
9a217e34 695 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
afaad83b 696 struct sh_mobile_lcdc_panel_cfg *panel;
8564557a 697
37c5dcc2 698 ch = &priv->ch[k];
9a217e34
LP		 699 if (!ch->enabled)
700 continue;
701
afaad83b
LP		 702 panel = &ch->cfg.panel_cfg;
703 if (panel->setup_sys) {
704 ret = panel->setup_sys(ch, &sh_mobile_lcdc_sys_bus_ops);
9a217e34
LP		 705 if (ret)
706 return ret;
8564557a 707 }
cfb4f5d1
MD		 708 }
709
9a217e34
LP		 710 /* Compute frame buffer base address and pitch for each channel. */
711 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
712 struct sh_mobile_meram_cfg *cfg;
713 int pixelformat;
cfb4f5d1 714
9a217e34
LP		 715 ch = &priv->ch[k];
716 if (!ch->enabled)
717 continue;
cfb4f5d1 718
9a217e34
LP		 719 ch->base_addr_y = ch->info->fix.smem_start;
720 ch->base_addr_c = ch->base_addr_y
721 + ch->info->var.xres
722 * ch->info->var.yres_virtual;
723 ch->pitch = ch->info->fix.line_length;
724
725 /* Enable MERAM if possible. */
726 cfg = ch->cfg.meram_cfg;
727 if (mdev == NULL || mdev->ops == NULL || cfg == NULL)
728 continue;
729
730 /* we need to de-init configured ICBs before we can
731 * re-initialize them.
732 */
733 if (ch->meram_enabled) {
734 mdev->ops->meram_unregister(mdev, cfg);
735 ch->meram_enabled = 0;
736 }
737
edd153a3
LP		 738 switch (sh_mobile_format_fourcc(&ch->info->var)) {
739 case V4L2_PIX_FMT_NV12:
740 case V4L2_PIX_FMT_NV21:
741 case V4L2_PIX_FMT_NV16:
742 case V4L2_PIX_FMT_NV61:
9a217e34 743 pixelformat = SH_MOBILE_MERAM_PF_NV;
edd153a3
LP		 744 break;
745 case V4L2_PIX_FMT_NV24:
746 case V4L2_PIX_FMT_NV42:
747 pixelformat = SH_MOBILE_MERAM_PF_NV24;
748 break;
749 case V4L2_PIX_FMT_RGB565:
750 case V4L2_PIX_FMT_BGR24:
751 case V4L2_PIX_FMT_BGR32:
752 default:
753 pixelformat = SH_MOBILE_MERAM_PF_RGB;
754 break;
755 }
9a217e34
LP		 756
757 ret = mdev->ops->meram_register(mdev, cfg, ch->pitch,
758 ch->info->var.yres, pixelformat,
759 ch->base_addr_y, ch->base_addr_c,
760 &ch->base_addr_y, &ch->base_addr_c,
761 &ch->pitch);
762 if (!ret)
763 ch->meram_enabled = 1;
764 }
765
766 /* Start the LCDC. */
767 __sh_mobile_lcdc_start(priv);
768
769 /* Setup deferred I/O, tell the board code to enable the panels, and
770 * turn backlight on.
771 */
cfb4f5d1
MD		 772 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
773 ch = &priv->ch[k];
21bc1f02
MD		 774 if (!ch->enabled)
775 continue;
776
9a217e34
LP		 777 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
778 if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
779 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
780 ch->defio.delay = msecs_to_jiffies(tmp);
781 ch->info->fbdefio = &ch->defio;
782 fb_deferred_io_init(ch->info);
783 }
784
37c5dcc2 785 sh_mobile_lcdc_display_on(ch);
3b0fd9d7
AC		 786
787 if (ch->bl) {
788 ch->bl->props.power = FB_BLANK_UNBLANK;
789 backlight_update_status(ch->bl);
790 }
cfb4f5d1
MD		 791 }
792
793 return 0;
794}
795
796static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
797{
798 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD		 799 int k;
800
2feb075a 801 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 802 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
803 ch = &priv->ch[k];
21bc1f02
MD		 804 if (!ch->enabled)
805 continue;
8564557a 806
2feb075a
MD		 807 /* deferred io mode:
808 * flush frame, and wait for frame end interrupt
809 * clean up deferred io and enable clock
810 */
5ef6b505 811 if (ch->info && ch->info->fbdefio) {
2feb075a 812 ch->frame_end = 0;
e33afddc 813 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 814 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 815 fb_deferred_io_cleanup(ch->info);
816 ch->info->fbdefio = NULL;
2feb075a 817 sh_mobile_lcdc_clk_on(priv);
8564557a 818 }
2feb075a 819
3b0fd9d7
AC		 820 if (ch->bl) {
821 ch->bl->props.power = FB_BLANK_POWERDOWN;
822 backlight_update_status(ch->bl);
823 }
824
37c5dcc2 825 sh_mobile_lcdc_display_off(ch);
7caa4342
D		 826
827 /* disable the meram */
828 if (ch->meram_enabled) {
829 struct sh_mobile_meram_cfg *cfg;
830 struct sh_mobile_meram_info *mdev;
831 cfg = ch->cfg.meram_cfg;
832 mdev = priv->meram_dev;
833 mdev->ops->meram_unregister(mdev, cfg);
834 ch->meram_enabled = 0;
835 }
836
cfb4f5d1
MD		 837 }
838
839 /* stop the lcdc */
8e9bb19e
MD		 840 if (priv->started) {
841 sh_mobile_lcdc_start_stop(priv, 0);
842 priv->started = 0;
843 }
b51339ff 844
8564557a
MD		 845 /* stop clocks */
846 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
847 if (priv->ch[k].enabled)
848 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 849}
850
f1f60b5f
LP		 851/* -----------------------------------------------------------------------------
852 * Frame buffer operations
853 */
cfb4f5d1
MD		 854
855static int sh_mobile_lcdc_setcolreg(u_int regno,
856 u_int red, u_int green, u_int blue,
857 u_int transp, struct fb_info *info)
858{
859 u32 *palette = info->pseudo_palette;
860
861 if (regno >= PALETTE_NR)
862 return -EINVAL;
863
864 /* only FB_VISUAL_TRUECOLOR supported */
865
866 red >>= 16 - info->var.red.length;
867 green >>= 16 - info->var.green.length;
868 blue >>= 16 - info->var.blue.length;
869 transp >>= 16 - info->var.transp.length;
870
871 palette[regno] = (red << info->var.red.offset) |
872 (green << info->var.green.offset) |
873 (blue << info->var.blue.offset) |
874 (transp << info->var.transp.offset);
875
876 return 0;
877}
878
879static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
880 .id = "SH Mobile LCDC",
881 .type = FB_TYPE_PACKED_PIXELS,
882 .visual = FB_VISUAL_TRUECOLOR,
883 .accel = FB_ACCEL_NONE,
9dd38819
PE		 884 .xpanstep = 0,
885 .ypanstep = 1,
886 .ywrapstep = 0,
edd153a3 887 .capabilities = FB_CAP_FOURCC,
cfb4f5d1
MD		 888};
889
8564557a
MD		 890static void sh_mobile_lcdc_fillrect(struct fb_info *info,
891 const struct fb_fillrect *rect)
892{
893 sys_fillrect(info, rect);
894 sh_mobile_lcdc_deferred_io_touch(info);
895}
896
897static void sh_mobile_lcdc_copyarea(struct fb_info *info,
898 const struct fb_copyarea *area)
899{
900 sys_copyarea(info, area);
901 sh_mobile_lcdc_deferred_io_touch(info);
902}
903
904static void sh_mobile_lcdc_imageblit(struct fb_info *info,
905 const struct fb_image *image)
906{
907 sys_imageblit(info, image);
908 sh_mobile_lcdc_deferred_io_touch(info);
909}
910
9dd38819
PE		 911static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
912 struct fb_info *info)
913{
914 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 915 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
916 unsigned long ldrcntr;
917 unsigned long new_pan_offset;
53b50314
DHG		 918 unsigned long base_addr_y, base_addr_c;
919 unsigned long c_offset;
edd153a3 920 bool yuv = sh_mobile_format_is_yuv(&info->var);
92e1f9a7 921
edd153a3 922 if (!yuv)
dc1d5ada
LP		 923 new_pan_offset = var->yoffset * info->fix.line_length
924 + var->xoffset * (info->var.bits_per_pixel / 8);
53b50314 925 else
dc1d5ada
LP		 926 new_pan_offset = var->yoffset * info->fix.line_length
927 + var->xoffset;
9dd38819 928
92e1f9a7 929 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 930 return 0; /* No change, do nothing */
931
92e1f9a7 932 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 933
92e1f9a7 934 /* Set the source address for the next refresh */
53b50314 935 base_addr_y = ch->dma_handle + new_pan_offset;
edd153a3 936 if (yuv) {
53b50314 937 /* Set y offset */
dc1d5ada
LP		 938 c_offset = var->yoffset * info->fix.line_length
939 * (info->var.bits_per_pixel - 8) / 8;
940 base_addr_c = ch->dma_handle
941 + info->var.xres * info->var.yres_virtual
942 + c_offset;
53b50314 943 /* Set x offset */
edd153a3 944 if (sh_mobile_format_fourcc(&info->var) == V4L2_PIX_FMT_NV24)
53b50314
DHG		 945 base_addr_c += 2 * var->xoffset;
946 else
947 base_addr_c += var->xoffset;
49d79ba2 948 }
53b50314 949
49d79ba2 950 if (ch->meram_enabled) {
7caa4342
D		 951 struct sh_mobile_meram_cfg *cfg;
952 struct sh_mobile_meram_info *mdev;
7caa4342
D		 953 int ret;
954
955 cfg = ch->cfg.meram_cfg;
956 mdev = priv->meram_dev;
957 ret = mdev->ops->meram_update(mdev, cfg,
958 base_addr_y, base_addr_c,
49d79ba2 959 &base_addr_y, &base_addr_c);
7caa4342
D		 960 if (ret)
961 return ret;
49d79ba2 962 }
7caa4342 963
49d79ba2
LP		 964 ch->base_addr_y = base_addr_y;
965 ch->base_addr_c = base_addr_c;
7caa4342 966
49d79ba2 967 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
edd153a3 968 if (yuv)
49d79ba2 969 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
53b50314 970
92e1f9a7
PE		 971 if (lcdc_chan_is_sublcd(ch))
972 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
973 else
974 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
975
976 ch->pan_offset = new_pan_offset;
977
978 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 979
980 return 0;
981}
982
40331b21
PE		 983static int sh_mobile_wait_for_vsync(struct fb_info *info)
984{
985 struct sh_mobile_lcdc_chan *ch = info->par;
986 unsigned long ldintr;
987 int ret;
988
dc48665f
LP		 989 /* Enable VSync End interrupt and be careful not to acknowledge any
990 * pending interrupt.
991 */
40331b21 992 ldintr = lcdc_read(ch->lcdc, _LDINTR);
dc48665f 993 ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK;
40331b21
PE		 994 lcdc_write(ch->lcdc, _LDINTR, ldintr);
995
996 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
997 msecs_to_jiffies(100));
998 if (!ret)
999 return -ETIMEDOUT;
1000
1001 return 0;
1002}
1003
1004static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
1005 unsigned long arg)
1006{
1007 int retval;
1008
1009 switch (cmd) {
1010 case FBIO_WAITFORVSYNC:
1011 retval = sh_mobile_wait_for_vsync(info);
1012 break;
1013
1014 default:
1015 retval = -ENOIOCTLCMD;
1016 break;
1017 }
1018 return retval;
1019}
1020
dd210503
GL		 1021static void sh_mobile_fb_reconfig(struct fb_info *info)
1022{
1023 struct sh_mobile_lcdc_chan *ch = info->par;
1024 struct fb_videomode mode1, mode2;
1025 struct fb_event event;
1026 int evnt = FB_EVENT_MODE_CHANGE_ALL;
1027
1028 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1029 /* More framebuffer users are active */
1030 return;
1031
1032 fb_var_to_videomode(&mode1, &ch->display_var);
1033 fb_var_to_videomode(&mode2, &info->var);
1034
1035 if (fb_mode_is_equal(&mode1, &mode2))
1036 return;
1037
1038 /* Display has been re-plugged, framebuffer is free now, reconfigure */
1039 if (fb_set_var(info, &ch->display_var) < 0)
1040 /* Couldn't reconfigure, hopefully, can continue as before */
1041 return;
1042
dd210503
GL		 1043 /*
1044 * fb_set_var() calls the notifier change internally, only if
1045 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
1046 * user event, we have to call the chain ourselves.
1047 */
1048 event.info = info;
cc267ec5 1049 event.data = &mode1;
dd210503
GL		 1050 fb_notifier_call_chain(evnt, &event);
1051}
1052
1053/*
1054 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1055 * user == 1, or with console sem held, if user == 0.
1056 */
1057static int sh_mobile_release(struct fb_info *info, int user)
1058{
1059 struct sh_mobile_lcdc_chan *ch = info->par;
1060
1061 mutex_lock(&ch->open_lock);
1062 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1063
1064 ch->use_count--;
1065
1066 /* Nothing to reconfigure, when called from fbcon */
1067 if (user) {
ac751efa 1068 console_lock();
dd210503 1069 sh_mobile_fb_reconfig(info);
ac751efa 1070 console_unlock();
dd210503
GL		 1071 }
1072
1073 mutex_unlock(&ch->open_lock);
1074
1075 return 0;
1076}
1077
1078static int sh_mobile_open(struct fb_info *info, int user)
1079{
1080 struct sh_mobile_lcdc_chan *ch = info->par;
1081
1082 mutex_lock(&ch->open_lock);
1083 ch->use_count++;
1084
1085 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1086 mutex_unlock(&ch->open_lock);
1087
1088 return 0;
1089}
1090
1091static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1092{
1093 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1094 struct sh_mobile_lcdc_priv *p = ch->lcdc;
03862194
LP		 1095 unsigned int best_dist = (unsigned int)-1;
1096 unsigned int best_xres = 0;
1097 unsigned int best_yres = 0;
1098 unsigned int i;
dd210503 1099
03862194 1100 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
dd210503 1101 return -EINVAL;
03862194
LP		 1102
1103 /* If board code provides us with a list of available modes, make sure
1104 * we use one of them. Find the mode closest to the requested one. The
1105 * distance between two modes is defined as the size of the
1106 * non-overlapping parts of the two rectangles.
1107 */
1108 for (i = 0; i < ch->cfg.num_cfg; ++i) {
1109 const struct fb_videomode *mode = &ch->cfg.lcd_cfg[i];
1110 unsigned int dist;
1111
1112 /* We can only round up. */
1113 if (var->xres > mode->xres || var->yres > mode->yres)
1114 continue;
1115
1116 dist = var->xres * var->yres + mode->xres * mode->yres
1117 - 2 * min(var->xres, mode->xres)
1118 * min(var->yres, mode->yres);
1119
1120 if (dist < best_dist) {
1121 best_xres = mode->xres;
1122 best_yres = mode->yres;
1123 best_dist = dist;
1124 }
dd210503 1125 }
417d4827 1126
03862194
LP		 1127 /* If no available mode can be used, return an error. */
1128 if (ch->cfg.num_cfg != 0) {
1129 if (best_dist == (unsigned int)-1)
1130 return -EINVAL;
1131
1132 var->xres = best_xres;
1133 var->yres = best_yres;
1134 }
1135
1136 /* Make sure the virtual resolution is at least as big as the visible
1137 * resolution.
1138 */
1139 if (var->xres_virtual < var->xres)
1140 var->xres_virtual = var->xres;
1141 if (var->yres_virtual < var->yres)
1142 var->yres_virtual = var->yres;
1143
edd153a3
LP		 1144 if (sh_mobile_format_is_fourcc(var)) {
1145 switch (var->grayscale) {
1146 case V4L2_PIX_FMT_NV12:
1147 case V4L2_PIX_FMT_NV21:
1148 var->bits_per_pixel = 12;
1149 break;
1150 case V4L2_PIX_FMT_RGB565:
1151 case V4L2_PIX_FMT_NV16:
1152 case V4L2_PIX_FMT_NV61:
1153 var->bits_per_pixel = 16;
1154 break;
1155 case V4L2_PIX_FMT_BGR24:
1156 case V4L2_PIX_FMT_NV24:
1157 case V4L2_PIX_FMT_NV42:
1158 var->bits_per_pixel = 24;
1159 break;
1160 case V4L2_PIX_FMT_BGR32:
1161 var->bits_per_pixel = 32;
1162 break;
1163 default:
1164 return -EINVAL;
1165 }
1166
1167 /* Default to RGB and JPEG color-spaces for RGB and YUV formats
1168 * respectively.
1169 */
1170 if (!sh_mobile_format_is_yuv(var))
1171 var->colorspace = V4L2_COLORSPACE_SRGB;
1172 else if (var->colorspace != V4L2_COLORSPACE_REC709)
1173 var->colorspace = V4L2_COLORSPACE_JPEG;
1174 } else {
1175 if (var->bits_per_pixel <= 16) { /* RGB 565 */
1176 var->bits_per_pixel = 16;
1177 var->red.offset = 11;
1178 var->red.length = 5;
1179 var->green.offset = 5;
1180 var->green.length = 6;
1181 var->blue.offset = 0;
1182 var->blue.length = 5;
1183 var->transp.offset = 0;
1184 var->transp.length = 0;
1185 } else if (var->bits_per_pixel <= 24) { /* RGB 888 */
1186 var->bits_per_pixel = 24;
1187 var->red.offset = 16;
1188 var->red.length = 8;
1189 var->green.offset = 8;
1190 var->green.length = 8;
1191 var->blue.offset = 0;
1192 var->blue.length = 8;
1193 var->transp.offset = 0;
1194 var->transp.length = 0;
1195 } else if (var->bits_per_pixel <= 32) { /* RGBA 888 */
1196 var->bits_per_pixel = 32;
1197 var->red.offset = 16;
1198 var->red.length = 8;
1199 var->green.offset = 8;
1200 var->green.length = 8;
1201 var->blue.offset = 0;
1202 var->blue.length = 8;
1203 var->transp.offset = 24;
1204 var->transp.length = 8;
1205 } else
1206 return -EINVAL;
417d4827 1207
edd153a3
LP		 1208 var->red.msb_right = 0;
1209 var->green.msb_right = 0;
1210 var->blue.msb_right = 0;
1211 var->transp.msb_right = 0;
1212 }
03862194
LP		 1213
1214 /* Make sure we don't exceed our allocated memory. */
1215 if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 >
1216 info->fix.smem_len)
1217 return -EINVAL;
1218
edd153a3
LP		 1219 /* only accept the forced_fourcc for dual channel configurations */
1220 if (p->forced_fourcc &&
1221 p->forced_fourcc != sh_mobile_format_fourcc(var))
417d4827 1222 return -EINVAL;
417d4827 1223
dd210503
GL		 1224 return 0;
1225}
40331b21 1226
ed5bebf2
LP		 1227static int sh_mobile_set_par(struct fb_info *info)
1228{
1229 struct sh_mobile_lcdc_chan *ch = info->par;
91fba48d 1230 u32 line_length = info->fix.line_length;
ed5bebf2
LP		 1231 int ret;
1232
1233 sh_mobile_lcdc_stop(ch->lcdc);
91fba48d 1234
edd153a3 1235 if (sh_mobile_format_is_yuv(&info->var))
91fba48d
LP		 1236 info->fix.line_length = info->var.xres;
1237 else
1238 info->fix.line_length = info->var.xres
1239 * info->var.bits_per_pixel / 8;
1240
ed5bebf2 1241 ret = sh_mobile_lcdc_start(ch->lcdc);
91fba48d 1242 if (ret < 0) {
ed5bebf2 1243 dev_err(info->dev, "%s: unable to restart LCDC\n", __func__);
91fba48d
LP		 1244 info->fix.line_length = line_length;
1245 }
ed5bebf2 1246
edd153a3
LP		 1247 if (sh_mobile_format_is_fourcc(&info->var)) {
1248 info->fix.type = FB_TYPE_FOURCC;
1249 info->fix.visual = FB_VISUAL_FOURCC;
1250 } else {
1251 info->fix.type = FB_TYPE_PACKED_PIXELS;
1252 info->fix.visual = FB_VISUAL_TRUECOLOR;
1253 }
1254
ed5bebf2
LP		 1255 return ret;
1256}
1257
8857b9aa
AC		 1258/*
1259 * Screen blanking. Behavior is as follows:
1260 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
1261 * FB_BLANK_NORMAL: screen blanked, clocks enabled
1262 * FB_BLANK_VSYNC,
1263 * FB_BLANK_HSYNC,
1264 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
1265 */
1266static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
1267{
1268 struct sh_mobile_lcdc_chan *ch = info->par;
1269 struct sh_mobile_lcdc_priv *p = ch->lcdc;
1270
1271 /* blank the screen? */
1272 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
1273 struct fb_fillrect rect = {
1274 .width = info->var.xres,
1275 .height = info->var.yres,
1276 };
1277 sh_mobile_lcdc_fillrect(info, &rect);
1278 }
1279 /* turn clocks on? */
1280 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
1281 sh_mobile_lcdc_clk_on(p);
1282 }
1283 /* turn clocks off? */
1284 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
1285 /* make sure the screen is updated with the black fill before
1286 * switching the clocks off. one vsync is not enough since
1287 * blanking may occur in the middle of a refresh. deferred io
1288 * mode will reenable the clocks and update the screen in time,
1289 * so it does not need this. */
1290 if (!info->fbdefio) {
1291 sh_mobile_wait_for_vsync(info);
1292 sh_mobile_wait_for_vsync(info);
1293 }
1294 sh_mobile_lcdc_clk_off(p);
1295 }
1296
1297 ch->blank_status = blank;
1298 return 0;
1299}
1300
cfb4f5d1 1301static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 1302 .owner = THIS_MODULE,
cfb4f5d1 1303 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 1304 .fb_read = fb_sys_read,
1305 .fb_write = fb_sys_write,
8564557a
MD		 1306 .fb_fillrect = sh_mobile_lcdc_fillrect,
1307 .fb_copyarea = sh_mobile_lcdc_copyarea,
1308 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 1309 .fb_blank = sh_mobile_lcdc_blank,
9dd38819 1310 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 1311 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL		 1312 .fb_open = sh_mobile_open,
1313 .fb_release = sh_mobile_release,
1314 .fb_check_var = sh_mobile_check_var,
ed5bebf2 1315 .fb_set_par = sh_mobile_set_par,
cfb4f5d1
MD		 1316};
1317
f1f60b5f
LP		 1318/* -----------------------------------------------------------------------------
1319 * Backlight
1320 */
1321
3b0fd9d7
AC		 1322static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
1323{
1324 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
3b0fd9d7
AC		 1325 int brightness = bdev->props.brightness;
1326
1327 if (bdev->props.power != FB_BLANK_UNBLANK ||
1328 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
1329 brightness = 0;
1330
43059b0f 1331 return ch->cfg.bl_info.set_brightness(brightness);
3b0fd9d7
AC		 1332}
1333
1334static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
1335{
1336 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
3b0fd9d7 1337
43059b0f 1338 return ch->cfg.bl_info.get_brightness();
3b0fd9d7
AC		 1339}
1340
1341static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
1342 struct fb_info *info)
1343{
1344 return (info->bl_dev == bdev);
1345}
1346
1347static struct backlight_ops sh_mobile_lcdc_bl_ops = {
1348 .options = BL_CORE_SUSPENDRESUME,
1349 .update_status = sh_mobile_lcdc_update_bl,
1350 .get_brightness = sh_mobile_lcdc_get_brightness,
1351 .check_fb = sh_mobile_lcdc_check_fb,
1352};
1353
1354static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
1355 struct sh_mobile_lcdc_chan *ch)
1356{
1357 struct backlight_device *bl;
1358
1359 bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
1360 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 1361 if (IS_ERR(bl)) {
1362 dev_err(parent, "unable to register backlight device: %ld\n",
1363 PTR_ERR(bl));
3b0fd9d7
AC		 1364 return NULL;
1365 }
1366
1367 bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
1368 bl->props.brightness = bl->props.max_brightness;
1369 backlight_update_status(bl);
1370
1371 return bl;
1372}
1373
1374static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
1375{
1376 backlight_device_unregister(bdev);
1377}
1378
f1f60b5f
LP		 1379/* -----------------------------------------------------------------------------
1380 * Power management
1381 */
1382
2feb075a
MD		 1383static int sh_mobile_lcdc_suspend(struct device *dev)
1384{
1385 struct platform_device *pdev = to_platform_device(dev);
1386
1387 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
1388 return 0;
1389}
1390
1391static int sh_mobile_lcdc_resume(struct device *dev)
1392{
1393 struct platform_device *pdev = to_platform_device(dev);
1394
1395 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
1396}
1397
0246c471
MD		 1398static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
1399{
1400 struct platform_device *pdev = to_platform_device(dev);
2427bb24 1401 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
0246c471
MD		 1402
1403 /* turn off LCDC hardware */
2427bb24
LP		 1404 lcdc_write(priv, _LDCNT1R, 0);
1405
0246c471
MD		 1406 return 0;
1407}
1408
1409static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1410{
1411 struct platform_device *pdev = to_platform_device(dev);
2427bb24 1412 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
0246c471 1413
2427bb24 1414 __sh_mobile_lcdc_start(priv);
0246c471
MD		 1415
1416 return 0;
1417}
1418
47145210 1419static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 1420 .suspend = sh_mobile_lcdc_suspend,
1421 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 1422 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1423 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 1424};
1425
f1f60b5f
LP		 1426/* -----------------------------------------------------------------------------
1427 * Framebuffer notifier
1428 */
1429
6de9edd5 1430/* locking: called with info->lock held */
6011bdea
GL		 1431static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1432 unsigned long action, void *data)
1433{
1434 struct fb_event *event = data;
1435 struct fb_info *info = event->info;
1436 struct sh_mobile_lcdc_chan *ch = info->par;
6011bdea
GL		 1437
1438 if (&ch->lcdc->notifier != nb)
baf16374 1439 return NOTIFY_DONE;
6011bdea
GL		 1440
1441 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1442 __func__, action, event->data);
1443
1444 switch(action) {
1445 case FB_EVENT_SUSPEND:
37c5dcc2 1446 sh_mobile_lcdc_display_off(ch);
afe417c0 1447 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL		 1448 break;
1449 case FB_EVENT_RESUME:
dd210503
GL		 1450 mutex_lock(&ch->open_lock);
1451 sh_mobile_fb_reconfig(info);
1452 mutex_unlock(&ch->open_lock);
6011bdea 1453
37c5dcc2 1454 sh_mobile_lcdc_display_on(ch);
ebe5e12d 1455 sh_mobile_lcdc_start(ch->lcdc);
6011bdea
GL		 1456 }
1457
baf16374 1458 return NOTIFY_OK;
6011bdea
GL		 1459}
1460
f1f60b5f
LP		 1461/* -----------------------------------------------------------------------------
1462 * Probe/remove and driver init/exit
1463 */
1464
217e9c43 1465static const struct fb_videomode default_720p __devinitconst = {
f1f60b5f
LP		 1466 .name = "HDMI 720p",
1467 .xres = 1280,
1468 .yres = 720,
1469
1470 .left_margin = 220,
1471 .right_margin = 110,
1472 .hsync_len = 40,
1473
1474 .upper_margin = 20,
1475 .lower_margin = 5,
1476 .vsync_len = 5,
1477
1478 .pixclock = 13468,
1479 .refresh = 60,
1480 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
1481};
1482
b4bee692
LP		 1483static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1484{
1485 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1486 struct fb_info *info;
1487 int i;
1488
1489 fb_unregister_client(&priv->notifier);
1490
1491 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
1492 if (priv->ch[i].info && priv->ch[i].info->dev)
1493 unregister_framebuffer(priv->ch[i].info);
1494
1495 sh_mobile_lcdc_stop(priv);
1496
1497 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
9a2985e7 1498 struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
b4bee692 1499
9a2985e7 1500 info = ch->info;
b4bee692
LP		 1501 if (!info || !info->device)
1502 continue;
1503
e34d0bbb
LP		 1504 if (ch->tx_dev) {
1505 ch->tx_dev->lcdc = NULL;
9a2985e7 1506 module_put(ch->cfg.tx_dev->dev.driver->owner);
e34d0bbb 1507 }
9a2985e7
LP		 1508
1509 if (ch->sglist)
1510 vfree(ch->sglist);
b4bee692
LP		 1511
1512 if (info->screen_base)
1513 dma_free_coherent(&pdev->dev, info->fix.smem_len,
9a2985e7 1514 info->screen_base, ch->dma_handle);
b4bee692
LP		 1515 fb_dealloc_cmap(&info->cmap);
1516 framebuffer_release(info);
1517 }
1518
1519 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1520 if (priv->ch[i].bl)
1521 sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
1522 }
1523
4774c12a
LP		 1524 if (priv->dot_clk) {
1525 pm_runtime_disable(&pdev->dev);
b4bee692 1526 clk_put(priv->dot_clk);
4774c12a 1527 }
b4bee692
LP		 1528
1529 if (priv->base)
1530 iounmap(priv->base);
1531
1532 if (priv->irq)
1533 free_irq(priv->irq, priv);
1534 kfree(priv);
1535 return 0;
1536}
cfb4f5d1 1537
217e9c43 1538static int __devinit sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
f1f60b5f
LP		 1539{
1540 int interface_type = ch->cfg.interface_type;
1541
1542 switch (interface_type) {
1543 case RGB8:
1544 case RGB9:
1545 case RGB12A:
1546 case RGB12B:
1547 case RGB16:
1548 case RGB18:
1549 case RGB24:
1550 case SYS8A:
1551 case SYS8B:
1552 case SYS8C:
1553 case SYS8D:
1554 case SYS9:
1555 case SYS12:
1556 case SYS16A:
1557 case SYS16B:
1558 case SYS16C:
1559 case SYS18:
1560 case SYS24:
1561 break;
1562 default:
1563 return -EINVAL;
1564 }
1565
1566 /* SUBLCD only supports SYS interface */
1567 if (lcdc_chan_is_sublcd(ch)) {
1568 if (!(interface_type & LDMT1R_IFM))
1569 return -EINVAL;
1570
1571 interface_type &= ~LDMT1R_IFM;
1572 }
1573
1574 ch->ldmt1r_value = interface_type;
1575 return 0;
1576}
1577
0a7f17aa
LP		 1578static int __devinit
1579sh_mobile_lcdc_channel_init(struct sh_mobile_lcdc_priv *priv,
1580 struct sh_mobile_lcdc_chan *ch)
cfb4f5d1 1581{
3ce05599
LP		 1582 struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
1583 const struct fb_videomode *max_mode;
1584 const struct fb_videomode *mode;
1585 struct fb_var_screeninfo *var;
cfb4f5d1 1586 struct fb_info *info;
3ce05599
LP		 1587 unsigned int max_size;
1588 int num_cfg;
1589 void *buf;
1590 int ret;
1591 int i;
1592
a67472ad
LP		 1593 mutex_init(&ch->open_lock);
1594
1595 /* Allocate the frame buffer device. */
0a7f17aa 1596 ch->info = framebuffer_alloc(0, priv->dev);
3ce05599 1597 if (!ch->info) {
0a7f17aa 1598 dev_err(priv->dev, "unable to allocate fb_info\n");
3ce05599
LP		 1599 return -ENOMEM;
1600 }
1601
1602 info = ch->info;
3ce05599
LP		 1603 info->fbops = &sh_mobile_lcdc_ops;
1604 info->par = ch;
a67472ad
LP		 1605 info->pseudo_palette = &ch->pseudo_palette;
1606 info->flags = FBINFO_FLAG_DEFAULT;
3ce05599 1607
9a2985e7
LP		 1608 if (cfg->tx_dev) {
1609 if (!cfg->tx_dev->dev.driver ||
1610 !try_module_get(cfg->tx_dev->dev.driver->owner)) {
1611 dev_warn(priv->dev,
1612 "unable to get transmitter device\n");
1613 return -EINVAL;
1614 }
1615 ch->tx_dev = platform_get_drvdata(cfg->tx_dev);
e34d0bbb 1616 ch->tx_dev->lcdc = ch;
9a2985e7
LP		 1617 }
1618
3ce05599
LP		 1619 /* Iterate through the modes to validate them and find the highest
1620 * resolution.
1621 */
1622 max_mode = NULL;
1623 max_size = 0;
1624
1625 for (i = 0, mode = cfg->lcd_cfg; i < cfg->num_cfg; i++, mode++) {
1626 unsigned int size = mode->yres * mode->xres;
1627
edd153a3
LP		 1628 /* NV12/NV21 buffers must have even number of lines */
1629 if ((cfg->fourcc == V4L2_PIX_FMT_NV12 ||
1630 cfg->fourcc == V4L2_PIX_FMT_NV21) && (mode->yres & 0x1)) {
0a7f17aa
LP		 1631 dev_err(priv->dev, "yres must be multiple of 2 for "
1632 "YCbCr420 mode.\n");
3ce05599
LP		 1633 return -EINVAL;
1634 }
1635
1636 if (size > max_size) {
1637 max_mode = mode;
1638 max_size = size;
1639 }
1640 }
1641
1642 if (!max_size)
1643 max_size = MAX_XRES * MAX_YRES;
1644 else
0a7f17aa 1645 dev_dbg(priv->dev, "Found largest videomode %ux%u\n",
3ce05599
LP		 1646 max_mode->xres, max_mode->yres);
1647
a67472ad 1648 /* Create the mode list. */
3ce05599
LP		 1649 if (cfg->lcd_cfg == NULL) {
1650 mode = &default_720p;
1651 num_cfg = 1;
1652 } else {
1653 mode = cfg->lcd_cfg;
1654 num_cfg = cfg->num_cfg;
1655 }
1656
1657 fb_videomode_to_modelist(mode, num_cfg, &info->modelist);
1658
a67472ad
LP		 1659 /* Initialize variable screen information using the first mode as
1660 * default. The default Y virtual resolution is twice the panel size to
1661 * allow for double-buffering.
1662 */
1663 var = &info->var;
3ce05599 1664 fb_videomode_to_var(var, mode);
afaad83b
LP		 1665 var->width = cfg->panel_cfg.width;
1666 var->height = cfg->panel_cfg.height;
3ce05599
LP		 1667 var->yres_virtual = var->yres * 2;
1668 var->activate = FB_ACTIVATE_NOW;
1669
edd153a3
LP		 1670 switch (cfg->fourcc) {
1671 case V4L2_PIX_FMT_RGB565:
1672 var->bits_per_pixel = 16;
1673 break;
1674 case V4L2_PIX_FMT_BGR24:
1675 var->bits_per_pixel = 24;
1676 break;
1677 case V4L2_PIX_FMT_BGR32:
1678 var->bits_per_pixel = 32;
1679 break;
1680 default:
1681 var->grayscale = cfg->fourcc;
1682 break;
1683 }
1684
1685 /* Make sure the memory size check won't fail. smem_len is initialized
1686 * later based on var.
1687 */
1688 info->fix.smem_len = UINT_MAX;
a67472ad 1689 ret = sh_mobile_check_var(var, info);
3ce05599
LP		 1690 if (ret)
1691 return ret;
1692
edd153a3
LP		 1693 max_size = max_size * var->bits_per_pixel / 8 * 2;
1694
a67472ad 1695 /* Allocate frame buffer memory and color map. */
0a7f17aa
LP		 1696 buf = dma_alloc_coherent(priv->dev, max_size, &ch->dma_handle,
1697 GFP_KERNEL);
3ce05599 1698 if (!buf) {
0a7f17aa 1699 dev_err(priv->dev, "unable to allocate buffer\n");
3ce05599
LP		 1700 return -ENOMEM;
1701 }
1702
3ce05599
LP		 1703 ret = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1704 if (ret < 0) {
0a7f17aa
LP		 1705 dev_err(priv->dev, "unable to allocate cmap\n");
1706 dma_free_coherent(priv->dev, max_size, buf, ch->dma_handle);
3ce05599
LP		 1707 return ret;
1708 }
1709
edd153a3
LP		 1710 /* Initialize fixed screen information. Restrict pan to 2 lines steps
1711 * for NV12 and NV21.
1712 */
1713 info->fix = sh_mobile_lcdc_fix;
3ce05599 1714 info->fix.smem_start = ch->dma_handle;
edd153a3
LP		 1715 info->fix.smem_len = max_size;
1716 if (cfg->fourcc == V4L2_PIX_FMT_NV12 ||
1717 cfg->fourcc == V4L2_PIX_FMT_NV21)
1718 info->fix.ypanstep = 2;
1719
1720 if (sh_mobile_format_is_yuv(var)) {
3ce05599 1721 info->fix.line_length = var->xres;
edd153a3
LP		 1722 info->fix.visual = FB_VISUAL_FOURCC;
1723 } else {
1724 info->fix.line_length = var->xres * var->bits_per_pixel / 8;
1725 info->fix.visual = FB_VISUAL_TRUECOLOR;
1726 }
3ce05599
LP		 1727
1728 info->screen_base = buf;
0a7f17aa 1729 info->device = priv->dev;
3ce05599
LP		 1730 ch->display_var = *var;
1731
1732 return 0;
1733}
1734
1735static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1736{
01ac25b5 1737 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
3ce05599 1738 struct sh_mobile_lcdc_priv *priv;
cfb4f5d1 1739 struct resource *res;
3ce05599 1740 int num_channels;
cfb4f5d1 1741 int error;
3ce05599 1742 int i;
cfb4f5d1 1743
01ac25b5 1744 if (!pdata) {
cfb4f5d1 1745 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1746 return -EINVAL;
cfb4f5d1
MD		 1747 }
1748
1749 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1750 i = platform_get_irq(pdev, 0);
1751 if (!res || i < 0) {
1752 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1753 return -ENOENT;
cfb4f5d1
MD		 1754 }
1755
1756 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1757 if (!priv) {
1758 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1759 return -ENOMEM;
cfb4f5d1
MD		 1760 }
1761
4774c12a
LP		 1762 priv->dev = &pdev->dev;
1763 priv->meram_dev = pdata->meram_dev;
8bed9055
GL		 1764 platform_set_drvdata(pdev, priv);
1765
f8798ccb 1766 error = request_irq(i, sh_mobile_lcdc_irq, 0,
7ad33e74 1767 dev_name(&pdev->dev), priv);
8564557a
MD		 1768 if (error) {
1769 dev_err(&pdev->dev, "unable to request irq\n");
1770 goto err1;
1771 }
1772
1773 priv->irq = i;
5ef6b505 1774 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1 1775
3ce05599
LP		 1776 for (i = 0, num_channels = 0; i < ARRAY_SIZE(pdata->ch); i++) {
1777 struct sh_mobile_lcdc_chan *ch = priv->ch + num_channels;
cfb4f5d1 1778
01ac25b5
GL		 1779 ch->lcdc = priv;
1780 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
cfb4f5d1 1781
01ac25b5 1782 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 1783 if (error) {
1784 dev_err(&pdev->dev, "unsupported interface type\n");
1785 goto err1;
1786 }
01ac25b5
GL		 1787 init_waitqueue_head(&ch->frame_end_wait);
1788 init_completion(&ch->vsync_completion);
1789 ch->pan_offset = 0;
cfb4f5d1 1790
3b0fd9d7
AC		 1791 /* probe the backlight is there is one defined */
1792 if (ch->cfg.bl_info.max_brightness)
1793 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
1794
cfb4f5d1
MD		 1795 switch (pdata->ch[i].chan) {
1796 case LCDC_CHAN_MAINLCD:
ce1c0b08 1797 ch->enabled = LDCNT2R_ME;
01ac25b5 1798 ch->reg_offs = lcdc_offs_mainlcd;
3ce05599 1799 num_channels++;
cfb4f5d1
MD		 1800 break;
1801 case LCDC_CHAN_SUBLCD:
ce1c0b08 1802 ch->enabled = LDCNT2R_SE;
01ac25b5 1803 ch->reg_offs = lcdc_offs_sublcd;
3ce05599 1804 num_channels++;
cfb4f5d1
MD		 1805 break;
1806 }
1807 }
1808
3ce05599 1809 if (!num_channels) {
cfb4f5d1
MD		 1810 dev_err(&pdev->dev, "no channels defined\n");
1811 error = -EINVAL;
1812 goto err1;
1813 }
1814
edd153a3 1815 /* for dual channel LCDC (MAIN + SUB) force shared format setting */
3ce05599 1816 if (num_channels == 2)
edd153a3 1817 priv->forced_fourcc = pdata->ch[0].fourcc;
417d4827 1818
dba6f385
GL		 1819 priv->base = ioremap_nocache(res->start, resource_size(res));
1820 if (!priv->base)
1821 goto err1;
1822
0a7f17aa 1823 error = sh_mobile_lcdc_setup_clocks(priv, pdata->clock_source);
cfb4f5d1
MD		 1824 if (error) {
1825 dev_err(&pdev->dev, "unable to setup clocks\n");
1826 goto err1;
1827 }
1828
4774c12a
LP		 1829 /* Enable runtime PM. */
1830 pm_runtime_enable(&pdev->dev);
7caa4342 1831
3ce05599 1832 for (i = 0; i < num_channels; i++) {
01ac25b5 1833 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76 1834
0a7f17aa 1835 error = sh_mobile_lcdc_channel_init(priv, ch);
cfb4f5d1 1836 if (error)
3ce05599 1837 goto err1;
cfb4f5d1
MD		 1838 }
1839
cfb4f5d1
MD		 1840 error = sh_mobile_lcdc_start(priv);
1841 if (error) {
1842 dev_err(&pdev->dev, "unable to start hardware\n");
1843 goto err1;
1844 }
1845
3ce05599 1846 for (i = 0; i < num_channels; i++) {
1c6a307a 1847 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
3ce05599 1848 struct fb_info *info = ch->info;
1c6a307a
PM		 1849
1850 if (info->fbdefio) {
8bed9055 1851 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1852 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1853 if (!ch->sglist) {
1c6a307a
PM		 1854 dev_err(&pdev->dev, "cannot allocate sglist\n");
1855 goto err1;
1856 }
1857 }
1858
3b0fd9d7
AC		 1859 info->bl_dev = ch->bl;
1860
1c6a307a 1861 error = register_framebuffer(info);
cfb4f5d1
MD		 1862 if (error < 0)
1863 goto err1;
cfb4f5d1 1864
0a7f17aa 1865 dev_info(&pdev->dev, "registered %s/%s as %dx%d %dbpp.\n",
edd153a3
LP		 1866 pdev->name, (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
1867 "mainlcd" : "sublcd", info->var.xres, info->var.yres,
1868 info->var.bits_per_pixel);
8564557a
MD		 1869
1870 /* deferred io mode: disable clock to save power */
6011bdea 1871 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1872 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1873 }
1874
6011bdea
GL		 1875 /* Failure ignored */
1876 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1877 fb_register_client(&priv->notifier);
1878
cfb4f5d1 1879 return 0;
8bed9055 1880err1:
cfb4f5d1 1881 sh_mobile_lcdc_remove(pdev);
8bed9055 1882
cfb4f5d1
MD		 1883 return error;
1884}
1885
cfb4f5d1
MD		 1886static struct platform_driver sh_mobile_lcdc_driver = {
1887 .driver = {
1888 .name = "sh_mobile_lcdc_fb",
1889 .owner = THIS_MODULE,
2feb075a 1890 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1891 },
1892 .probe = sh_mobile_lcdc_probe,
1893 .remove = sh_mobile_lcdc_remove,
1894};
1895
4277f2c4 1896module_platform_driver(sh_mobile_lcdc_driver);
cfb4f5d1
MD		 1897
1898MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1899MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1900MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)