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6011bdea GL |
1 | /* |
2 | * SH-Mobile High-Definition Multimedia Interface (HDMI) driver | |
3 | * for SLISHDMI13T and SLIPHDMIT IP cores | |
4 | * | |
5 | * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/console.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/pm_runtime.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/types.h> | |
24 | #include <linux/workqueue.h> | |
25 | ||
26 | #include <video/sh_mobile_hdmi.h> | |
27 | #include <video/sh_mobile_lcdc.h> | |
28 | ||
6de9edd5 GL |
29 | #include "sh_mobile_lcdcfb.h" |
30 | ||
6011bdea GL |
31 | #define HDMI_SYSTEM_CTRL 0x00 /* System control */ |
32 | #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control, | |
33 | bits 19..16 of 20-bit N for Audio Clock Regeneration packet */ | |
34 | #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */ | |
35 | #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */ | |
36 | #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency, | |
37 | bits 19..16 of Internal CTS */ | |
38 | #define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */ | |
39 | #define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */ | |
40 | #define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */ | |
41 | #define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */ | |
42 | #define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */ | |
43 | #define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */ | |
44 | #define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */ | |
45 | #define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */ | |
46 | #define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */ | |
47 | #define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */ | |
48 | #define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */ | |
49 | #define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */ | |
50 | #define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */ | |
51 | #define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */ | |
52 | #define HDMI_CATEGORY_CODE 0x13 /* Category code */ | |
53 | #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */ | |
54 | #define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */ | |
55 | #define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */ | |
56 | #define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */ | |
57 | ||
58 | /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */ | |
59 | #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18 | |
60 | ||
61 | #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */ | |
62 | #define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */ | |
63 | #define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */ | |
64 | #define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */ | |
65 | #define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */ | |
66 | #define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */ | |
67 | #define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */ | |
68 | #define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */ | |
69 | #define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */ | |
70 | #define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */ | |
71 | #define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */ | |
72 | #define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */ | |
73 | #define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */ | |
74 | #define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */ | |
75 | #define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */ | |
76 | #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */ | |
77 | #define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */ | |
78 | #define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */ | |
79 | #define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */ | |
80 | #define HDMI_OUTPUT_OPTION 0x46 /* Output option */ | |
81 | #define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */ | |
82 | #define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */ | |
83 | #define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */ | |
84 | #define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */ | |
85 | #define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */ | |
86 | #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */ | |
87 | #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */ | |
88 | #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */ | |
89 | #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */ | |
90 | #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */ | |
91 | #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */ | |
92 | #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */ | |
93 | #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */ | |
94 | #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */ | |
95 | #define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */ | |
96 | #define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */ | |
97 | #define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */ | |
98 | #define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */ | |
99 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */ | |
100 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */ | |
101 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */ | |
102 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */ | |
103 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */ | |
104 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */ | |
105 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */ | |
106 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */ | |
107 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */ | |
108 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */ | |
109 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */ | |
110 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */ | |
111 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */ | |
112 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */ | |
113 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */ | |
114 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */ | |
115 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */ | |
116 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */ | |
117 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */ | |
118 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */ | |
119 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */ | |
120 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */ | |
121 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */ | |
122 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */ | |
123 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */ | |
124 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */ | |
125 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */ | |
126 | #define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */ | |
127 | #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */ | |
128 | #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */ | |
129 | #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */ | |
130 | #define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */ | |
131 | #define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */ | |
132 | #define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */ | |
133 | #define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */ | |
134 | #define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */ | |
135 | #define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */ | |
136 | #define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */ | |
137 | #define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */ | |
138 | #define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */ | |
139 | #define HDMI_FRAME_COUNTER 0x9C /* Frame counter */ | |
140 | #define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */ | |
141 | #define HDMI_HDCP_CONTROL 0xAF /* HDCP control */ | |
142 | #define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */ | |
143 | #define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */ | |
144 | #define HDMI_HDCP_STATUS 0xB8 /* HDCP status */ | |
145 | #define HDMI_SHA0 0xB9 /* sha0 */ | |
146 | #define HDMI_SHA1 0xBA /* sha1 */ | |
147 | #define HDMI_SHA2 0xBB /* sha2 */ | |
148 | #define HDMI_SHA3 0xBC /* sha3 */ | |
149 | #define HDMI_SHA4 0xBD /* sha4 */ | |
150 | #define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */ | |
151 | #define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */ | |
152 | #define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */ | |
153 | #define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */ | |
154 | #define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */ | |
155 | #define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */ | |
156 | #define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */ | |
157 | #define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */ | |
158 | #define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */ | |
159 | #define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */ | |
160 | #define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */ | |
161 | #define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */ | |
162 | #define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */ | |
163 | #define HDMI_RI_READ_COUNT 0xCB /* Ri read count */ | |
164 | #define HDMI_AN_SEED 0xCC /* An seed */ | |
165 | #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */ | |
166 | #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */ | |
167 | #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */ | |
168 | #define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */ | |
169 | #define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */ | |
170 | #define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */ | |
171 | #define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */ | |
172 | #define HDMI_RI_7_0 0xD5 /* Ri[7:0] */ | |
173 | #define HDMI_RI_15_8 0xD6 /* Ri[15:8] */ | |
174 | #define HDMI_PJ 0xD7 /* Pj */ | |
175 | #define HDMI_SHA_RD 0xD8 /* sha_rd */ | |
176 | #define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */ | |
177 | #define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */ | |
178 | #define HDMI_PJ_SAVED 0xDB /* Pj saved */ | |
179 | #define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */ | |
180 | #define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */ | |
181 | #define HDMI_BCAPS_WRITE 0xE0 /* bcaps */ | |
182 | #define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */ | |
183 | #define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */ | |
184 | #define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */ | |
185 | #define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */ | |
186 | #define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */ | |
187 | #define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */ | |
188 | #define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */ | |
189 | #define HDMI_AN_7_0 0xE8 /* An[7:0] */ | |
190 | #define HDMI_AN_15_8 0xE9 /* An [15:8] */ | |
191 | #define HDMI_AN_23_16 0xEA /* An [23:16] */ | |
192 | #define HDMI_AN_31_24 0xEB /* An [31:24] */ | |
193 | #define HDMI_AN_39_32 0xEC /* An [39:32] */ | |
194 | #define HDMI_AN_47_40 0xED /* An [47:40] */ | |
195 | #define HDMI_AN_55_48 0xEE /* An [55:48] */ | |
196 | #define HDMI_AN_63_56 0xEF /* An [63:56] */ | |
197 | #define HDMI_PRODUCT_ID 0xF0 /* Product ID */ | |
198 | #define HDMI_REVISION_ID 0xF1 /* Revision ID */ | |
199 | #define HDMI_TEST_MODE 0xFE /* Test mode */ | |
200 | ||
201 | enum hotplug_state { | |
202 | HDMI_HOTPLUG_DISCONNECTED, | |
203 | HDMI_HOTPLUG_CONNECTED, | |
204 | HDMI_HOTPLUG_EDID_DONE, | |
205 | }; | |
206 | ||
207 | struct sh_hdmi { | |
208 | void __iomem *base; | |
6aa966e6 | 209 | enum hotplug_state hp_state; /* hot-plug status */ |
89712699 | 210 | bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */ |
6011bdea GL |
211 | struct clk *hdmi_clk; |
212 | struct device *dev; | |
213 | struct fb_info *info; | |
6de9edd5 | 214 | struct mutex mutex; /* Protect the info pointer */ |
6011bdea GL |
215 | struct delayed_work edid_work; |
216 | struct fb_var_screeninfo var; | |
217 | }; | |
218 | ||
219 | static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg) | |
220 | { | |
221 | iowrite8(data, hdmi->base + reg); | |
222 | } | |
223 | ||
224 | static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg) | |
225 | { | |
226 | return ioread8(hdmi->base + reg); | |
227 | } | |
228 | ||
229 | /* External video parameter settings */ | |
6aa966e6 | 230 | static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi) |
6011bdea GL |
231 | { |
232 | struct fb_var_screeninfo *var = &hdmi->var; | |
233 | u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset; | |
234 | u8 sync = 0; | |
235 | ||
236 | htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len; | |
237 | ||
238 | hdelay = var->hsync_len + var->left_margin; | |
239 | hblank = var->right_margin + hdelay; | |
240 | ||
241 | /* | |
242 | * Vertical timing looks a bit different in Figure 18, | |
243 | * but let's try the same first by setting offset = 0 | |
244 | */ | |
245 | vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; | |
246 | ||
247 | vdelay = var->vsync_len + var->upper_margin; | |
248 | vblank = var->lower_margin + vdelay; | |
249 | voffset = min(var->upper_margin / 2, 6U); | |
250 | ||
251 | /* | |
252 | * [3]: VSYNC polarity: Positive | |
253 | * [2]: HSYNC polarity: Positive | |
254 | * [1]: Interlace/Progressive: Progressive | |
255 | * [0]: External video settings enable: used. | |
256 | */ | |
257 | if (var->sync & FB_SYNC_HOR_HIGH_ACT) | |
258 | sync |= 4; | |
259 | if (var->sync & FB_SYNC_VERT_HIGH_ACT) | |
260 | sync |= 8; | |
261 | ||
6aa966e6 GL |
262 | dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n", |
263 | htotal, hblank, hdelay, var->hsync_len, | |
264 | vtotal, vblank, vdelay, var->vsync_len, sync); | |
6011bdea GL |
265 | |
266 | hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS); | |
267 | ||
268 | hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0); | |
269 | hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8); | |
270 | ||
271 | hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0); | |
272 | hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8); | |
273 | ||
274 | hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0); | |
275 | hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8); | |
276 | ||
277 | hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0); | |
278 | hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8); | |
279 | ||
280 | hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0); | |
281 | hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8); | |
282 | ||
283 | hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK); | |
284 | ||
285 | hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY); | |
286 | ||
287 | hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION); | |
288 | ||
89712699 GL |
289 | /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */ |
290 | if (!hdmi->preprogrammed_mode) | |
291 | hdmi_write(hdmi, sync | 1 | (voffset << 4), | |
292 | HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS); | |
6011bdea GL |
293 | } |
294 | ||
295 | /** | |
296 | * sh_hdmi_video_config() | |
297 | */ | |
298 | static void sh_hdmi_video_config(struct sh_hdmi *hdmi) | |
299 | { | |
300 | /* | |
301 | * [7:4]: Audio sampling frequency: 48kHz | |
302 | * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green) | |
303 | * [0]: Internal/External DE select: internal | |
304 | */ | |
305 | hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1); | |
306 | ||
307 | /* | |
308 | * [7:6]: Video output format: RGB 4:4:4 | |
309 | * [5:4]: Input video data width: 8 bit | |
310 | * [3:1]: EAV/SAV location: channel 1 | |
311 | * [0]: Video input color space: RGB | |
312 | */ | |
313 | hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1); | |
314 | ||
315 | /* | |
316 | * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is | |
317 | * left at 0 by default, this configures 24bpp and sets the Color Depth | |
318 | * (CD) field in the General Control Packet | |
319 | */ | |
320 | hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES); | |
321 | } | |
322 | ||
323 | /** | |
324 | * sh_hdmi_audio_config() | |
325 | */ | |
326 | static void sh_hdmi_audio_config(struct sh_hdmi *hdmi) | |
327 | { | |
328 | /* | |
329 | * [7:4] L/R data swap control | |
330 | * [3:0] appropriate N[19:16] | |
331 | */ | |
332 | hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT); | |
333 | /* appropriate N[15:8] */ | |
334 | hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8); | |
335 | /* appropriate N[7:0] */ | |
336 | hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0); | |
337 | ||
338 | /* [7:4] 48 kHz SPDIF not used */ | |
339 | hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS); | |
340 | ||
341 | /* | |
342 | * [6:5] set required down sampling rate if required | |
343 | * [4:3] set required audio source | |
344 | */ | |
345 | hdmi_write(hdmi, 0x00, HDMI_AUDIO_SETTING_1); | |
346 | ||
347 | /* [3:0] set sending channel number for channel status */ | |
348 | hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2); | |
349 | ||
350 | /* | |
351 | * [5:2] set valid I2S source input pin | |
352 | * [1:0] set input I2S source mode | |
353 | */ | |
354 | hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET); | |
355 | ||
356 | /* [7:4] set valid DSD source input pin */ | |
357 | hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET); | |
358 | ||
359 | /* [7:0] set appropriate I2S input pin swap settings if required */ | |
360 | hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP); | |
361 | ||
362 | /* | |
363 | * [7] set validity bit for channel status | |
364 | * [3:0] set original sample frequency for channel status | |
365 | */ | |
366 | hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1); | |
367 | ||
368 | /* | |
369 | * [7] set value for channel status | |
370 | * [6] set value for channel status | |
371 | * [5] set copyright bit for channel status | |
372 | * [4:2] set additional information for channel status | |
373 | * [1:0] set clock accuracy for channel status | |
374 | */ | |
375 | hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2); | |
376 | ||
377 | /* [7:0] set category code for channel status */ | |
378 | hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE); | |
379 | ||
380 | /* | |
381 | * [7:4] set source number for channel status | |
382 | * [3:0] set word length for channel status | |
383 | */ | |
384 | hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN); | |
385 | ||
386 | /* [7:4] set sample frequency for channel status */ | |
387 | hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1); | |
388 | } | |
389 | ||
390 | /** | |
6e45746c | 391 | * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode |
6011bdea GL |
392 | */ |
393 | static void sh_hdmi_phy_config(struct sh_hdmi *hdmi) | |
394 | { | |
6e45746c GL |
395 | if (hdmi->var.yres > 480) { |
396 | /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */ | |
397 | /* | |
398 | * [1:0] Speed_A | |
399 | * [3:2] Speed_B | |
400 | * [4] PLLA_Bypass | |
401 | * [6] DRV_TEST_EN | |
402 | * [7] DRV_TEST_IN | |
403 | */ | |
9289c475 | 404 | hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1); |
6e45746c GL |
405 | /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */ |
406 | hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2); | |
407 | /* | |
408 | * [2:0] BGR_I_OFFSET | |
409 | * [6:4] BGR_V_OFFSET | |
410 | */ | |
411 | hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3); | |
412 | /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */ | |
413 | hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5); | |
414 | /* | |
415 | * PLLA_CONFIG[15:8]: regulator voltage[0], CP current, | |
416 | * LPF capacitance, LPF resistance[1] | |
417 | */ | |
418 | hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6); | |
419 | /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */ | |
420 | hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7); | |
421 | /* | |
422 | * PLLB_CONFIG[15:8]: regulator voltage[0], CP current, | |
423 | * LPF capacitance, LPF resistance[1] | |
424 | */ | |
9289c475 | 425 | hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8); |
6e45746c GL |
426 | /* DRV_CONFIG, PE_CONFIG */ |
427 | hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9); | |
428 | /* | |
429 | * [2:0] AMON_SEL (4 == LPF voltage) | |
430 | * [4] PLLA_CONFIG[16] | |
431 | * [5] PLLB_CONFIG[16] | |
432 | */ | |
433 | hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10); | |
434 | } else { | |
435 | /* for 480p8bit 27MHz */ | |
436 | hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1); | |
437 | hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2); | |
438 | hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3); | |
439 | hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5); | |
440 | hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6); | |
441 | hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7); | |
442 | hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8); | |
443 | hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9); | |
444 | hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10); | |
445 | } | |
6011bdea GL |
446 | } |
447 | ||
448 | /** | |
449 | * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET | |
450 | */ | |
451 | static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi) | |
452 | { | |
6e45746c GL |
453 | u8 vic; |
454 | ||
6011bdea GL |
455 | /* AVI InfoFrame */ |
456 | hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX); | |
457 | ||
458 | /* Packet Type = 0x82 */ | |
459 | hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0); | |
460 | ||
461 | /* Version = 0x02 */ | |
462 | hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1); | |
463 | ||
464 | /* Length = 13 (0x0D) */ | |
465 | hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2); | |
466 | ||
467 | /* N. A. Checksum */ | |
468 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0); | |
469 | ||
470 | /* | |
471 | * Y = RGB | |
472 | * A0 = No Data | |
473 | * B = Bar Data not valid | |
474 | * S = No Data | |
475 | */ | |
476 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1); | |
477 | ||
478 | /* | |
6aa966e6 GL |
479 | * [7:6] C = Colorimetry: no data |
480 | * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio | |
481 | * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio | |
6011bdea GL |
482 | */ |
483 | hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2); | |
484 | ||
485 | /* | |
486 | * ITC = No Data | |
487 | * EC = xvYCC601 | |
488 | * Q = Default (depends on video format) | |
489 | * SC = No Known non_uniform Scaling | |
490 | */ | |
491 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3); | |
492 | ||
493 | /* | |
494 | * VIC = 1280 x 720p: ignored if external config is used | |
6e45746c | 495 | * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode |
6011bdea | 496 | */ |
6e45746c GL |
497 | if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920) |
498 | vic = 16; | |
499 | else if (hdmi->var.yres == 480 && hdmi->var.xres == 720) | |
500 | vic = 2; | |
501 | else | |
502 | vic = 4; | |
503 | hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4); | |
6011bdea GL |
504 | |
505 | /* PR = No Repetition */ | |
506 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5); | |
507 | ||
508 | /* Line Number of End of Top Bar (lower 8 bits) */ | |
509 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6); | |
510 | ||
511 | /* Line Number of End of Top Bar (upper 8 bits) */ | |
512 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7); | |
513 | ||
514 | /* Line Number of Start of Bottom Bar (lower 8 bits) */ | |
515 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8); | |
516 | ||
517 | /* Line Number of Start of Bottom Bar (upper 8 bits) */ | |
518 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9); | |
519 | ||
520 | /* Pixel Number of End of Left Bar (lower 8 bits) */ | |
521 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10); | |
522 | ||
523 | /* Pixel Number of End of Left Bar (upper 8 bits) */ | |
524 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11); | |
525 | ||
526 | /* Pixel Number of Start of Right Bar (lower 8 bits) */ | |
527 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12); | |
528 | ||
529 | /* Pixel Number of Start of Right Bar (upper 8 bits) */ | |
530 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13); | |
531 | } | |
532 | ||
533 | /** | |
534 | * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET | |
535 | */ | |
536 | static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi) | |
537 | { | |
538 | /* Audio InfoFrame */ | |
539 | hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX); | |
540 | ||
541 | /* Packet Type = 0x84 */ | |
542 | hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0); | |
543 | ||
544 | /* Version Number = 0x01 */ | |
545 | hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1); | |
546 | ||
547 | /* 0 Length = 10 (0x0A) */ | |
548 | hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2); | |
549 | ||
550 | /* n. a. Checksum */ | |
551 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0); | |
552 | ||
553 | /* Audio Channel Count = Refer to Stream Header */ | |
554 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1); | |
555 | ||
556 | /* Refer to Stream Header */ | |
557 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2); | |
558 | ||
559 | /* Format depends on coding type (i.e. CT0...CT3) */ | |
560 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3); | |
561 | ||
562 | /* Speaker Channel Allocation = Front Right + Front Left */ | |
563 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4); | |
564 | ||
565 | /* Level Shift Value = 0 dB, Down - mix is permitted or no information */ | |
566 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5); | |
567 | ||
568 | /* Reserved (0) */ | |
569 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6); | |
570 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7); | |
571 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8); | |
572 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9); | |
573 | hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10); | |
574 | } | |
575 | ||
6011bdea GL |
576 | /** |
577 | * sh_hdmi_configure() - Initialise HDMI for output | |
578 | */ | |
579 | static void sh_hdmi_configure(struct sh_hdmi *hdmi) | |
580 | { | |
581 | /* Configure video format */ | |
582 | sh_hdmi_video_config(hdmi); | |
583 | ||
584 | /* Configure audio format */ | |
585 | sh_hdmi_audio_config(hdmi); | |
586 | ||
587 | /* Configure PHY */ | |
588 | sh_hdmi_phy_config(hdmi); | |
589 | ||
590 | /* Auxiliary Video Information (AVI) InfoFrame */ | |
591 | sh_hdmi_avi_infoframe_setup(hdmi); | |
592 | ||
593 | /* Audio InfoFrame */ | |
594 | sh_hdmi_audio_infoframe_setup(hdmi); | |
595 | ||
6011bdea GL |
596 | /* |
597 | * Control packet auto send with VSYNC control: auto send | |
598 | * General control, Gamut metadata, ISRC, and ACP packets | |
599 | */ | |
600 | hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND); | |
601 | ||
602 | /* FIXME */ | |
603 | msleep(10); | |
604 | ||
605 | /* PS mode b->d, reset PLLA and PLLB */ | |
606 | hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL); | |
607 | ||
608 | udelay(10); | |
609 | ||
610 | hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL); | |
611 | } | |
612 | ||
613 | static void sh_hdmi_read_edid(struct sh_hdmi *hdmi) | |
614 | { | |
6ee48452 GL |
615 | struct fb_var_screeninfo tmpvar; |
616 | /* TODO: When we are ready to use EDID, use this to fill &hdmi->var */ | |
617 | struct fb_var_screeninfo *var = &tmpvar; | |
6011bdea GL |
618 | int i; |
619 | u8 edid[128]; | |
620 | ||
621 | /* Read EDID */ | |
6aa966e6 | 622 | dev_dbg(hdmi->dev, "Read back EDID code:"); |
6011bdea GL |
623 | for (i = 0; i < 128; i++) { |
624 | edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW); | |
625 | #ifdef DEBUG | |
626 | if ((i % 16) == 0) { | |
627 | printk(KERN_CONT "\n"); | |
628 | printk(KERN_DEBUG "%02X | %02X", i, edid[i]); | |
629 | } else { | |
630 | printk(KERN_CONT " %02X", edid[i]); | |
631 | } | |
632 | #endif | |
633 | } | |
634 | #ifdef DEBUG | |
635 | printk(KERN_CONT "\n"); | |
636 | #endif | |
637 | fb_parse_edid(edid, var); | |
6aa966e6 GL |
638 | dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n", |
639 | var->left_margin, var->xres, var->right_margin, var->hsync_len, | |
640 | var->upper_margin, var->yres, var->lower_margin, var->vsync_len, | |
641 | PICOS2KHZ(var->pixclock)); | |
6011bdea | 642 | |
89712699 GL |
643 | if ((hdmi->var.xres == 720 && hdmi->var.yres == 480) || |
644 | (hdmi->var.xres == 1280 && hdmi->var.yres == 720) || | |
645 | (hdmi->var.xres == 1920 && hdmi->var.yres == 1080)) | |
646 | hdmi->preprogrammed_mode = true; | |
647 | else | |
648 | hdmi->preprogrammed_mode = false; | |
649 | ||
6aa966e6 | 650 | sh_hdmi_external_video_param(hdmi); |
6011bdea GL |
651 | } |
652 | ||
653 | static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id) | |
654 | { | |
655 | struct sh_hdmi *hdmi = dev_id; | |
656 | u8 status1, status2, mask1, mask2; | |
657 | ||
658 | /* mode_b and PLLA and PLLB reset */ | |
659 | hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL); | |
660 | ||
661 | /* How long shall reset be held? */ | |
662 | udelay(10); | |
663 | ||
664 | /* mode_b and PLLA and PLLB reset release */ | |
665 | hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL); | |
666 | ||
667 | status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1); | |
668 | status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2); | |
669 | ||
670 | mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1); | |
671 | mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2); | |
672 | ||
673 | /* Correct would be to ack only set bits, but the datasheet requires 0xff */ | |
674 | hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1); | |
675 | hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2); | |
676 | ||
677 | if (printk_ratelimit()) | |
6aa966e6 GL |
678 | dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n", |
679 | irq, status1, mask1, status2, mask2); | |
6011bdea GL |
680 | |
681 | if (!((status1 & mask1) | (status2 & mask2))) { | |
682 | return IRQ_NONE; | |
683 | } else if (status1 & 0xc0) { | |
684 | u8 msens; | |
685 | ||
686 | /* Datasheet specifies 10ms... */ | |
687 | udelay(500); | |
688 | ||
689 | msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS); | |
6aa966e6 | 690 | dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens); |
6011bdea GL |
691 | /* Check, if hot plug & MSENS pin status are both high */ |
692 | if ((msens & 0xC0) == 0xC0) { | |
693 | /* Display plug in */ | |
694 | hdmi->hp_state = HDMI_HOTPLUG_CONNECTED; | |
695 | ||
696 | /* Set EDID word address */ | |
697 | hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS); | |
698 | /* Set EDID segment pointer */ | |
699 | hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER); | |
700 | /* Enable EDID interrupt */ | |
701 | hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1); | |
702 | } else if (!(status1 & 0x80)) { | |
703 | /* Display unplug, beware multiple interrupts */ | |
704 | if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) | |
705 | schedule_delayed_work(&hdmi->edid_work, 0); | |
706 | ||
707 | hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED; | |
708 | /* display_off will switch back to mode_a */ | |
709 | } | |
710 | } else if (status1 & 2) { | |
711 | /* EDID error interrupt: retry */ | |
712 | /* Set EDID word address */ | |
713 | hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS); | |
714 | /* Set EDID segment pointer */ | |
715 | hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER); | |
716 | } else if (status1 & 4) { | |
717 | /* Disable EDID interrupt */ | |
718 | hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1); | |
719 | hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE; | |
720 | schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10)); | |
721 | } | |
722 | ||
723 | return IRQ_HANDLED; | |
724 | } | |
725 | ||
6de9edd5 | 726 | /* locking: called with info->lock held, or before register_framebuffer() */ |
6aa966e6 | 727 | static void sh_hdmi_display_on(void *arg, struct fb_info *info) |
6011bdea | 728 | { |
6de9edd5 GL |
729 | /* |
730 | * info is guaranteed to be valid, when we are called, because our | |
731 | * FB_EVENT_FB_UNBIND notify is also called with info->lock held | |
732 | */ | |
6011bdea GL |
733 | struct sh_hdmi *hdmi = arg; |
734 | struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data; | |
1c120deb | 735 | struct sh_mobile_lcdc_chan *ch = info->par; |
6011bdea | 736 | |
6aa966e6 GL |
737 | dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__, |
738 | pdata->lcd_dev, info->state); | |
6de9edd5 GL |
739 | |
740 | /* No need to lock */ | |
6011bdea | 741 | hdmi->info = info; |
6de9edd5 | 742 | |
6aa966e6 GL |
743 | /* |
744 | * hp_state can be set to | |
745 | * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug | |
746 | * HDMI_HOTPLUG_CONNECTED: on monitor plug-in | |
747 | * HDMI_HOTPLUG_EDID_DONE: on EDID read completion | |
748 | */ | |
6011bdea GL |
749 | switch (hdmi->hp_state) { |
750 | case HDMI_HOTPLUG_EDID_DONE: | |
751 | /* PS mode d->e. All functions are active */ | |
752 | hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL); | |
6aa966e6 | 753 | dev_dbg(hdmi->dev, "HDMI running\n"); |
6011bdea GL |
754 | break; |
755 | case HDMI_HOTPLUG_DISCONNECTED: | |
756 | info->state = FBINFO_STATE_SUSPENDED; | |
757 | default: | |
1c120deb | 758 | hdmi->var = ch->display_var; |
6011bdea GL |
759 | } |
760 | } | |
761 | ||
6de9edd5 | 762 | /* locking: called with info->lock held */ |
6aa966e6 | 763 | static void sh_hdmi_display_off(void *arg) |
6011bdea GL |
764 | { |
765 | struct sh_hdmi *hdmi = arg; | |
766 | struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data; | |
767 | ||
6aa966e6 | 768 | dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev); |
6011bdea GL |
769 | /* PS mode e->a */ |
770 | hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL); | |
771 | } | |
772 | ||
773 | /* Hotplug interrupt occurred, read EDID */ | |
6aa966e6 | 774 | static void sh_hdmi_edid_work_fn(struct work_struct *work) |
6011bdea GL |
775 | { |
776 | struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work); | |
777 | struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data; | |
1c120deb | 778 | struct sh_mobile_lcdc_chan *ch; |
6011bdea | 779 | |
6aa966e6 GL |
780 | dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__, |
781 | pdata->lcd_dev, hdmi->hp_state); | |
6011bdea GL |
782 | |
783 | if (!pdata->lcd_dev) | |
784 | return; | |
785 | ||
6de9edd5 GL |
786 | mutex_lock(&hdmi->mutex); |
787 | ||
6011bdea GL |
788 | if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) { |
789 | pm_runtime_get_sync(hdmi->dev); | |
790 | /* A device has been plugged in */ | |
791 | sh_hdmi_read_edid(hdmi); | |
792 | msleep(10); | |
793 | sh_hdmi_configure(hdmi); | |
794 | /* Switched to another (d) power-save mode */ | |
795 | msleep(10); | |
796 | ||
797 | if (!hdmi->info) | |
6de9edd5 | 798 | goto out; |
6011bdea | 799 | |
1c120deb GL |
800 | ch = hdmi->info->par; |
801 | ||
6011bdea GL |
802 | acquire_console_sem(); |
803 | ||
804 | /* HDMI plug in */ | |
1c120deb | 805 | ch->display_var = hdmi->var; |
6de9edd5 | 806 | if (hdmi->info->state != FBINFO_STATE_RUNNING) { |
6011bdea | 807 | fb_set_suspend(hdmi->info, 0); |
6de9edd5 GL |
808 | } else { |
809 | if (lock_fb_info(hdmi->info)) { | |
6aa966e6 | 810 | sh_hdmi_display_on(hdmi, hdmi->info); |
6de9edd5 GL |
811 | unlock_fb_info(hdmi->info); |
812 | } | |
813 | } | |
6011bdea GL |
814 | |
815 | release_console_sem(); | |
816 | } else { | |
817 | if (!hdmi->info) | |
6de9edd5 | 818 | goto out; |
6011bdea GL |
819 | |
820 | acquire_console_sem(); | |
821 | ||
822 | /* HDMI disconnect */ | |
823 | fb_set_suspend(hdmi->info, 1); | |
824 | ||
825 | release_console_sem(); | |
826 | pm_runtime_put(hdmi->dev); | |
827 | } | |
828 | ||
6de9edd5 GL |
829 | out: |
830 | mutex_unlock(&hdmi->mutex); | |
831 | ||
6aa966e6 | 832 | dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev); |
6011bdea GL |
833 | } |
834 | ||
6de9edd5 GL |
835 | static int sh_hdmi_notify(struct notifier_block *nb, |
836 | unsigned long action, void *data); | |
837 | ||
838 | static struct notifier_block sh_hdmi_notifier = { | |
839 | .notifier_call = sh_hdmi_notify, | |
840 | }; | |
841 | ||
842 | static int sh_hdmi_notify(struct notifier_block *nb, | |
843 | unsigned long action, void *data) | |
844 | { | |
845 | struct fb_event *event = data; | |
846 | struct fb_info *info = event->info; | |
847 | struct sh_mobile_lcdc_chan *ch = info->par; | |
848 | struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg; | |
849 | struct sh_hdmi *hdmi = board_cfg->board_data; | |
850 | ||
851 | if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info) | |
852 | return NOTIFY_DONE; | |
853 | ||
854 | switch(action) { | |
855 | case FB_EVENT_FB_REGISTERED: | |
6aa966e6 | 856 | /* Unneeded, activation taken care by sh_hdmi_display_on() */ |
6de9edd5 GL |
857 | break; |
858 | case FB_EVENT_FB_UNREGISTERED: | |
859 | /* | |
860 | * We are called from unregister_framebuffer() with the | |
861 | * info->lock held. This is bad for us, because we can race with | |
862 | * the scheduled work, which has to call fb_set_suspend(), which | |
6aa966e6 GL |
863 | * takes info->lock internally, so, sh_hdmi_edid_work_fn() |
864 | * cannot take and hold info->lock for the whole function | |
865 | * duration. Using an additional lock creates a classical AB-BA | |
866 | * lock up. Therefore, we have to release the info->lock | |
867 | * temporarily, synchronise with the work queue and re-acquire | |
868 | * the info->lock. | |
6de9edd5 GL |
869 | */ |
870 | unlock_fb_info(hdmi->info); | |
871 | mutex_lock(&hdmi->mutex); | |
872 | hdmi->info = NULL; | |
873 | mutex_unlock(&hdmi->mutex); | |
874 | lock_fb_info(hdmi->info); | |
875 | return NOTIFY_OK; | |
876 | } | |
877 | return NOTIFY_DONE; | |
878 | } | |
879 | ||
6011bdea GL |
880 | static int __init sh_hdmi_probe(struct platform_device *pdev) |
881 | { | |
882 | struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data; | |
883 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6de9edd5 | 884 | struct sh_mobile_lcdc_board_cfg *board_cfg; |
6011bdea GL |
885 | int irq = platform_get_irq(pdev, 0), ret; |
886 | struct sh_hdmi *hdmi; | |
887 | long rate; | |
888 | ||
889 | if (!res || !pdata || irq < 0) | |
890 | return -ENODEV; | |
891 | ||
892 | hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL); | |
893 | if (!hdmi) { | |
894 | dev_err(&pdev->dev, "Cannot allocate device data\n"); | |
895 | return -ENOMEM; | |
896 | } | |
897 | ||
6de9edd5 | 898 | mutex_init(&hdmi->mutex); |
6011bdea GL |
899 | hdmi->dev = &pdev->dev; |
900 | ||
901 | hdmi->hdmi_clk = clk_get(&pdev->dev, "ick"); | |
902 | if (IS_ERR(hdmi->hdmi_clk)) { | |
903 | ret = PTR_ERR(hdmi->hdmi_clk); | |
904 | dev_err(&pdev->dev, "Unable to get clock: %d\n", ret); | |
905 | goto egetclk; | |
906 | } | |
907 | ||
44432407 GL |
908 | /* TODO: reconfigure the clock on monitor plug in */ |
909 | rate = PICOS2KHZ(pdata->lcd_chan->lcd_cfg[0].pixclock) * 1000; | |
6011bdea GL |
910 | |
911 | rate = clk_round_rate(hdmi->hdmi_clk, rate); | |
912 | if (rate < 0) { | |
913 | ret = rate; | |
914 | dev_err(&pdev->dev, "Cannot get suitable rate: %ld\n", rate); | |
915 | goto erate; | |
916 | } | |
917 | ||
918 | ret = clk_set_rate(hdmi->hdmi_clk, rate); | |
919 | if (ret < 0) { | |
920 | dev_err(&pdev->dev, "Cannot set rate %ld: %d\n", rate, ret); | |
921 | goto erate; | |
922 | } | |
923 | ||
6aa966e6 | 924 | dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", rate); |
6011bdea GL |
925 | |
926 | ret = clk_enable(hdmi->hdmi_clk); | |
927 | if (ret < 0) { | |
928 | dev_err(&pdev->dev, "Cannot enable clock: %d\n", ret); | |
929 | goto eclkenable; | |
930 | } | |
931 | ||
932 | dev_info(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate); | |
933 | ||
934 | if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) { | |
935 | dev_err(&pdev->dev, "HDMI register region already claimed\n"); | |
936 | ret = -EBUSY; | |
937 | goto ereqreg; | |
938 | } | |
939 | ||
940 | hdmi->base = ioremap(res->start, resource_size(res)); | |
941 | if (!hdmi->base) { | |
942 | dev_err(&pdev->dev, "HDMI register region already claimed\n"); | |
943 | ret = -ENOMEM; | |
944 | goto emap; | |
945 | } | |
946 | ||
947 | platform_set_drvdata(pdev, hdmi); | |
948 | ||
949 | #if 1 | |
950 | /* Product and revision IDs are 0 in sh-mobile version */ | |
951 | dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n", | |
952 | hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID)); | |
953 | #endif | |
954 | ||
955 | /* Set up LCDC callbacks */ | |
6de9edd5 GL |
956 | board_cfg = &pdata->lcd_chan->board_cfg; |
957 | board_cfg->owner = THIS_MODULE; | |
958 | board_cfg->board_data = hdmi; | |
6aa966e6 GL |
959 | board_cfg->display_on = sh_hdmi_display_on; |
960 | board_cfg->display_off = sh_hdmi_display_off; | |
6011bdea | 961 | |
6aa966e6 | 962 | INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn); |
6011bdea GL |
963 | |
964 | pm_runtime_enable(&pdev->dev); | |
965 | pm_runtime_resume(&pdev->dev); | |
966 | ||
967 | ret = request_irq(irq, sh_hdmi_hotplug, 0, | |
968 | dev_name(&pdev->dev), hdmi); | |
969 | if (ret < 0) { | |
970 | dev_err(&pdev->dev, "Unable to request irq: %d\n", ret); | |
971 | goto ereqirq; | |
972 | } | |
973 | ||
974 | return 0; | |
975 | ||
976 | ereqirq: | |
977 | pm_runtime_disable(&pdev->dev); | |
978 | iounmap(hdmi->base); | |
979 | emap: | |
980 | release_mem_region(res->start, resource_size(res)); | |
981 | ereqreg: | |
982 | clk_disable(hdmi->hdmi_clk); | |
983 | eclkenable: | |
984 | erate: | |
985 | clk_put(hdmi->hdmi_clk); | |
986 | egetclk: | |
6de9edd5 | 987 | mutex_destroy(&hdmi->mutex); |
6011bdea GL |
988 | kfree(hdmi); |
989 | ||
990 | return ret; | |
991 | } | |
992 | ||
993 | static int __exit sh_hdmi_remove(struct platform_device *pdev) | |
994 | { | |
995 | struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data; | |
996 | struct sh_hdmi *hdmi = platform_get_drvdata(pdev); | |
997 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6de9edd5 | 998 | struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg; |
6011bdea GL |
999 | int irq = platform_get_irq(pdev, 0); |
1000 | ||
6de9edd5 GL |
1001 | board_cfg->display_on = NULL; |
1002 | board_cfg->display_off = NULL; | |
1003 | board_cfg->board_data = NULL; | |
1004 | board_cfg->owner = NULL; | |
6011bdea | 1005 | |
6de9edd5 | 1006 | /* No new work will be scheduled, wait for running ISR */ |
6011bdea | 1007 | free_irq(irq, hdmi); |
6de9edd5 | 1008 | /* Wait for already scheduled work */ |
6011bdea | 1009 | cancel_delayed_work_sync(&hdmi->edid_work); |
6de9edd5 | 1010 | pm_runtime_disable(&pdev->dev); |
6011bdea GL |
1011 | clk_disable(hdmi->hdmi_clk); |
1012 | clk_put(hdmi->hdmi_clk); | |
1013 | iounmap(hdmi->base); | |
1014 | release_mem_region(res->start, resource_size(res)); | |
6de9edd5 | 1015 | mutex_destroy(&hdmi->mutex); |
6011bdea GL |
1016 | kfree(hdmi); |
1017 | ||
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | static struct platform_driver sh_hdmi_driver = { | |
1022 | .remove = __exit_p(sh_hdmi_remove), | |
1023 | .driver = { | |
1024 | .name = "sh-mobile-hdmi", | |
1025 | }, | |
1026 | }; | |
1027 | ||
1028 | static int __init sh_hdmi_init(void) | |
1029 | { | |
1030 | return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe); | |
1031 | } | |
1032 | module_init(sh_hdmi_init); | |
1033 | ||
1034 | static void __exit sh_hdmi_exit(void) | |
1035 | { | |
1036 | platform_driver_unregister(&sh_hdmi_driver); | |
1037 | } | |
1038 | module_exit(sh_hdmi_exit); | |
1039 | ||
1040 | MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>"); | |
1041 | MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver"); | |
1042 | MODULE_LICENSE("GPL v2"); |