Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver | |
3 | * | |
4 | * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de> | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General | |
7 | * Public License. See the file COPYING in the main directory of this | |
8 | * archive for more details. | |
9 | */ | |
10 | ||
11 | ||
12 | #ifndef __SAVAGEFB_H__ | |
13 | #define __SAVAGEFB_H__ | |
14 | ||
15 | #include <linux/i2c.h> | |
1da177e4 | 16 | #include <linux/i2c-algo-bit.h> |
22d832ed AD |
17 | #include <linux/mutex.h> |
18 | #include <video/vga.h> | |
1da177e4 LT |
19 | #include "../edid.h" |
20 | ||
21 | #ifdef SAVAGEFB_DEBUG | |
22 | # define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x)); | |
23 | #else | |
24 | # define DBG(x) | |
25 | # define SavagePrintRegs(...) | |
26 | #endif | |
27 | ||
28 | ||
29 | #define PCI_CHIP_SAVAGE4 0x8a22 | |
30 | #define PCI_CHIP_SAVAGE3D 0x8a20 | |
31 | #define PCI_CHIP_SAVAGE3D_MV 0x8a21 | |
32 | #define PCI_CHIP_SAVAGE2000 0x9102 | |
33 | #define PCI_CHIP_SAVAGE_MX_MV 0x8c10 | |
34 | #define PCI_CHIP_SAVAGE_MX 0x8c11 | |
35 | #define PCI_CHIP_SAVAGE_IX_MV 0x8c12 | |
36 | #define PCI_CHIP_SAVAGE_IX 0x8c13 | |
37 | #define PCI_CHIP_PROSAVAGE_PM 0x8a25 | |
38 | #define PCI_CHIP_PROSAVAGE_KM 0x8a26 | |
39 | /* Twister is a code name; hope I get the real name soon. */ | |
40 | #define PCI_CHIP_S3TWISTER_P 0x8d01 | |
41 | #define PCI_CHIP_S3TWISTER_K 0x8d02 | |
42 | #define PCI_CHIP_PROSAVAGE_DDR 0x8d03 | |
43 | #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04 | |
44 | #define PCI_CHIP_SUPSAV_MX128 0x8c22 | |
45 | #define PCI_CHIP_SUPSAV_MX64 0x8c24 | |
46 | #define PCI_CHIP_SUPSAV_MX64C 0x8c26 | |
47 | #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a | |
48 | #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b | |
49 | #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c | |
50 | #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d | |
51 | #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e | |
52 | #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f | |
53 | ||
54 | ||
55 | ||
56 | #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) | |
57 | ||
58 | #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE)) | |
59 | ||
60 | #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) | |
61 | ||
62 | #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) | |
63 | ||
1da177e4 LT |
64 | /* Chip tags. These are used to group the adapters into |
65 | * related families. | |
66 | */ | |
67 | ||
68 | typedef enum { | |
69 | S3_UNKNOWN = 0, | |
70 | S3_SAVAGE3D, | |
71 | S3_SAVAGE_MX, | |
72 | S3_SAVAGE4, | |
73 | S3_PROSAVAGE, | |
74 | S3_SUPERSAVAGE, | |
75 | S3_SAVAGE2000, | |
76 | S3_LAST | |
77 | } savage_chipset; | |
78 | ||
79 | #define BIOS_BSIZE 1024 | |
80 | #define BIOS_BASE 0xc0000 | |
81 | ||
82 | #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */ | |
83 | #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000 | |
84 | #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */ | |
85 | #define SAVAGE_NEWMMIO_VGABASE 0x8000 | |
86 | ||
87 | #define BASE_FREQ 14318 | |
88 | #define HALF_BASE_FREQ 7159 | |
89 | ||
90 | #define FIFO_CONTROL_REG 0x8200 | |
91 | #define MIU_CONTROL_REG 0x8204 | |
92 | #define STREAMS_TIMEOUT_REG 0x8208 | |
93 | #define MISC_TIMEOUT_REG 0x820c | |
94 | ||
95 | #define MONO_PAT_0 0xa4e8 | |
96 | #define MONO_PAT_1 0xa4ec | |
97 | ||
98 | #define MAXFIFO 0x7f00 | |
99 | ||
100 | #define BCI_CMD_NOP 0x40000000 | |
101 | #define BCI_CMD_SETREG 0x96000000 | |
102 | #define BCI_CMD_RECT 0x48000000 | |
103 | #define BCI_CMD_RECT_XP 0x01000000 | |
104 | #define BCI_CMD_RECT_YP 0x02000000 | |
105 | #define BCI_CMD_SEND_COLOR 0x00008000 | |
106 | #define BCI_CMD_DEST_GBD 0x00000000 | |
107 | #define BCI_CMD_SRC_GBD 0x00000020 | |
108 | #define BCI_CMD_SRC_SOLID 0x00000000 | |
109 | #define BCI_CMD_SRC_MONO 0x00000060 | |
110 | #define BCI_CMD_CLIP_NEW 0x00006000 | |
111 | #define BCI_CMD_CLIP_LR 0x00004000 | |
112 | ||
113 | #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) | |
114 | #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) | |
115 | #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) | |
116 | #define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF)) | |
117 | #define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF)) | |
118 | ||
119 | #define BCI_GBD1 0xE0 | |
120 | #define BCI_GBD2 0xE1 | |
121 | ||
122 | #define BCI_BUFFER_OFFSET 0x10000 | |
123 | #define BCI_SIZE 0x4000 | |
124 | ||
125 | #define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++) | |
126 | ||
127 | #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) | |
128 | #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) | |
129 | #define BCI_CMD_SEND_COLOR 0x00008000 | |
130 | ||
13776711 AD |
131 | #define DISP_CRT 1 |
132 | #define DISP_LCD 2 | |
133 | #define DISP_DFP 3 | |
134 | ||
1da177e4 LT |
135 | struct xtimings { |
136 | unsigned int Clock; | |
137 | unsigned int HDisplay; | |
138 | unsigned int HSyncStart; | |
139 | unsigned int HSyncEnd; | |
140 | unsigned int HTotal; | |
141 | unsigned int HAdjusted; | |
142 | unsigned int VDisplay; | |
143 | unsigned int VSyncStart; | |
144 | unsigned int VSyncEnd; | |
145 | unsigned int VTotal; | |
146 | unsigned int sync; | |
147 | int dblscan; | |
148 | int interlaced; | |
149 | }; | |
150 | ||
2356614b AD |
151 | struct savage_reg { |
152 | unsigned char MiscOutReg; /* Misc */ | |
153 | unsigned char CRTC[25]; /* Crtc Controller */ | |
154 | unsigned char Sequencer[5]; /* Video Sequencer */ | |
155 | unsigned char Graphics[9]; /* Video Graphics */ | |
25985edc | 156 | unsigned char Attribute[21]; /* Video Attribute */ |
1da177e4 | 157 | |
2356614b AD |
158 | unsigned int mode, refresh; |
159 | unsigned char SR08, SR0E, SR0F; | |
160 | unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30; | |
161 | unsigned char SR54[8]; | |
162 | unsigned char Clock; | |
163 | unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C; | |
164 | unsigned char CR40, CR41, CR42, CR43, CR45; | |
165 | unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E; | |
166 | unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F; | |
167 | unsigned char CR86, CR88; | |
168 | unsigned char CR90, CR91, CRB0; | |
169 | unsigned int STREAMS[22]; /* yuck, streams regs */ | |
170 | unsigned int MMPR0, MMPR1, MMPR2, MMPR3; | |
171 | }; | |
1da177e4 LT |
172 | /* --------------------------------------------------------------------- */ |
173 | ||
174 | #define NR_PALETTE 256 | |
175 | ||
176 | ||
177 | struct savagefb_par; | |
178 | ||
179 | struct savagefb_i2c_chan { | |
180 | struct savagefb_par *par; | |
181 | struct i2c_adapter adapter; | |
182 | struct i2c_algo_bit_data algo; | |
183 | volatile u8 __iomem *ioaddr; | |
184 | u32 reg; | |
185 | }; | |
186 | ||
187 | struct savagefb_par { | |
188 | struct pci_dev *pcidev; | |
189 | savage_chipset chip; | |
190 | struct savagefb_i2c_chan chan; | |
2356614b AD |
191 | struct savage_reg state; |
192 | struct savage_reg save; | |
22d832ed AD |
193 | struct savage_reg initial; |
194 | struct vgastate vgastate; | |
195 | struct mutex open_lock; | |
1da177e4 LT |
196 | unsigned char *edid; |
197 | u32 pseudo_palette[16]; | |
22d832ed | 198 | u32 open_count; |
1cc650c6 | 199 | int paletteEnabled; |
13776711 AD |
200 | int pm_state; |
201 | int display_type; | |
202 | int dvi; | |
203 | int crtonly; | |
1da177e4 LT |
204 | int dacSpeedBpp; |
205 | int maxClock; | |
206 | int minClock; | |
207 | int numClocks; | |
208 | int clock[4]; | |
2356614b | 209 | int MCLK, REFCLK, LCDclk; |
1da177e4 | 210 | struct { |
22d832ed | 211 | void __iomem *vbase; |
1da177e4 LT |
212 | u32 pbase; |
213 | u32 len; | |
214 | #ifdef CONFIG_MTRR | |
215 | int mtrr; | |
216 | #endif | |
217 | } video; | |
218 | ||
219 | struct { | |
22d832ed | 220 | void __iomem *vbase; |
1da177e4 LT |
221 | u32 pbase; |
222 | u32 len; | |
223 | } mmio; | |
224 | ||
225 | volatile u32 __iomem *bci_base; | |
226 | unsigned int bci_ptr; | |
1da177e4 LT |
227 | u32 cob_offset; |
228 | u32 cob_size; | |
229 | int cob_index; | |
230 | ||
231 | void (*SavageWaitIdle) (struct savagefb_par *par); | |
232 | void (*SavageWaitFifo) (struct savagefb_par *par, int space); | |
233 | ||
1da177e4 LT |
234 | int HorizScaleFactor; |
235 | ||
236 | /* Panels size */ | |
237 | int SavagePanelWidth; | |
238 | int SavagePanelHeight; | |
239 | ||
240 | struct { | |
241 | u16 red, green, blue, transp; | |
242 | } palette[NR_PALETTE]; | |
243 | ||
244 | int depth; | |
245 | int vwidth; | |
1da177e4 LT |
246 | }; |
247 | ||
248 | #define BCI_BD_BW_DISABLE 0x10000000 | |
249 | #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) | |
250 | #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) | |
251 | ||
252 | ||
253 | /* IO functions */ | |
1cc650c6 AD |
254 | static inline u8 savage_in8(u32 addr, struct savagefb_par *par) |
255 | { | |
256 | return readb(par->mmio.vbase + addr); | |
257 | } | |
258 | ||
259 | static inline u16 savage_in16(u32 addr, struct savagefb_par *par) | |
260 | { | |
261 | return readw(par->mmio.vbase + addr); | |
262 | } | |
263 | ||
264 | static inline u32 savage_in32(u32 addr, struct savagefb_par *par) | |
265 | { | |
266 | return readl(par->mmio.vbase + addr); | |
267 | } | |
268 | ||
269 | static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par) | |
270 | { | |
271 | writeb(val, par->mmio.vbase + addr); | |
272 | } | |
273 | ||
274 | static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par) | |
275 | { | |
276 | writew(val, par->mmio.vbase + addr); | |
277 | } | |
278 | ||
279 | static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par) | |
280 | { | |
281 | writel(val, par->mmio.vbase + addr); | |
282 | } | |
283 | ||
284 | static inline u8 vga_in8(int addr, struct savagefb_par *par) | |
285 | { | |
286 | return savage_in8(0x8000 + addr, par); | |
287 | } | |
288 | ||
289 | static inline u16 vga_in16(int addr, struct savagefb_par *par) | |
290 | { | |
291 | return savage_in16(0x8000 + addr, par); | |
292 | } | |
293 | ||
294 | static inline u8 vga_in32(int addr, struct savagefb_par *par) | |
295 | { | |
296 | return savage_in32(0x8000 + addr, par); | |
297 | } | |
298 | ||
299 | static inline void vga_out8(int addr, u8 val, struct savagefb_par *par) | |
300 | { | |
301 | savage_out8(0x8000 + addr, val, par); | |
302 | } | |
303 | ||
304 | static inline void vga_out16(int addr, u16 val, struct savagefb_par *par) | |
305 | { | |
306 | savage_out16(0x8000 + addr, val, par); | |
307 | } | |
308 | ||
309 | static inline void vga_out32(int addr, u32 val, struct savagefb_par *par) | |
310 | { | |
311 | savage_out32(0x8000 + addr, val, par); | |
312 | } | |
1da177e4 | 313 | |
1cc650c6 AD |
314 | static inline u8 VGArCR (u8 index, struct savagefb_par *par) |
315 | { | |
316 | vga_out8(0x3d4, index, par); | |
317 | return vga_in8(0x3d5, par); | |
318 | } | |
319 | ||
320 | static inline u8 VGArGR (u8 index, struct savagefb_par *par) | |
321 | { | |
322 | vga_out8(0x3ce, index, par); | |
323 | return vga_in8(0x3cf, par); | |
324 | } | |
325 | ||
326 | static inline u8 VGArSEQ (u8 index, struct savagefb_par *par) | |
327 | { | |
328 | vga_out8(0x3c4, index, par); | |
329 | return vga_in8(0x3c5, par); | |
330 | } | |
1da177e4 | 331 | |
1cc650c6 AD |
332 | static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par) |
333 | { | |
334 | vga_out8(0x3d4, index, par); | |
335 | vga_out8(0x3d5, val, par); | |
336 | } | |
1da177e4 | 337 | |
1cc650c6 AD |
338 | static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par) |
339 | { | |
340 | vga_out8(0x3ce, index, par); | |
341 | vga_out8(0x3cf, val, par); | |
342 | } | |
1da177e4 | 343 | |
1cc650c6 AD |
344 | static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par) |
345 | { | |
346 | vga_out8(0x3c4, index, par); | |
347 | vga_out8 (0x3c5, val, par); | |
348 | } | |
1da177e4 | 349 | |
1cc650c6 | 350 | static inline void VGAenablePalette(struct savagefb_par *par) |
1da177e4 | 351 | { |
1cc650c6 AD |
352 | u8 tmp; |
353 | ||
354 | tmp = vga_in8(0x3da, par); | |
355 | vga_out8(0x3c0, 0x00, par); | |
356 | par->paletteEnabled = 1; | |
1da177e4 LT |
357 | } |
358 | ||
1cc650c6 | 359 | static inline void VGAdisablePalette(struct savagefb_par *par) |
1da177e4 | 360 | { |
1cc650c6 AD |
361 | u8 tmp; |
362 | ||
363 | tmp = vga_in8(0x3da, par); | |
364 | vga_out8(0x3c0, 0x20, par); | |
365 | par->paletteEnabled = 0; | |
1da177e4 LT |
366 | } |
367 | ||
1cc650c6 | 368 | static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par) |
1da177e4 | 369 | { |
1cc650c6 AD |
370 | u8 tmp; |
371 | ||
372 | if (par->paletteEnabled) | |
373 | index &= ~0x20; | |
374 | else | |
375 | index |= 0x20; | |
376 | ||
377 | tmp = vga_in8(0x3da, par); | |
378 | vga_out8(0x3c0, index, par); | |
379 | vga_out8 (0x3c0, value, par); | |
1da177e4 LT |
380 | } |
381 | ||
1cc650c6 AD |
382 | static inline void VGAwMISC(u8 value, struct savagefb_par *par) |
383 | { | |
384 | vga_out8(0x3c2, value, par); | |
385 | } | |
1da177e4 LT |
386 | |
387 | #ifndef CONFIG_FB_SAVAGE_ACCEL | |
388 | #define savagefb_set_clip(x) | |
389 | #endif | |
390 | ||
1cc650c6 AD |
391 | static inline void VerticalRetraceWait(struct savagefb_par *par) |
392 | { | |
393 | vga_out8(0x3d4, 0x17, par); | |
394 | if (vga_in8(0x3d5, par) & 0x80) { | |
395 | while ((vga_in8(0x3da, par) & 0x08) == 0x08); | |
396 | while ((vga_in8(0x3da, par) & 0x08) == 0x00); | |
397 | } | |
1da177e4 LT |
398 | } |
399 | ||
13776711 | 400 | extern int savagefb_probe_i2c_connector(struct fb_info *info, |
1da177e4 LT |
401 | u8 **out_edid); |
402 | extern void savagefb_create_i2c_busses(struct fb_info *info); | |
403 | extern void savagefb_delete_i2c_busses(struct fb_info *info); | |
404 | extern int savagefb_sync(struct fb_info *info); | |
405 | extern void savagefb_copyarea(struct fb_info *info, | |
406 | const struct fb_copyarea *region); | |
407 | extern void savagefb_fillrect(struct fb_info *info, | |
408 | const struct fb_fillrect *rect); | |
409 | extern void savagefb_imageblit(struct fb_info *info, | |
410 | const struct fb_image *image); | |
411 | ||
412 | ||
413 | #endif /* __SAVAGEFB_H__ */ |