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a268422d OZ |
1 | /* |
2 | * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge | |
3 | * | |
4 | * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file COPYING in the main directory of this archive for | |
8 | * more details. | |
9 | * | |
10 | * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) | |
11 | * which is based on the code of neofb. | |
12 | */ | |
13 | ||
14 | #include <linux/version.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/tty.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/fb.h> | |
24 | #include <linux/svga.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */ | |
28 | #include <video/vga.h> | |
29 | ||
30 | #ifdef CONFIG_MTRR | |
31 | #include <asm/mtrr.h> | |
32 | #endif | |
33 | ||
34 | struct s3fb_info { | |
35 | int chip, rev, mclk_freq; | |
36 | int mtrr_reg; | |
37 | struct vgastate state; | |
38 | struct mutex open_lock; | |
39 | unsigned int ref_count; | |
40 | u32 pseudo_palette[16]; | |
41 | }; | |
42 | ||
43 | ||
44 | /* ------------------------------------------------------------------------- */ | |
45 | ||
46 | static const struct svga_fb_format s3fb_formats[] = { | |
47 | { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, | |
48 | FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16}, | |
49 | { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, | |
50 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, | |
51 | { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1, | |
52 | FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, | |
53 | { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, | |
54 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8}, | |
55 | {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, | |
56 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, | |
57 | {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, | |
58 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, | |
59 | {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, | |
60 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, | |
61 | {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, | |
62 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, | |
63 | SVGA_FORMAT_END | |
64 | }; | |
65 | ||
66 | ||
67 | static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, | |
249bdbbf | 68 | 35000, 240000, 14318}; |
a268422d OZ |
69 | |
70 | static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; | |
71 | ||
72 | static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+", | |
73 | "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX", | |
74 | "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge", | |
75 | "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", | |
76 | "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P"}; | |
77 | ||
78 | #define CHIP_UNKNOWN 0x00 | |
79 | #define CHIP_732_TRIO32 0x01 | |
80 | #define CHIP_764_TRIO64 0x02 | |
81 | #define CHIP_765_TRIO64VP 0x03 | |
82 | #define CHIP_767_TRIO64UVP 0x04 | |
83 | #define CHIP_775_TRIO64V2_DX 0x05 | |
84 | #define CHIP_785_TRIO64V2_GX 0x06 | |
85 | #define CHIP_551_PLATO_PX 0x07 | |
86 | #define CHIP_M65_AURORA64VP 0x08 | |
87 | #define CHIP_325_VIRGE 0x09 | |
88 | #define CHIP_988_VIRGE_VX 0x0A | |
89 | #define CHIP_375_VIRGE_DX 0x0B | |
90 | #define CHIP_385_VIRGE_GX 0x0C | |
91 | #define CHIP_356_VIRGE_GX2 0x0D | |
92 | #define CHIP_357_VIRGE_GX2P 0x0E | |
93 | #define CHIP_359_VIRGE_GX2P 0x0F | |
94 | ||
95 | #define CHIP_XXX_TRIO 0x80 | |
96 | #define CHIP_XXX_TRIO64V2_DXGX 0x81 | |
97 | #define CHIP_XXX_VIRGE_DXGX 0x82 | |
98 | ||
99 | #define CHIP_UNDECIDED_FLAG 0x80 | |
100 | #define CHIP_MASK 0xFF | |
101 | ||
102 | /* CRT timing register sets */ | |
103 | ||
104 | static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END}; | |
105 | static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END}; | |
106 | static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END}; | |
107 | static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END}; | |
108 | static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END}; | |
109 | static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; | |
110 | ||
111 | static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END}; | |
112 | static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END}; | |
113 | static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END}; | |
114 | static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; | |
115 | static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END}; | |
116 | static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; | |
117 | ||
118 | static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END}; | |
119 | static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END}; | |
120 | static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ | |
121 | ||
122 | static const struct svga_timing_regs s3_timing_regs = { | |
123 | s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, | |
124 | s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, | |
125 | s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs, | |
126 | s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs, | |
127 | }; | |
128 | ||
129 | ||
130 | /* ------------------------------------------------------------------------- */ | |
131 | ||
132 | /* Module parameters */ | |
133 | ||
134 | ||
a8140543 | 135 | static char *mode_option __devinitdata = "640x480-8@60"; |
a268422d OZ |
136 | |
137 | #ifdef CONFIG_MTRR | |
a8140543 | 138 | static int mtrr __devinitdata = 1; |
a268422d OZ |
139 | #endif |
140 | ||
141 | static int fasttext = 1; | |
142 | ||
143 | ||
144 | MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>"); | |
145 | MODULE_LICENSE("GPL"); | |
146 | MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge"); | |
147 | ||
a8140543 KH |
148 | module_param(mode_option, charp, 0444); |
149 | MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); | |
150 | module_param_named(mode, mode_option, charp, 0444); | |
151 | MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)"); | |
a268422d OZ |
152 | |
153 | #ifdef CONFIG_MTRR | |
154 | module_param(mtrr, int, 0444); | |
155 | MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); | |
156 | #endif | |
157 | ||
158 | module_param(fasttext, int, 0644); | |
159 | MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)"); | |
160 | ||
161 | ||
162 | /* ------------------------------------------------------------------------- */ | |
163 | ||
164 | /* Set font in S3 fast text mode */ | |
165 | ||
166 | static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) | |
167 | { | |
168 | const u8 *font = map->data; | |
75814d87 | 169 | u8 __iomem *fb = (u8 __iomem *) info->screen_base; |
a268422d OZ |
170 | int i, c; |
171 | ||
172 | if ((map->width != 8) || (map->height != 16) || | |
173 | (map->depth != 1) || (map->length != 256)) { | |
174 | printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", | |
175 | info->node, map->width, map->height, map->depth, map->length); | |
176 | return; | |
177 | } | |
178 | ||
179 | fb += 2; | |
180 | for (i = 0; i < map->height; i++) { | |
181 | for (c = 0; c < map->length; c++) { | |
75814d87 | 182 | fb_writeb(font[c * map->height + i], fb + c * 4); |
a268422d OZ |
183 | } |
184 | fb += 1024; | |
185 | } | |
186 | } | |
187 | ||
a268422d OZ |
188 | static struct fb_tile_ops s3fb_tile_ops = { |
189 | .fb_settile = svga_settile, | |
190 | .fb_tilecopy = svga_tilecopy, | |
191 | .fb_tilefill = svga_tilefill, | |
192 | .fb_tileblit = svga_tileblit, | |
193 | .fb_tilecursor = svga_tilecursor, | |
34ed25f5 | 194 | .fb_get_tilemax = svga_get_tilemax, |
a268422d OZ |
195 | }; |
196 | ||
197 | static struct fb_tile_ops s3fb_fast_tile_ops = { | |
198 | .fb_settile = s3fb_settile_fast, | |
199 | .fb_tilecopy = svga_tilecopy, | |
200 | .fb_tilefill = svga_tilefill, | |
201 | .fb_tileblit = svga_tileblit, | |
202 | .fb_tilecursor = svga_tilecursor, | |
34ed25f5 | 203 | .fb_get_tilemax = svga_get_tilemax, |
a268422d OZ |
204 | }; |
205 | ||
206 | ||
207 | /* ------------------------------------------------------------------------- */ | |
208 | ||
209 | /* image data is MSB-first, fb structure is MSB-first too */ | |
210 | static inline u32 expand_color(u32 c) | |
211 | { | |
212 | return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; | |
213 | } | |
214 | ||
215 | /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ | |
216 | static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) | |
217 | { | |
218 | u32 fg = expand_color(image->fg_color); | |
219 | u32 bg = expand_color(image->bg_color); | |
220 | const u8 *src1, *src; | |
221 | u8 __iomem *dst1; | |
222 | u32 __iomem *dst; | |
223 | u32 val; | |
224 | int x, y; | |
225 | ||
226 | src1 = image->data; | |
227 | dst1 = info->screen_base + (image->dy * info->fix.line_length) | |
228 | + ((image->dx / 8) * 4); | |
229 | ||
230 | for (y = 0; y < image->height; y++) { | |
231 | src = src1; | |
232 | dst = (u32 __iomem *) dst1; | |
233 | for (x = 0; x < image->width; x += 8) { | |
234 | val = *(src++) * 0x01010101; | |
235 | val = (val & fg) | (~val & bg); | |
236 | fb_writel(val, dst++); | |
237 | } | |
238 | src1 += image->width / 8; | |
239 | dst1 += info->fix.line_length; | |
240 | } | |
241 | ||
242 | } | |
243 | ||
244 | /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ | |
245 | static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
246 | { | |
247 | u32 fg = expand_color(rect->color); | |
248 | u8 __iomem *dst1; | |
249 | u32 __iomem *dst; | |
250 | int x, y; | |
251 | ||
252 | dst1 = info->screen_base + (rect->dy * info->fix.line_length) | |
253 | + ((rect->dx / 8) * 4); | |
254 | ||
255 | for (y = 0; y < rect->height; y++) { | |
256 | dst = (u32 __iomem *) dst1; | |
257 | for (x = 0; x < rect->width; x += 8) { | |
258 | fb_writel(fg, dst++); | |
259 | } | |
260 | dst1 += info->fix.line_length; | |
261 | } | |
262 | } | |
263 | ||
264 | ||
265 | /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ | |
266 | static inline u32 expand_pixel(u32 c) | |
267 | { | |
268 | return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | | |
269 | ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; | |
270 | } | |
271 | ||
272 | /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ | |
273 | static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) | |
274 | { | |
275 | u32 fg = image->fg_color * 0x11111111; | |
276 | u32 bg = image->bg_color * 0x11111111; | |
277 | const u8 *src1, *src; | |
278 | u8 __iomem *dst1; | |
279 | u32 __iomem *dst; | |
280 | u32 val; | |
281 | int x, y; | |
282 | ||
283 | src1 = image->data; | |
284 | dst1 = info->screen_base + (image->dy * info->fix.line_length) | |
285 | + ((image->dx / 8) * 4); | |
286 | ||
287 | for (y = 0; y < image->height; y++) { | |
288 | src = src1; | |
289 | dst = (u32 __iomem *) dst1; | |
290 | for (x = 0; x < image->width; x += 8) { | |
291 | val = expand_pixel(*(src++)); | |
292 | val = (val & fg) | (~val & bg); | |
293 | fb_writel(val, dst++); | |
294 | } | |
295 | src1 += image->width / 8; | |
296 | dst1 += info->fix.line_length; | |
297 | } | |
298 | } | |
299 | ||
300 | static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image) | |
301 | { | |
302 | if ((info->var.bits_per_pixel == 4) && (image->depth == 1) | |
303 | && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { | |
304 | if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) | |
305 | s3fb_iplan_imageblit(info, image); | |
306 | else | |
307 | s3fb_cfb4_imageblit(info, image); | |
308 | } else | |
309 | cfb_imageblit(info, image); | |
310 | } | |
311 | ||
312 | static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
313 | { | |
314 | if ((info->var.bits_per_pixel == 4) | |
315 | && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) | |
316 | && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) | |
317 | s3fb_iplan_fillrect(info, rect); | |
318 | else | |
319 | cfb_fillrect(info, rect); | |
320 | } | |
321 | ||
322 | ||
323 | ||
324 | /* ------------------------------------------------------------------------- */ | |
325 | ||
326 | ||
327 | static void s3_set_pixclock(struct fb_info *info, u32 pixclock) | |
328 | { | |
329 | u16 m, n, r; | |
330 | u8 regval; | |
249bdbbf | 331 | int rv; |
a268422d | 332 | |
249bdbbf OZ |
333 | rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node); |
334 | if (rv < 0) { | |
335 | printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); | |
336 | return; | |
337 | } | |
a268422d OZ |
338 | |
339 | /* Set VGA misc register */ | |
340 | regval = vga_r(NULL, VGA_MIS_R); | |
341 | vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); | |
342 | ||
343 | /* Set S3 clock registers */ | |
344 | vga_wseq(NULL, 0x12, ((n - 2) | (r << 5))); | |
345 | vga_wseq(NULL, 0x13, m - 2); | |
346 | ||
347 | udelay(1000); | |
348 | ||
349 | /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ | |
350 | regval = vga_rseq (NULL, 0x15); /* | 0x80; */ | |
351 | vga_wseq(NULL, 0x15, regval & ~(1<<5)); | |
352 | vga_wseq(NULL, 0x15, regval | (1<<5)); | |
353 | vga_wseq(NULL, 0x15, regval & ~(1<<5)); | |
354 | } | |
355 | ||
356 | ||
357 | /* Open framebuffer */ | |
358 | ||
359 | static int s3fb_open(struct fb_info *info, int user) | |
360 | { | |
361 | struct s3fb_info *par = info->par; | |
362 | ||
363 | mutex_lock(&(par->open_lock)); | |
364 | if (par->ref_count == 0) { | |
365 | memset(&(par->state), 0, sizeof(struct vgastate)); | |
366 | par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; | |
367 | par->state.num_crtc = 0x70; | |
368 | par->state.num_seq = 0x20; | |
369 | save_vga(&(par->state)); | |
370 | } | |
371 | ||
372 | par->ref_count++; | |
373 | mutex_unlock(&(par->open_lock)); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
378 | /* Close framebuffer */ | |
379 | ||
380 | static int s3fb_release(struct fb_info *info, int user) | |
381 | { | |
382 | struct s3fb_info *par = info->par; | |
383 | ||
384 | mutex_lock(&(par->open_lock)); | |
385 | if (par->ref_count == 0) { | |
386 | mutex_unlock(&(par->open_lock)); | |
387 | return -EINVAL; | |
388 | } | |
389 | ||
390 | if (par->ref_count == 1) | |
391 | restore_vga(&(par->state)); | |
392 | ||
393 | par->ref_count--; | |
394 | mutex_unlock(&(par->open_lock)); | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | /* Validate passed in var */ | |
400 | ||
401 | static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
402 | { | |
403 | struct s3fb_info *par = info->par; | |
404 | int rv, mem, step; | |
c3ca34f9 | 405 | u16 m, n, r; |
a268422d OZ |
406 | |
407 | /* Find appropriate format */ | |
408 | rv = svga_match_format (s3fb_formats, var, NULL); | |
d4b766a0 OZ |
409 | |
410 | /* 32bpp mode is not supported on VIRGE VX, | |
411 | 24bpp is not supported on others */ | |
412 | if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) | |
413 | rv = -EINVAL; | |
414 | ||
415 | if (rv < 0) { | |
a268422d OZ |
416 | printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); |
417 | return rv; | |
418 | } | |
419 | ||
420 | /* Do not allow to have real resoulution larger than virtual */ | |
421 | if (var->xres > var->xres_virtual) | |
422 | var->xres_virtual = var->xres; | |
423 | ||
424 | if (var->yres > var->yres_virtual) | |
425 | var->yres_virtual = var->yres; | |
426 | ||
427 | /* Round up xres_virtual to have proper alignment of lines */ | |
428 | step = s3fb_formats[rv].xresstep - 1; | |
429 | var->xres_virtual = (var->xres_virtual+step) & ~step; | |
430 | ||
431 | /* Check whether have enough memory */ | |
432 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; | |
c3ca34f9 | 433 | if (mem > info->screen_size) { |
a268422d OZ |
434 | printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", |
435 | info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); | |
436 | return -EINVAL; | |
437 | } | |
438 | ||
439 | rv = svga_check_timings (&s3_timing_regs, var, info->node); | |
c3ca34f9 | 440 | if (rv < 0) { |
a268422d OZ |
441 | printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); |
442 | return rv; | |
443 | } | |
444 | ||
c3ca34f9 KH |
445 | rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, |
446 | info->node); | |
447 | if (rv < 0) { | |
448 | printk(KERN_ERR "fb%d: invalid pixclock value requested\n", | |
449 | info->node); | |
450 | return rv; | |
451 | } | |
452 | ||
a268422d OZ |
453 | return 0; |
454 | } | |
455 | ||
456 | /* Set video mode from par */ | |
457 | ||
458 | static int s3fb_set_par(struct fb_info *info) | |
459 | { | |
460 | struct s3fb_info *par = info->par; | |
461 | u32 value, mode, hmul, offset_value, screen_size, multiplex; | |
462 | u32 bpp = info->var.bits_per_pixel; | |
463 | ||
464 | if (bpp != 0) { | |
465 | info->fix.ypanstep = 1; | |
466 | info->fix.line_length = (info->var.xres_virtual * bpp) / 8; | |
467 | ||
468 | info->flags &= ~FBINFO_MISC_TILEBLITTING; | |
469 | info->tileops = NULL; | |
470 | ||
34ed25f5 OZ |
471 | /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ |
472 | info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); | |
8db51668 | 473 | info->pixmap.blit_y = ~(u32)0; |
34ed25f5 | 474 | |
a268422d OZ |
475 | offset_value = (info->var.xres_virtual * bpp) / 64; |
476 | screen_size = info->var.yres_virtual * info->fix.line_length; | |
477 | } else { | |
478 | info->fix.ypanstep = 16; | |
479 | info->fix.line_length = 0; | |
480 | ||
481 | info->flags |= FBINFO_MISC_TILEBLITTING; | |
482 | info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; | |
34ed25f5 | 483 | |
8db51668 AD |
484 | /* supports 8x16 tiles only */ |
485 | info->pixmap.blit_x = 1 << (8 - 1); | |
486 | info->pixmap.blit_y = 1 << (16 - 1); | |
a268422d OZ |
487 | |
488 | offset_value = info->var.xres_virtual / 16; | |
489 | screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; | |
490 | } | |
491 | ||
492 | info->var.xoffset = 0; | |
493 | info->var.yoffset = 0; | |
494 | info->var.activate = FB_ACTIVATE_NOW; | |
495 | ||
496 | /* Unlock registers */ | |
497 | vga_wcrt(NULL, 0x38, 0x48); | |
498 | vga_wcrt(NULL, 0x39, 0xA5); | |
499 | vga_wseq(NULL, 0x08, 0x06); | |
500 | svga_wcrt_mask(0x11, 0x00, 0x80); | |
501 | ||
502 | /* Blank screen and turn off sync */ | |
503 | svga_wseq_mask(0x01, 0x20, 0x20); | |
504 | svga_wcrt_mask(0x17, 0x00, 0x80); | |
505 | ||
506 | /* Set default values */ | |
507 | svga_set_default_gfx_regs(); | |
508 | svga_set_default_atc_regs(); | |
509 | svga_set_default_seq_regs(); | |
510 | svga_set_default_crt_regs(); | |
511 | svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF); | |
512 | svga_wcrt_multi(s3_start_address_regs, 0); | |
513 | ||
514 | /* S3 specific initialization */ | |
515 | svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */ | |
516 | svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */ | |
517 | ||
518 | /* svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ? */ | |
519 | /* svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ? */ | |
520 | svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ? */ | |
521 | svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ? */ | |
522 | ||
523 | svga_wcrt_mask(0x5D, 0x00, 0x28); // Clear strange HSlen bits | |
524 | ||
525 | /* svga_wcrt_mask(0x58, 0x03, 0x03); */ | |
526 | ||
527 | /* svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */ | |
528 | /* svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */ | |
529 | ||
530 | ||
531 | /* Set the offset register */ | |
532 | pr_debug("fb%d: offset register : %d\n", info->node, offset_value); | |
533 | svga_wcrt_multi(s3_offset_regs, offset_value); | |
534 | ||
535 | vga_wcrt(NULL, 0x54, 0x18); /* M parameter */ | |
536 | vga_wcrt(NULL, 0x60, 0xff); /* N parameter */ | |
537 | vga_wcrt(NULL, 0x61, 0xff); /* L parameter */ | |
538 | vga_wcrt(NULL, 0x62, 0xff); /* L parameter */ | |
539 | ||
540 | vga_wcrt(NULL, 0x3A, 0x35); | |
541 | svga_wattr(0x33, 0x00); | |
542 | ||
543 | if (info->var.vmode & FB_VMODE_DOUBLE) | |
544 | svga_wcrt_mask(0x09, 0x80, 0x80); | |
545 | else | |
546 | svga_wcrt_mask(0x09, 0x00, 0x80); | |
547 | ||
548 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
549 | svga_wcrt_mask(0x42, 0x20, 0x20); | |
550 | else | |
551 | svga_wcrt_mask(0x42, 0x00, 0x20); | |
552 | ||
553 | /* Disable hardware graphics cursor */ | |
554 | svga_wcrt_mask(0x45, 0x00, 0x01); | |
555 | /* Disable Streams engine */ | |
556 | svga_wcrt_mask(0x67, 0x00, 0x0C); | |
557 | ||
558 | mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); | |
559 | ||
560 | /* S3 virge DX hack */ | |
561 | if (par->chip == CHIP_375_VIRGE_DX) { | |
562 | vga_wcrt(NULL, 0x86, 0x80); | |
563 | vga_wcrt(NULL, 0x90, 0x00); | |
564 | } | |
565 | ||
566 | /* S3 virge VX hack */ | |
567 | if (par->chip == CHIP_988_VIRGE_VX) { | |
568 | vga_wcrt(NULL, 0x50, 0x00); | |
569 | vga_wcrt(NULL, 0x67, 0x50); | |
570 | ||
571 | vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09); | |
572 | vga_wcrt(NULL, 0x66, 0x90); | |
573 | } | |
574 | ||
575 | svga_wcrt_mask(0x31, 0x00, 0x40); | |
576 | multiplex = 0; | |
577 | hmul = 1; | |
578 | ||
579 | /* Set mode-specific register values */ | |
580 | switch (mode) { | |
581 | case 0: | |
582 | pr_debug("fb%d: text mode\n", info->node); | |
583 | svga_set_textmode_vga_regs(); | |
584 | ||
585 | /* Set additional registers like in 8-bit mode */ | |
586 | svga_wcrt_mask(0x50, 0x00, 0x30); | |
587 | svga_wcrt_mask(0x67, 0x00, 0xF0); | |
588 | ||
589 | /* Disable enhanced mode */ | |
590 | svga_wcrt_mask(0x3A, 0x00, 0x30); | |
591 | ||
592 | if (fasttext) { | |
593 | pr_debug("fb%d: high speed text mode set\n", info->node); | |
594 | svga_wcrt_mask(0x31, 0x40, 0x40); | |
595 | } | |
596 | break; | |
597 | case 1: | |
598 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); | |
599 | vga_wgfx(NULL, VGA_GFX_MODE, 0x40); | |
600 | ||
601 | /* Set additional registers like in 8-bit mode */ | |
602 | svga_wcrt_mask(0x50, 0x00, 0x30); | |
603 | svga_wcrt_mask(0x67, 0x00, 0xF0); | |
604 | ||
605 | /* disable enhanced mode */ | |
606 | svga_wcrt_mask(0x3A, 0x00, 0x30); | |
607 | break; | |
608 | case 2: | |
609 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); | |
610 | ||
611 | /* Set additional registers like in 8-bit mode */ | |
612 | svga_wcrt_mask(0x50, 0x00, 0x30); | |
613 | svga_wcrt_mask(0x67, 0x00, 0xF0); | |
614 | ||
615 | /* disable enhanced mode */ | |
616 | svga_wcrt_mask(0x3A, 0x00, 0x30); | |
617 | break; | |
618 | case 3: | |
619 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); | |
620 | if (info->var.pixclock > 20000) { | |
621 | svga_wcrt_mask(0x50, 0x00, 0x30); | |
622 | svga_wcrt_mask(0x67, 0x00, 0xF0); | |
623 | } else { | |
624 | svga_wcrt_mask(0x50, 0x00, 0x30); | |
625 | svga_wcrt_mask(0x67, 0x10, 0xF0); | |
626 | multiplex = 1; | |
627 | } | |
628 | break; | |
629 | case 4: | |
630 | pr_debug("fb%d: 5/5/5 truecolor\n", info->node); | |
631 | if (par->chip == CHIP_988_VIRGE_VX) { | |
632 | if (info->var.pixclock > 20000) | |
633 | svga_wcrt_mask(0x67, 0x20, 0xF0); | |
634 | else | |
635 | svga_wcrt_mask(0x67, 0x30, 0xF0); | |
636 | } else { | |
637 | svga_wcrt_mask(0x50, 0x10, 0x30); | |
638 | svga_wcrt_mask(0x67, 0x30, 0xF0); | |
639 | hmul = 2; | |
640 | } | |
641 | break; | |
642 | case 5: | |
643 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); | |
644 | if (par->chip == CHIP_988_VIRGE_VX) { | |
645 | if (info->var.pixclock > 20000) | |
646 | svga_wcrt_mask(0x67, 0x40, 0xF0); | |
647 | else | |
648 | svga_wcrt_mask(0x67, 0x50, 0xF0); | |
649 | } else { | |
650 | svga_wcrt_mask(0x50, 0x10, 0x30); | |
651 | svga_wcrt_mask(0x67, 0x50, 0xF0); | |
652 | hmul = 2; | |
653 | } | |
654 | break; | |
655 | case 6: | |
656 | /* VIRGE VX case */ | |
657 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); | |
658 | svga_wcrt_mask(0x67, 0xD0, 0xF0); | |
659 | break; | |
660 | case 7: | |
661 | pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); | |
662 | svga_wcrt_mask(0x50, 0x30, 0x30); | |
663 | svga_wcrt_mask(0x67, 0xD0, 0xF0); | |
664 | break; | |
665 | default: | |
666 | printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); | |
667 | return -EINVAL; | |
668 | } | |
669 | ||
670 | if (par->chip != CHIP_988_VIRGE_VX) { | |
671 | svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10); | |
672 | svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80); | |
673 | } | |
674 | ||
675 | s3_set_pixclock(info, info->var.pixclock); | |
676 | svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1, | |
677 | (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, | |
678 | (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, | |
679 | hmul, info->node); | |
680 | ||
681 | /* Set interlaced mode start/end register */ | |
682 | value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; | |
683 | value = ((value * hmul) / 8) - 5; | |
684 | vga_wcrt(NULL, 0x3C, (value + 1) / 2); | |
685 | ||
75814d87 | 686 | memset_io(info->screen_base, 0x00, screen_size); |
a268422d OZ |
687 | /* Device and screen back on */ |
688 | svga_wcrt_mask(0x17, 0x80, 0x80); | |
689 | svga_wseq_mask(0x01, 0x00, 0x20); | |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
694 | /* Set a colour register */ | |
695 | ||
696 | static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
697 | u_int transp, struct fb_info *fb) | |
698 | { | |
699 | switch (fb->var.bits_per_pixel) { | |
700 | case 0: | |
701 | case 4: | |
702 | if (regno >= 16) | |
703 | return -EINVAL; | |
704 | ||
705 | if ((fb->var.bits_per_pixel == 4) && | |
706 | (fb->var.nonstd == 0)) { | |
707 | outb(0xF0, VGA_PEL_MSK); | |
708 | outb(regno*16, VGA_PEL_IW); | |
709 | } else { | |
710 | outb(0x0F, VGA_PEL_MSK); | |
711 | outb(regno, VGA_PEL_IW); | |
712 | } | |
713 | outb(red >> 10, VGA_PEL_D); | |
714 | outb(green >> 10, VGA_PEL_D); | |
715 | outb(blue >> 10, VGA_PEL_D); | |
716 | break; | |
717 | case 8: | |
718 | if (regno >= 256) | |
719 | return -EINVAL; | |
720 | ||
721 | outb(0xFF, VGA_PEL_MSK); | |
722 | outb(regno, VGA_PEL_IW); | |
723 | outb(red >> 10, VGA_PEL_D); | |
724 | outb(green >> 10, VGA_PEL_D); | |
725 | outb(blue >> 10, VGA_PEL_D); | |
726 | break; | |
727 | case 16: | |
728 | if (regno >= 16) | |
249bdbbf | 729 | return 0; |
a268422d OZ |
730 | |
731 | if (fb->var.green.length == 5) | |
732 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | | |
733 | ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); | |
734 | else if (fb->var.green.length == 6) | |
735 | ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | | |
736 | ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); | |
737 | else return -EINVAL; | |
738 | break; | |
739 | case 24: | |
740 | case 32: | |
741 | if (regno >= 16) | |
249bdbbf | 742 | return 0; |
a268422d | 743 | |
249bdbbf | 744 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | |
a268422d OZ |
745 | (green & 0xFF00) | ((blue & 0xFF00) >> 8); |
746 | break; | |
747 | default: | |
748 | return -EINVAL; | |
749 | } | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
754 | ||
755 | /* Set the display blanking state */ | |
756 | ||
757 | static int s3fb_blank(int blank_mode, struct fb_info *info) | |
758 | { | |
759 | switch (blank_mode) { | |
760 | case FB_BLANK_UNBLANK: | |
761 | pr_debug("fb%d: unblank\n", info->node); | |
762 | svga_wcrt_mask(0x56, 0x00, 0x06); | |
763 | svga_wseq_mask(0x01, 0x00, 0x20); | |
764 | break; | |
765 | case FB_BLANK_NORMAL: | |
766 | pr_debug("fb%d: blank\n", info->node); | |
767 | svga_wcrt_mask(0x56, 0x00, 0x06); | |
768 | svga_wseq_mask(0x01, 0x20, 0x20); | |
769 | break; | |
770 | case FB_BLANK_HSYNC_SUSPEND: | |
771 | pr_debug("fb%d: hsync\n", info->node); | |
772 | svga_wcrt_mask(0x56, 0x02, 0x06); | |
773 | svga_wseq_mask(0x01, 0x20, 0x20); | |
774 | break; | |
775 | case FB_BLANK_VSYNC_SUSPEND: | |
776 | pr_debug("fb%d: vsync\n", info->node); | |
777 | svga_wcrt_mask(0x56, 0x04, 0x06); | |
778 | svga_wseq_mask(0x01, 0x20, 0x20); | |
779 | break; | |
780 | case FB_BLANK_POWERDOWN: | |
781 | pr_debug("fb%d: sync down\n", info->node); | |
782 | svga_wcrt_mask(0x56, 0x06, 0x06); | |
783 | svga_wseq_mask(0x01, 0x20, 0x20); | |
784 | break; | |
785 | } | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | ||
791 | /* Pan the display */ | |
792 | ||
793 | static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) { | |
794 | ||
795 | unsigned int offset; | |
796 | ||
a268422d OZ |
797 | /* Calculate the offset */ |
798 | if (var->bits_per_pixel == 0) { | |
799 | offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2); | |
800 | offset = offset >> 2; | |
801 | } else { | |
802 | offset = (var->yoffset * info->fix.line_length) + | |
803 | (var->xoffset * var->bits_per_pixel / 8); | |
804 | offset = offset >> 2; | |
805 | } | |
806 | ||
807 | /* Set the offset */ | |
808 | svga_wcrt_multi(s3_start_address_regs, offset); | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | /* ------------------------------------------------------------------------- */ | |
814 | ||
815 | /* Frame buffer operations */ | |
816 | ||
817 | static struct fb_ops s3fb_ops = { | |
818 | .owner = THIS_MODULE, | |
819 | .fb_open = s3fb_open, | |
820 | .fb_release = s3fb_release, | |
821 | .fb_check_var = s3fb_check_var, | |
822 | .fb_set_par = s3fb_set_par, | |
823 | .fb_setcolreg = s3fb_setcolreg, | |
824 | .fb_blank = s3fb_blank, | |
825 | .fb_pan_display = s3fb_pan_display, | |
826 | .fb_fillrect = s3fb_fillrect, | |
827 | .fb_copyarea = cfb_copyarea, | |
828 | .fb_imageblit = s3fb_imageblit, | |
5a87ede9 | 829 | .fb_get_caps = svga_get_caps, |
a268422d OZ |
830 | }; |
831 | ||
832 | /* ------------------------------------------------------------------------- */ | |
833 | ||
834 | static int __devinit s3_identification(int chip) | |
835 | { | |
836 | if (chip == CHIP_XXX_TRIO) { | |
837 | u8 cr30 = vga_rcrt(NULL, 0x30); | |
838 | u8 cr2e = vga_rcrt(NULL, 0x2e); | |
839 | u8 cr2f = vga_rcrt(NULL, 0x2f); | |
840 | ||
841 | if ((cr30 == 0xE0) || (cr30 == 0xE1)) { | |
842 | if (cr2e == 0x10) | |
843 | return CHIP_732_TRIO32; | |
844 | if (cr2e == 0x11) { | |
845 | if (! (cr2f & 0x40)) | |
846 | return CHIP_764_TRIO64; | |
847 | else | |
848 | return CHIP_765_TRIO64VP; | |
849 | } | |
850 | } | |
851 | } | |
852 | ||
853 | if (chip == CHIP_XXX_TRIO64V2_DXGX) { | |
854 | u8 cr6f = vga_rcrt(NULL, 0x6f); | |
855 | ||
856 | if (! (cr6f & 0x01)) | |
857 | return CHIP_775_TRIO64V2_DX; | |
858 | else | |
859 | return CHIP_785_TRIO64V2_GX; | |
860 | } | |
861 | ||
862 | if (chip == CHIP_XXX_VIRGE_DXGX) { | |
863 | u8 cr6f = vga_rcrt(NULL, 0x6f); | |
864 | ||
865 | if (! (cr6f & 0x01)) | |
866 | return CHIP_375_VIRGE_DX; | |
867 | else | |
868 | return CHIP_385_VIRGE_GX; | |
869 | } | |
870 | ||
871 | return CHIP_UNKNOWN; | |
872 | } | |
873 | ||
874 | ||
875 | /* PCI probe */ | |
876 | ||
877 | static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
878 | { | |
879 | struct fb_info *info; | |
880 | struct s3fb_info *par; | |
881 | int rc; | |
882 | u8 regval, cr38, cr39; | |
883 | ||
884 | /* Ignore secondary VGA device because there is no VGA arbitration */ | |
885 | if (! svga_primary_device(dev)) { | |
886 | dev_info(&(dev->dev), "ignoring secondary device\n"); | |
887 | return -ENODEV; | |
888 | } | |
889 | ||
890 | /* Allocate and fill driver data structure */ | |
20e061fb | 891 | info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev)); |
a268422d OZ |
892 | if (!info) { |
893 | dev_err(&(dev->dev), "cannot allocate memory\n"); | |
894 | return -ENOMEM; | |
895 | } | |
896 | ||
897 | par = info->par; | |
898 | mutex_init(&par->open_lock); | |
899 | ||
900 | info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; | |
901 | info->fbops = &s3fb_ops; | |
902 | ||
903 | /* Prepare PCI device */ | |
904 | rc = pci_enable_device(dev); | |
905 | if (rc < 0) { | |
20e061fb | 906 | dev_err(info->dev, "cannot enable PCI device\n"); |
a268422d OZ |
907 | goto err_enable_device; |
908 | } | |
909 | ||
910 | rc = pci_request_regions(dev, "s3fb"); | |
911 | if (rc < 0) { | |
20e061fb | 912 | dev_err(info->dev, "cannot reserve framebuffer region\n"); |
a268422d OZ |
913 | goto err_request_regions; |
914 | } | |
915 | ||
916 | ||
917 | info->fix.smem_start = pci_resource_start(dev, 0); | |
918 | info->fix.smem_len = pci_resource_len(dev, 0); | |
919 | ||
920 | /* Map physical IO memory address into kernel space */ | |
921 | info->screen_base = pci_iomap(dev, 0, 0); | |
922 | if (! info->screen_base) { | |
923 | rc = -ENOMEM; | |
20e061fb | 924 | dev_err(info->dev, "iomap for framebuffer failed\n"); |
a268422d OZ |
925 | goto err_iomap; |
926 | } | |
927 | ||
928 | /* Unlock regs */ | |
929 | cr38 = vga_rcrt(NULL, 0x38); | |
930 | cr39 = vga_rcrt(NULL, 0x39); | |
931 | vga_wseq(NULL, 0x08, 0x06); | |
932 | vga_wcrt(NULL, 0x38, 0x48); | |
933 | vga_wcrt(NULL, 0x39, 0xA5); | |
934 | ||
935 | /* Find how many physical memory there is on card */ | |
936 | /* 0x36 register is accessible even if other registers are locked */ | |
937 | regval = vga_rcrt(NULL, 0x36); | |
938 | info->screen_size = s3_memsizes[regval >> 5] << 10; | |
939 | info->fix.smem_len = info->screen_size; | |
940 | ||
941 | par->chip = id->driver_data & CHIP_MASK; | |
942 | par->rev = vga_rcrt(NULL, 0x2f); | |
943 | if (par->chip & CHIP_UNDECIDED_FLAG) | |
944 | par->chip = s3_identification(par->chip); | |
945 | ||
946 | /* Find MCLK frequency */ | |
947 | regval = vga_rseq(NULL, 0x10); | |
948 | par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); | |
949 | par->mclk_freq = par->mclk_freq >> (regval >> 5); | |
950 | ||
951 | /* Restore locks */ | |
952 | vga_wcrt(NULL, 0x38, cr38); | |
953 | vga_wcrt(NULL, 0x39, cr39); | |
954 | ||
955 | strcpy(info->fix.id, s3_names [par->chip]); | |
956 | info->fix.mmio_start = 0; | |
957 | info->fix.mmio_len = 0; | |
958 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
959 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
960 | info->fix.ypanstep = 0; | |
961 | info->fix.accel = FB_ACCEL_NONE; | |
962 | info->pseudo_palette = (void*) (par->pseudo_palette); | |
963 | ||
964 | /* Prepare startup mode */ | |
a8140543 | 965 | rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8); |
a268422d OZ |
966 | if (! ((rc == 1) || (rc == 2))) { |
967 | rc = -EINVAL; | |
20e061fb | 968 | dev_err(info->dev, "mode %s not found\n", mode_option); |
a268422d OZ |
969 | goto err_find_mode; |
970 | } | |
971 | ||
972 | rc = fb_alloc_cmap(&info->cmap, 256, 0); | |
973 | if (rc < 0) { | |
20e061fb | 974 | dev_err(info->dev, "cannot allocate colormap\n"); |
a268422d OZ |
975 | goto err_alloc_cmap; |
976 | } | |
977 | ||
978 | rc = register_framebuffer(info); | |
979 | if (rc < 0) { | |
20e061fb | 980 | dev_err(info->dev, "cannot register framebuffer\n"); |
a268422d OZ |
981 | goto err_reg_fb; |
982 | } | |
983 | ||
984 | printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id, | |
985 | pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); | |
986 | ||
987 | if (par->chip == CHIP_UNKNOWN) | |
988 | printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", | |
989 | info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e), | |
990 | vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30)); | |
991 | ||
992 | /* Record a reference to the driver data */ | |
993 | pci_set_drvdata(dev, info); | |
994 | ||
995 | #ifdef CONFIG_MTRR | |
996 | if (mtrr) { | |
997 | par->mtrr_reg = -1; | |
998 | par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1); | |
999 | } | |
1000 | #endif | |
1001 | ||
1002 | return 0; | |
1003 | ||
1004 | /* Error handling */ | |
1005 | err_reg_fb: | |
1006 | fb_dealloc_cmap(&info->cmap); | |
1007 | err_alloc_cmap: | |
1008 | err_find_mode: | |
1009 | pci_iounmap(dev, info->screen_base); | |
1010 | err_iomap: | |
1011 | pci_release_regions(dev); | |
1012 | err_request_regions: | |
1013 | /* pci_disable_device(dev); */ | |
1014 | err_enable_device: | |
1015 | framebuffer_release(info); | |
1016 | return rc; | |
1017 | } | |
1018 | ||
1019 | ||
1020 | /* PCI remove */ | |
1021 | ||
1022 | static void __devexit s3_pci_remove(struct pci_dev *dev) | |
1023 | { | |
1024 | struct fb_info *info = pci_get_drvdata(dev); | |
a268422d OZ |
1025 | |
1026 | if (info) { | |
1027 | ||
1028 | #ifdef CONFIG_MTRR | |
47ebea83 AB |
1029 | struct s3fb_info *par = info->par; |
1030 | ||
a268422d OZ |
1031 | if (par->mtrr_reg >= 0) { |
1032 | mtrr_del(par->mtrr_reg, 0, 0); | |
1033 | par->mtrr_reg = -1; | |
1034 | } | |
1035 | #endif | |
1036 | ||
1037 | unregister_framebuffer(info); | |
1038 | fb_dealloc_cmap(&info->cmap); | |
1039 | ||
1040 | pci_iounmap(dev, info->screen_base); | |
1041 | pci_release_regions(dev); | |
1042 | /* pci_disable_device(dev); */ | |
1043 | ||
1044 | pci_set_drvdata(dev, NULL); | |
1045 | framebuffer_release(info); | |
1046 | } | |
1047 | } | |
1048 | ||
1049 | /* PCI suspend */ | |
1050 | ||
1051 | static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state) | |
1052 | { | |
1053 | struct fb_info *info = pci_get_drvdata(dev); | |
1054 | struct s3fb_info *par = info->par; | |
1055 | ||
20e061fb | 1056 | dev_info(info->dev, "suspend\n"); |
a268422d OZ |
1057 | |
1058 | acquire_console_sem(); | |
1059 | mutex_lock(&(par->open_lock)); | |
1060 | ||
1061 | if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) { | |
1062 | mutex_unlock(&(par->open_lock)); | |
1063 | release_console_sem(); | |
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | fb_set_suspend(info, 1); | |
1068 | ||
1069 | pci_save_state(dev); | |
1070 | pci_disable_device(dev); | |
1071 | pci_set_power_state(dev, pci_choose_state(dev, state)); | |
1072 | ||
1073 | mutex_unlock(&(par->open_lock)); | |
1074 | release_console_sem(); | |
1075 | ||
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | ||
1080 | /* PCI resume */ | |
1081 | ||
1082 | static int s3_pci_resume(struct pci_dev* dev) | |
1083 | { | |
1084 | struct fb_info *info = pci_get_drvdata(dev); | |
1085 | struct s3fb_info *par = info->par; | |
6314db41 | 1086 | int err; |
a268422d | 1087 | |
20e061fb | 1088 | dev_info(info->dev, "resume\n"); |
a268422d OZ |
1089 | |
1090 | acquire_console_sem(); | |
1091 | mutex_lock(&(par->open_lock)); | |
1092 | ||
1093 | if (par->ref_count == 0) { | |
1094 | mutex_unlock(&(par->open_lock)); | |
1095 | release_console_sem(); | |
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | pci_set_power_state(dev, PCI_D0); | |
1100 | pci_restore_state(dev); | |
6314db41 RD |
1101 | err = pci_enable_device(dev); |
1102 | if (err) { | |
1103 | mutex_unlock(&(par->open_lock)); | |
1104 | release_console_sem(); | |
20e061fb | 1105 | dev_err(info->dev, "error %d enabling device for resume\n", err); |
6314db41 RD |
1106 | return err; |
1107 | } | |
a268422d OZ |
1108 | pci_set_master(dev); |
1109 | ||
1110 | s3fb_set_par(info); | |
1111 | fb_set_suspend(info, 0); | |
1112 | ||
1113 | mutex_unlock(&(par->open_lock)); | |
1114 | release_console_sem(); | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | ||
1120 | /* List of boards that we are trying to support */ | |
1121 | ||
1122 | static struct pci_device_id s3_devices[] __devinitdata = { | |
1123 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO}, | |
1124 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO}, | |
1125 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP}, | |
1126 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP}, | |
1127 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX}, | |
1128 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX}, | |
1129 | ||
1130 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE}, | |
1131 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX}, | |
1132 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX}, | |
1133 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2}, | |
1134 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P}, | |
1135 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P}, | |
1136 | ||
1137 | {0, 0, 0, 0, 0, 0, 0} | |
1138 | }; | |
1139 | ||
1140 | ||
1141 | MODULE_DEVICE_TABLE(pci, s3_devices); | |
1142 | ||
1143 | static struct pci_driver s3fb_pci_driver = { | |
1144 | .name = "s3fb", | |
1145 | .id_table = s3_devices, | |
1146 | .probe = s3_pci_probe, | |
1147 | .remove = __devexit_p(s3_pci_remove), | |
1148 | .suspend = s3_pci_suspend, | |
1149 | .resume = s3_pci_resume, | |
1150 | }; | |
1151 | ||
1152 | /* Parse user speficied options */ | |
1153 | ||
1154 | #ifndef MODULE | |
1155 | static int __init s3fb_setup(char *options) | |
1156 | { | |
1157 | char *opt; | |
1158 | ||
1159 | if (!options || !*options) | |
1160 | return 0; | |
1161 | ||
1162 | while ((opt = strsep(&options, ",")) != NULL) { | |
1163 | ||
1164 | if (!*opt) | |
1165 | continue; | |
1166 | #ifdef CONFIG_MTRR | |
62fa4dc7 | 1167 | else if (!strncmp(opt, "mtrr:", 5)) |
a268422d OZ |
1168 | mtrr = simple_strtoul(opt + 5, NULL, 0); |
1169 | #endif | |
62fa4dc7 OZ |
1170 | else if (!strncmp(opt, "fasttext:", 9)) |
1171 | fasttext = simple_strtoul(opt + 9, NULL, 0); | |
a268422d | 1172 | else |
a8140543 | 1173 | mode_option = opt; |
a268422d OZ |
1174 | } |
1175 | ||
1176 | return 0; | |
1177 | } | |
1178 | #endif | |
1179 | ||
1180 | /* Cleanup */ | |
1181 | ||
1182 | static void __exit s3fb_cleanup(void) | |
1183 | { | |
1184 | pr_debug("s3fb: cleaning up\n"); | |
1185 | pci_unregister_driver(&s3fb_pci_driver); | |
1186 | } | |
1187 | ||
1188 | /* Driver Initialisation */ | |
1189 | ||
1190 | static int __init s3fb_init(void) | |
1191 | { | |
1192 | ||
1193 | #ifndef MODULE | |
1194 | char *option = NULL; | |
1195 | ||
1196 | if (fb_get_options("s3fb", &option)) | |
1197 | return -ENODEV; | |
1198 | s3fb_setup(option); | |
1199 | #endif | |
1200 | ||
1201 | pr_debug("s3fb: initializing\n"); | |
1202 | return pci_register_driver(&s3fb_pci_driver); | |
1203 | } | |
1204 | ||
1205 | /* ------------------------------------------------------------------------- */ | |
1206 | ||
1207 | /* Modularization */ | |
1208 | ||
1209 | module_init(s3fb_init); | |
1210 | module_exit(s3fb_cleanup); |