Commit | Line | Data |
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1da177e4 LT |
1 | /* drivers/video/s1d13xxxfb.c |
2 | * | |
3 | * (c) 2004 Simtec Electronics | |
4 | * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org> | |
5 | * | |
6 | * Driver for Epson S1D13xxx series framebuffer chips | |
7 | * | |
8 | * Adapted from | |
9 | * linux/drivers/video/skeletonfb.c | |
10 | * linux/drivers/video/epson1355fb.c | |
11 | * linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson) | |
12 | * | |
13 | * Note, currently only tested on S1D13806 with 16bit CRT. | |
14 | * As such, this driver might still contain some hardcoded bits relating to | |
15 | * S1D13806. | |
16 | * Making it work on other S1D13XXX chips should merely be a matter of adding | |
17 | * a few switch()s, some missing glue here and there maybe, and split header | |
18 | * files. | |
19 | * | |
20 | * TODO: - handle dual screen display (CRT and LCD at the same time). | |
21 | * - check_var(), mode change, etc. | |
22 | * - PM untested. | |
23 | * - Accelerated interfaces. | |
24 | * - Probably not SMP safe :) | |
25 | * | |
26 | * This file is subject to the terms and conditions of the GNU General Public | |
27 | * License. See the file COPYING in the main directory of this archive for | |
28 | * more details. | |
29 | */ | |
30 | ||
1da177e4 | 31 | #include <linux/module.h> |
d052d1be | 32 | #include <linux/platform_device.h> |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | ||
35 | #include <linux/types.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/mm.h> | |
38 | #include <linux/mman.h> | |
39 | #include <linux/fb.h> | |
40 | ||
41 | #include <asm/io.h> | |
42 | ||
43 | #include <video/s1d13xxxfb.h> | |
44 | ||
45 | #define PFX "s1d13xxxfb: " | |
46 | ||
47 | #if 0 | |
48 | #define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0) | |
49 | #else | |
50 | #define dbg(fmt, args...) do { } while (0) | |
51 | #endif | |
52 | ||
53 | /* | |
54 | * Here we define the default struct fb_fix_screeninfo | |
55 | */ | |
56 | static struct fb_fix_screeninfo __devinitdata s1d13xxxfb_fix = { | |
57 | .id = S1D_FBID, | |
58 | .type = FB_TYPE_PACKED_PIXELS, | |
59 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
60 | .xpanstep = 0, | |
61 | .ypanstep = 1, | |
62 | .ywrapstep = 0, | |
63 | .accel = FB_ACCEL_NONE, | |
64 | }; | |
65 | ||
66 | static inline u8 | |
67 | s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno) | |
68 | { | |
316240f6 HT |
69 | #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3) |
70 | regno=((regno & 1) ? (regno & ~1L) : (regno + 1)); | |
71 | #endif | |
1da177e4 LT |
72 | return readb(par->regs + regno); |
73 | } | |
74 | ||
75 | static inline void | |
76 | s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value) | |
77 | { | |
316240f6 HT |
78 | #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3) |
79 | regno=((regno & 1) ? (regno & ~1L) : (regno + 1)); | |
80 | #endif | |
1da177e4 LT |
81 | writeb(value, par->regs + regno); |
82 | } | |
83 | ||
84 | static inline void | |
85 | s1d13xxxfb_runinit(struct s1d13xxxfb_par *par, | |
86 | const struct s1d13xxxfb_regval *initregs, | |
87 | const unsigned int size) | |
88 | { | |
89 | int i; | |
90 | ||
91 | for (i = 0; i < size; i++) { | |
92 | if ((initregs[i].addr == S1DREG_DELAYOFF) || | |
93 | (initregs[i].addr == S1DREG_DELAYON)) | |
94 | mdelay((int)initregs[i].value); | |
95 | else { | |
96 | s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value); | |
97 | } | |
98 | } | |
99 | ||
100 | /* make sure the hardware can cope with us */ | |
101 | mdelay(1); | |
102 | } | |
103 | ||
104 | static inline void | |
105 | lcd_enable(struct s1d13xxxfb_par *par, int enable) | |
106 | { | |
107 | u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE); | |
108 | ||
109 | if (enable) | |
110 | mode |= 0x01; | |
111 | else | |
112 | mode &= ~0x01; | |
113 | ||
114 | s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode); | |
115 | } | |
116 | ||
117 | static inline void | |
118 | crt_enable(struct s1d13xxxfb_par *par, int enable) | |
119 | { | |
120 | u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE); | |
121 | ||
122 | if (enable) | |
123 | mode |= 0x02; | |
124 | else | |
125 | mode &= ~0x02; | |
126 | ||
127 | s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode); | |
128 | } | |
129 | ||
130 | /* framebuffer control routines */ | |
131 | ||
132 | static inline void | |
133 | s1d13xxxfb_setup_pseudocolour(struct fb_info *info) | |
134 | { | |
135 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
136 | ||
137 | info->var.red.length = 4; | |
138 | info->var.green.length = 4; | |
139 | info->var.blue.length = 4; | |
140 | } | |
141 | ||
142 | static inline void | |
143 | s1d13xxxfb_setup_truecolour(struct fb_info *info) | |
144 | { | |
145 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
146 | info->var.bits_per_pixel = 16; | |
147 | ||
148 | info->var.red.length = 5; | |
149 | info->var.red.offset = 11; | |
150 | ||
151 | info->var.green.length = 6; | |
152 | info->var.green.offset = 5; | |
153 | ||
154 | info->var.blue.length = 5; | |
155 | info->var.blue.offset = 0; | |
156 | } | |
157 | ||
158 | /** | |
159 | * s1d13xxxfb_set_par - Alters the hardware state. | |
160 | * @info: frame buffer structure | |
161 | * | |
162 | * Using the fb_var_screeninfo in fb_info we set the depth of the | |
163 | * framebuffer. This function alters the par AND the | |
164 | * fb_fix_screeninfo stored in fb_info. It doesn't not alter var in | |
165 | * fb_info since we are using that data. This means we depend on the | |
166 | * data in var inside fb_info to be supported by the hardware. | |
167 | * xxxfb_check_var is always called before xxxfb_set_par to ensure this. | |
168 | * | |
169 | * XXX TODO: write proper s1d13xxxfb_check_var(), without which that | |
170 | * function is quite useless. | |
171 | */ | |
172 | static int | |
173 | s1d13xxxfb_set_par(struct fb_info *info) | |
174 | { | |
175 | struct s1d13xxxfb_par *s1dfb = info->par; | |
176 | unsigned int val; | |
177 | ||
178 | dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel); | |
179 | ||
180 | if ((s1dfb->display & 0x01)) /* LCD */ | |
181 | val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE); /* read colour control */ | |
182 | else /* CRT */ | |
183 | val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE); /* read colour control */ | |
184 | ||
185 | val &= ~0x07; | |
186 | ||
187 | switch (info->var.bits_per_pixel) { | |
188 | case 4: | |
189 | dbg("pseudo colour 4\n"); | |
190 | s1d13xxxfb_setup_pseudocolour(info); | |
191 | val |= 2; | |
192 | break; | |
193 | case 8: | |
194 | dbg("pseudo colour 8\n"); | |
195 | s1d13xxxfb_setup_pseudocolour(info); | |
196 | val |= 3; | |
197 | break; | |
198 | case 16: | |
199 | dbg("true colour\n"); | |
200 | s1d13xxxfb_setup_truecolour(info); | |
201 | val |= 5; | |
202 | break; | |
203 | ||
204 | default: | |
205 | dbg("bpp not supported!\n"); | |
206 | return -EINVAL; | |
207 | } | |
208 | ||
209 | dbg("writing %02x to display mode register\n", val); | |
210 | ||
211 | if ((s1dfb->display & 0x01)) /* LCD */ | |
212 | s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val); | |
213 | else /* CRT */ | |
214 | s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val); | |
215 | ||
216 | info->fix.line_length = info->var.xres * info->var.bits_per_pixel; | |
217 | info->fix.line_length /= 8; | |
218 | ||
219 | dbg("setting line_length to %d\n", info->fix.line_length); | |
220 | ||
221 | dbg("done setup\n"); | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | /** | |
227 | * s1d13xxxfb_setcolreg - sets a color register. | |
228 | * @regno: Which register in the CLUT we are programming | |
229 | * @red: The red value which can be up to 16 bits wide | |
230 | * @green: The green value which can be up to 16 bits wide | |
231 | * @blue: The blue value which can be up to 16 bits wide. | |
232 | * @transp: If supported the alpha value which can be up to 16 bits wide. | |
233 | * @info: frame buffer info structure | |
234 | * | |
235 | * Returns negative errno on error, or zero on success. | |
236 | */ | |
237 | static int | |
238 | s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
239 | u_int transp, struct fb_info *info) | |
240 | { | |
241 | struct s1d13xxxfb_par *s1dfb = info->par; | |
242 | unsigned int pseudo_val; | |
243 | ||
244 | if (regno >= S1D_PALETTE_SIZE) | |
245 | return -EINVAL; | |
246 | ||
247 | dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n", | |
248 | regno, red, green, blue, transp); | |
249 | ||
250 | if (info->var.grayscale) | |
251 | red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16; | |
252 | ||
253 | switch (info->fix.visual) { | |
254 | case FB_VISUAL_TRUECOLOR: | |
255 | if (regno >= 16) | |
256 | return -EINVAL; | |
257 | ||
258 | /* deal with creating pseudo-palette entries */ | |
259 | ||
260 | pseudo_val = (red >> 11) << info->var.red.offset; | |
261 | pseudo_val |= (green >> 10) << info->var.green.offset; | |
262 | pseudo_val |= (blue >> 11) << info->var.blue.offset; | |
263 | ||
264 | dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n", | |
265 | regno, pseudo_val); | |
266 | ||
316240f6 HT |
267 | #if defined(CONFIG_PLAT_MAPPI) |
268 | ((u32 *)info->pseudo_palette)[regno] = cpu_to_le16(pseudo_val); | |
269 | #else | |
1da177e4 | 270 | ((u32 *)info->pseudo_palette)[regno] = pseudo_val; |
316240f6 | 271 | #endif |
1da177e4 LT |
272 | |
273 | break; | |
274 | case FB_VISUAL_PSEUDOCOLOR: | |
275 | s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno); | |
276 | s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red); | |
277 | s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green); | |
278 | s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue); | |
279 | ||
280 | break; | |
281 | default: | |
282 | return -ENOSYS; | |
283 | } | |
284 | ||
285 | dbg("s1d13xxxfb_setcolreg: done\n"); | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
290 | /** | |
291 | * s1d13xxxfb_blank - blanks the display. | |
292 | * @blank_mode: the blank mode we want. | |
293 | * @info: frame buffer structure that represents a single frame buffer | |
294 | * | |
295 | * Blank the screen if blank_mode != 0, else unblank. Return 0 if | |
296 | * blanking succeeded, != 0 if un-/blanking failed due to e.g. a | |
297 | * video mode which doesn't support it. Implements VESA suspend | |
298 | * and powerdown modes on hardware that supports disabling hsync/vsync: | |
299 | * blank_mode == 2: suspend vsync | |
300 | * blank_mode == 3: suspend hsync | |
301 | * blank_mode == 4: powerdown | |
302 | * | |
303 | * Returns negative errno on error, or zero on success. | |
304 | */ | |
305 | static int | |
306 | s1d13xxxfb_blank(int blank_mode, struct fb_info *info) | |
307 | { | |
308 | struct s1d13xxxfb_par *par = info->par; | |
309 | ||
310 | dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info); | |
311 | ||
312 | switch (blank_mode) { | |
313 | case FB_BLANK_UNBLANK: | |
314 | case FB_BLANK_NORMAL: | |
315 | if ((par->display & 0x01) != 0) | |
316 | lcd_enable(par, 1); | |
317 | if ((par->display & 0x02) != 0) | |
318 | crt_enable(par, 1); | |
319 | break; | |
320 | case FB_BLANK_VSYNC_SUSPEND: | |
321 | case FB_BLANK_HSYNC_SUSPEND: | |
322 | break; | |
323 | case FB_BLANK_POWERDOWN: | |
324 | lcd_enable(par, 0); | |
325 | crt_enable(par, 0); | |
326 | break; | |
327 | default: | |
328 | return -EINVAL; | |
329 | } | |
330 | ||
331 | /* let fbcon do a soft blank for us */ | |
332 | return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0); | |
333 | } | |
334 | ||
335 | /** | |
336 | * s1d13xxxfb_pan_display - Pans the display. | |
337 | * @var: frame buffer variable screen structure | |
338 | * @info: frame buffer structure that represents a single frame buffer | |
339 | * | |
340 | * Pan (or wrap, depending on the `vmode' field) the display using the | |
341 | * `yoffset' field of the `var' structure (`xoffset' not yet supported). | |
342 | * If the values don't fit, return -EINVAL. | |
343 | * | |
344 | * Returns negative errno on error, or zero on success. | |
345 | */ | |
346 | static int | |
347 | s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | |
348 | { | |
349 | struct s1d13xxxfb_par *par = info->par; | |
350 | u32 start; | |
351 | ||
352 | if (var->xoffset != 0) /* not yet ... */ | |
353 | return -EINVAL; | |
354 | ||
355 | if (var->yoffset + info->var.yres > info->var.yres_virtual) | |
356 | return -EINVAL; | |
357 | ||
358 | start = (info->fix.line_length >> 1) * var->yoffset; | |
359 | ||
360 | if ((par->display & 0x01)) { | |
361 | /* LCD */ | |
362 | s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff)); | |
363 | s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff)); | |
364 | s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f)); | |
365 | } else { | |
366 | /* CRT */ | |
367 | s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START0, (start & 0xff)); | |
368 | s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START1, ((start >> 8) & 0xff)); | |
369 | s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START2, ((start >> 16) & 0x0f)); | |
370 | } | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | ||
376 | /* framebuffer information structures */ | |
377 | ||
378 | static struct fb_ops s1d13xxxfb_fbops = { | |
379 | .owner = THIS_MODULE, | |
380 | .fb_set_par = s1d13xxxfb_set_par, | |
381 | .fb_setcolreg = s1d13xxxfb_setcolreg, | |
382 | .fb_blank = s1d13xxxfb_blank, | |
383 | ||
384 | .fb_pan_display = s1d13xxxfb_pan_display, | |
385 | ||
386 | /* to be replaced by any acceleration we can */ | |
387 | .fb_fillrect = cfb_fillrect, | |
388 | .fb_copyarea = cfb_copyarea, | |
389 | .fb_imageblit = cfb_imageblit, | |
1da177e4 LT |
390 | }; |
391 | ||
392 | static int s1d13xxxfb_width_tab[2][4] __devinitdata = { | |
393 | {4, 8, 16, -1}, | |
394 | {9, 12, 18, -1}, | |
395 | }; | |
396 | ||
397 | /** | |
398 | * s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to | |
399 | * hardware setup. | |
400 | * @info: frame buffer structure | |
401 | * | |
402 | * We setup the framebuffer structures according to the current | |
403 | * hardware setup. On some machines, the BIOS will have filled | |
404 | * the chip registers with such info, on others, these values will | |
405 | * have been written in some init procedure. In any case, the | |
406 | * software values needs to match the hardware ones. This is what | |
407 | * this function ensures. | |
408 | * | |
409 | * Note: some of the hardcoded values here might need some love to | |
410 | * work on various chips, and might need to no longer be hardcoded. | |
411 | */ | |
412 | static void __devinit | |
413 | s1d13xxxfb_fetch_hw_state(struct fb_info *info) | |
414 | { | |
415 | struct fb_var_screeninfo *var = &info->var; | |
416 | struct fb_fix_screeninfo *fix = &info->fix; | |
417 | struct s1d13xxxfb_par *par = info->par; | |
418 | u8 panel, display; | |
419 | u16 offset; | |
420 | u32 xres, yres; | |
421 | u32 xres_virtual, yres_virtual; | |
422 | int bpp, lcd_bpp; | |
423 | int is_color, is_dual, is_tft; | |
424 | int lcd_enabled, crt_enabled; | |
425 | ||
426 | fix->type = FB_TYPE_PACKED_PIXELS; | |
427 | ||
428 | /* general info */ | |
429 | par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE); | |
430 | crt_enabled = (par->display & 0x02) != 0; | |
431 | lcd_enabled = (par->display & 0x01) != 0; | |
432 | ||
433 | if (lcd_enabled && crt_enabled) | |
434 | printk(KERN_WARNING PFX "Warning: LCD and CRT detected, using LCD\n"); | |
435 | ||
436 | if (lcd_enabled) | |
437 | display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE); | |
438 | else /* CRT */ | |
439 | display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE); | |
440 | ||
441 | bpp = display & 0x07; | |
442 | ||
443 | switch (bpp) { | |
444 | case 2: /* 4 bpp */ | |
445 | case 3: /* 8 bpp */ | |
446 | var->bits_per_pixel = 8; | |
447 | var->red.offset = var->green.offset = var->blue.offset = 0; | |
448 | var->red.length = var->green.length = var->blue.length = 8; | |
449 | break; | |
450 | case 5: /* 16 bpp */ | |
451 | s1d13xxxfb_setup_truecolour(info); | |
452 | break; | |
453 | default: | |
454 | dbg("bpp: %i\n", bpp); | |
455 | } | |
456 | fb_alloc_cmap(&info->cmap, 256, 0); | |
457 | ||
458 | /* LCD info */ | |
459 | panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE); | |
460 | is_color = (panel & 0x04) != 0; | |
461 | is_dual = (panel & 0x02) != 0; | |
462 | is_tft = (panel & 0x01) != 0; | |
463 | lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3]; | |
464 | ||
465 | if (lcd_enabled) { | |
466 | xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8; | |
467 | yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) + | |
468 | ((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1); | |
469 | ||
470 | offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) + | |
471 | ((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8)); | |
472 | } else { /* crt */ | |
473 | xres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_HWIDTH) + 1) * 8; | |
474 | yres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT0) + | |
475 | ((s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT1) & 0x03) << 8) + 1); | |
476 | ||
477 | offset = (s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF0) + | |
478 | ((s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF1) & 0x7) << 8)); | |
479 | } | |
480 | xres_virtual = offset * 16 / var->bits_per_pixel; | |
481 | yres_virtual = fix->smem_len / (offset * 2); | |
482 | ||
483 | var->xres = xres; | |
484 | var->yres = yres; | |
485 | var->xres_virtual = xres_virtual; | |
486 | var->yres_virtual = yres_virtual; | |
487 | var->xoffset = var->yoffset = 0; | |
488 | ||
489 | fix->line_length = offset * 2; | |
490 | ||
491 | var->grayscale = !is_color; | |
492 | ||
493 | var->activate = FB_ACTIVATE_NOW; | |
494 | ||
495 | dbg(PFX "bpp=%d, lcd_bpp=%d, " | |
496 | "crt_enabled=%d, lcd_enabled=%d\n", | |
497 | var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled); | |
498 | dbg(PFX "xres=%d, yres=%d, vxres=%d, vyres=%d " | |
499 | "is_color=%d, is_dual=%d, is_tft=%d\n", | |
500 | xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft); | |
501 | } | |
502 | ||
503 | ||
27f931da | 504 | static int |
3ae5eaec | 505 | s1d13xxxfb_remove(struct platform_device *pdev) |
1da177e4 | 506 | { |
3ae5eaec | 507 | struct fb_info *info = platform_get_drvdata(pdev); |
1da177e4 LT |
508 | struct s1d13xxxfb_par *par = NULL; |
509 | ||
510 | if (info) { | |
511 | par = info->par; | |
512 | if (par && par->regs) { | |
513 | /* disable output & enable powersave */ | |
514 | s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00); | |
515 | s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11); | |
516 | iounmap(par->regs); | |
517 | } | |
518 | ||
519 | fb_dealloc_cmap(&info->cmap); | |
520 | ||
521 | if (info->screen_base) | |
522 | iounmap(info->screen_base); | |
523 | ||
524 | framebuffer_release(info); | |
525 | } | |
526 | ||
527 | release_mem_region(pdev->resource[0].start, | |
528 | pdev->resource[0].end - pdev->resource[0].start +1); | |
529 | release_mem_region(pdev->resource[1].start, | |
530 | pdev->resource[1].end - pdev->resource[1].start +1); | |
531 | return 0; | |
532 | } | |
533 | ||
534 | static int __devinit | |
3ae5eaec | 535 | s1d13xxxfb_probe(struct platform_device *pdev) |
1da177e4 | 536 | { |
1da177e4 LT |
537 | struct s1d13xxxfb_par *default_par; |
538 | struct fb_info *info; | |
539 | struct s1d13xxxfb_pdata *pdata = NULL; | |
540 | int ret = 0; | |
541 | u8 revision; | |
542 | ||
28822f22 | 543 | dbg("probe called: device is %p\n", pdev); |
1da177e4 LT |
544 | |
545 | printk(KERN_INFO "Epson S1D13XXX FB Driver\n"); | |
546 | ||
547 | /* enable platform-dependent hardware glue, if any */ | |
3ae5eaec RK |
548 | if (pdev->dev.platform_data) |
549 | pdata = pdev->dev.platform_data; | |
1da177e4 LT |
550 | |
551 | if (pdata && pdata->platform_init_video) | |
552 | pdata->platform_init_video(); | |
553 | ||
554 | ||
555 | if (pdev->num_resources != 2) { | |
556 | dev_err(&pdev->dev, "invalid num_resources: %i\n", | |
557 | pdev->num_resources); | |
558 | ret = -ENODEV; | |
559 | goto bail; | |
560 | } | |
561 | ||
562 | /* resource[0] is VRAM, resource[1] is registers */ | |
563 | if (pdev->resource[0].flags != IORESOURCE_MEM | |
564 | || pdev->resource[1].flags != IORESOURCE_MEM) { | |
565 | dev_err(&pdev->dev, "invalid resource type\n"); | |
566 | ret = -ENODEV; | |
567 | goto bail; | |
568 | } | |
569 | ||
570 | if (!request_mem_region(pdev->resource[0].start, | |
571 | pdev->resource[0].end - pdev->resource[0].start +1, "s1d13xxxfb mem")) { | |
3ae5eaec | 572 | dev_dbg(&pdev->dev, "request_mem_region failed\n"); |
1da177e4 LT |
573 | ret = -EBUSY; |
574 | goto bail; | |
575 | } | |
576 | ||
577 | if (!request_mem_region(pdev->resource[1].start, | |
578 | pdev->resource[1].end - pdev->resource[1].start +1, "s1d13xxxfb regs")) { | |
3ae5eaec | 579 | dev_dbg(&pdev->dev, "request_mem_region failed\n"); |
1da177e4 LT |
580 | ret = -EBUSY; |
581 | goto bail; | |
582 | } | |
583 | ||
584 | info = framebuffer_alloc(sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev); | |
585 | if (!info) { | |
586 | ret = -ENOMEM; | |
587 | goto bail; | |
588 | } | |
589 | ||
98365f5e | 590 | platform_set_drvdata(pdev, info); |
1da177e4 LT |
591 | default_par = info->par; |
592 | default_par->regs = ioremap_nocache(pdev->resource[1].start, | |
593 | pdev->resource[1].end - pdev->resource[1].start +1); | |
594 | if (!default_par->regs) { | |
595 | printk(KERN_ERR PFX "unable to map registers\n"); | |
596 | ret = -ENOMEM; | |
597 | goto bail; | |
598 | } | |
599 | info->pseudo_palette = default_par->pseudo_palette; | |
600 | ||
601 | info->screen_base = ioremap_nocache(pdev->resource[0].start, | |
602 | pdev->resource[0].end - pdev->resource[0].start +1); | |
603 | ||
604 | if (!info->screen_base) { | |
605 | printk(KERN_ERR PFX "unable to map framebuffer\n"); | |
606 | ret = -ENOMEM; | |
607 | goto bail; | |
608 | } | |
609 | ||
610 | revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE); | |
611 | if ((revision >> 2) != S1D_CHIP_REV) { | |
612 | printk(KERN_INFO PFX "chip not found: %i\n", (revision >> 2)); | |
613 | ret = -ENODEV; | |
614 | goto bail; | |
615 | } | |
616 | ||
617 | info->fix = s1d13xxxfb_fix; | |
618 | info->fix.mmio_start = pdev->resource[1].start; | |
619 | info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start +1; | |
620 | info->fix.smem_start = pdev->resource[0].start; | |
621 | info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start +1; | |
622 | ||
623 | printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n", | |
624 | default_par->regs, info->fix.smem_len / 1024, info->screen_base); | |
625 | ||
626 | info->par = default_par; | |
627 | info->fbops = &s1d13xxxfb_fbops; | |
628 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; | |
629 | ||
630 | /* perform "manual" chip initialization, if needed */ | |
631 | if (pdata && pdata->initregs) | |
632 | s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize); | |
633 | ||
634 | s1d13xxxfb_fetch_hw_state(info); | |
635 | ||
636 | if (register_framebuffer(info) < 0) { | |
637 | ret = -EINVAL; | |
638 | goto bail; | |
639 | } | |
640 | ||
1da177e4 LT |
641 | printk(KERN_INFO "fb%d: %s frame buffer device\n", |
642 | info->node, info->fix.id); | |
643 | ||
644 | return 0; | |
645 | ||
646 | bail: | |
3ae5eaec | 647 | s1d13xxxfb_remove(pdev); |
1da177e4 LT |
648 | return ret; |
649 | ||
650 | } | |
651 | ||
652 | #ifdef CONFIG_PM | |
3ae5eaec | 653 | static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 654 | { |
3ae5eaec | 655 | struct fb_info *info = platform_get_drvdata(dev); |
1da177e4 LT |
656 | struct s1d13xxxfb_par *s1dfb = info->par; |
657 | struct s1d13xxxfb_pdata *pdata = NULL; | |
658 | ||
659 | /* disable display */ | |
660 | lcd_enable(s1dfb, 0); | |
661 | crt_enable(s1dfb, 0); | |
662 | ||
3ae5eaec RK |
663 | if (dev->dev.platform_data) |
664 | pdata = dev->dev.platform_data; | |
1da177e4 LT |
665 | |
666 | #if 0 | |
667 | if (!s1dfb->disp_save) | |
668 | s1dfb->disp_save = kmalloc(info->fix.smem_len, GFP_KERNEL); | |
669 | ||
670 | if (!s1dfb->disp_save) { | |
671 | printk(KERN_ERR PFX "no memory to save screen"); | |
672 | return -ENOMEM; | |
673 | } | |
674 | ||
675 | memcpy_fromio(s1dfb->disp_save, info->screen_base, info->fix.smem_len); | |
676 | #else | |
677 | s1dfb->disp_save = NULL; | |
678 | #endif | |
679 | ||
680 | if (!s1dfb->regs_save) | |
681 | s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL); | |
682 | ||
683 | if (!s1dfb->regs_save) { | |
684 | printk(KERN_ERR PFX "no memory to save registers"); | |
685 | return -ENOMEM; | |
686 | } | |
687 | ||
688 | /* backup all registers */ | |
689 | memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len); | |
690 | ||
691 | /* now activate power save mode */ | |
692 | s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11); | |
693 | ||
694 | if (pdata && pdata->platform_suspend_video) | |
695 | return pdata->platform_suspend_video(); | |
696 | else | |
697 | return 0; | |
698 | } | |
699 | ||
3ae5eaec | 700 | static int s1d13xxxfb_resume(struct platform_device *dev) |
1da177e4 | 701 | { |
3ae5eaec | 702 | struct fb_info *info = platform_get_drvdata(dev); |
1da177e4 LT |
703 | struct s1d13xxxfb_par *s1dfb = info->par; |
704 | struct s1d13xxxfb_pdata *pdata = NULL; | |
705 | ||
1da177e4 LT |
706 | /* awaken the chip */ |
707 | s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10); | |
708 | ||
709 | /* do not let go until SDRAM "wakes up" */ | |
710 | while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01)) | |
711 | udelay(10); | |
712 | ||
3ae5eaec RK |
713 | if (dev->dev.platform_data) |
714 | pdata = dev->dev.platform_data; | |
1da177e4 LT |
715 | |
716 | if (s1dfb->regs_save) { | |
717 | /* will write RO regs, *should* get away with it :) */ | |
718 | memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len); | |
719 | kfree(s1dfb->regs_save); | |
720 | } | |
721 | ||
722 | if (s1dfb->disp_save) { | |
723 | memcpy_toio(info->screen_base, s1dfb->disp_save, | |
724 | info->fix.smem_len); | |
725 | kfree(s1dfb->disp_save); /* XXX kmalloc()'d when? */ | |
726 | } | |
727 | ||
728 | if ((s1dfb->display & 0x01) != 0) | |
729 | lcd_enable(s1dfb, 1); | |
730 | if ((s1dfb->display & 0x02) != 0) | |
731 | crt_enable(s1dfb, 1); | |
732 | ||
733 | if (pdata && pdata->platform_resume_video) | |
734 | return pdata->platform_resume_video(); | |
735 | else | |
736 | return 0; | |
737 | } | |
738 | #endif /* CONFIG_PM */ | |
739 | ||
3ae5eaec | 740 | static struct platform_driver s1d13xxxfb_driver = { |
1da177e4 LT |
741 | .probe = s1d13xxxfb_probe, |
742 | .remove = s1d13xxxfb_remove, | |
743 | #ifdef CONFIG_PM | |
744 | .suspend = s1d13xxxfb_suspend, | |
3ae5eaec | 745 | .resume = s1d13xxxfb_resume, |
1da177e4 | 746 | #endif |
3ae5eaec RK |
747 | .driver = { |
748 | .name = S1D_DEVICENAME, | |
749 | }, | |
1da177e4 LT |
750 | }; |
751 | ||
752 | ||
753 | static int __init | |
754 | s1d13xxxfb_init(void) | |
755 | { | |
28822f22 SB |
756 | |
757 | #ifndef MODULE | |
1da177e4 LT |
758 | if (fb_get_options("s1d13xxxfb", NULL)) |
759 | return -ENODEV; | |
28822f22 | 760 | #endif |
1da177e4 | 761 | |
3ae5eaec | 762 | return platform_driver_register(&s1d13xxxfb_driver); |
1da177e4 LT |
763 | } |
764 | ||
765 | ||
766 | static void __exit | |
767 | s1d13xxxfb_exit(void) | |
768 | { | |
3ae5eaec | 769 | platform_driver_unregister(&s1d13xxxfb_driver); |
1da177e4 LT |
770 | } |
771 | ||
772 | module_init(s1d13xxxfb_init); | |
773 | module_exit(s1d13xxxfb_exit); | |
774 | ||
775 | ||
776 | MODULE_LICENSE("GPL"); | |
777 | MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices"); | |
778 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Thibaut VARENE <varenet@parisc-linux.org>"); |