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[PATCH] briq_panel: read() and write() get __user pointers, damnit
[linux-2.6-block.git] / drivers / video / riva / fbdev.c
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1da177e4
LT		 1/*
2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 1999-2000 Jeff Garzik
7 *
8 * Contributors:
9 *
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
12 *
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
14 *
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
16 *
17 * Paul Richards: Bug fixes, updates
18 *
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
25 * for more details.
26 *
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
30 */
31
1da177e4
LT		 32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/errno.h>
35#include <linux/string.h>
36#include <linux/mm.h>
1da177e4
LT		 37#include <linux/slab.h>
38#include <linux/delay.h>
39#include <linux/fb.h>
40#include <linux/init.h>
41#include <linux/pci.h>
5474c120 42#include <linux/backlight.h>
1da177e4
LT		 43#ifdef CONFIG_MTRR
44#include <asm/mtrr.h>
45#endif
46#ifdef CONFIG_PPC_OF
47#include <asm/prom.h>
48#include <asm/pci-bridge.h>
49#endif
50#ifdef CONFIG_PMAC_BACKLIGHT
e8222502 51#include <asm/machdep.h>
1da177e4
LT		 52#include <asm/backlight.h>
53#endif
54
55#include "rivafb.h"
56#include "nvreg.h"
57
58#ifndef CONFIG_PCI /* sanity check */
59#error This driver requires PCI support.
60#endif
61
62/* version number of this driver */
63#define RIVAFB_VERSION "0.9.5b"
64
65/* ------------------------------------------------------------------------- *
66 *
67 * various helpful macros and constants
68 *
69 * ------------------------------------------------------------------------- */
70#ifdef CONFIG_FB_RIVA_DEBUG
71#define NVTRACE printk
72#else
73#define NVTRACE if(0) printk
74#endif
75
76#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
77#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
78
79#ifdef CONFIG_FB_RIVA_DEBUG
80#define assert(expr) \
81 if(!(expr)) { \
82 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
83 #expr,__FILE__,__FUNCTION__,__LINE__); \
84 BUG(); \
85 }
86#else
87#define assert(expr)
88#endif
89
90#define PFX "rivafb: "
91
92/* macro that allows you to set overflow bits */
93#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94#define SetBit(n) (1<<(n))
95#define Set8Bits(value) ((value)&0xff)
96
97/* HW cursor parameters */
98#define MAX_CURS 32
99
100/* ------------------------------------------------------------------------- *
101 *
102 * prototypes
103 *
104 * ------------------------------------------------------------------------- */
105
106static int rivafb_blank(int blank, struct fb_info *info);
107
108/* ------------------------------------------------------------------------- *
109 *
110 * card identification
111 *
112 * ------------------------------------------------------------------------- */
113
114static struct pci_device_id rivafb_pci_tbl[] = {
115 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 // NF2/IGP version, GeForce 4 MX, NV18
156 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
158 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
160 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
162 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
164 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
166 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
168 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
170 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
180 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
182 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
184 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
186 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
188 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
190 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
192 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
194 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
196 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
198 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
200 { 0, } /* terminate list */
201};
202MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
203
204/* ------------------------------------------------------------------------- *
205 *
206 * global variables
207 *
208 * ------------------------------------------------------------------------- */
209
210/* command line data, set in rivafb_setup() */
211static int flatpanel __devinitdata = -1; /* Autodetect later */
212static int forceCRTC __devinitdata = -1;
213static int noaccel __devinitdata = 0;
214#ifdef CONFIG_MTRR
215static int nomtrr __devinitdata = 0;
216#endif
217
218static char *mode_option __devinitdata = NULL;
219static int strictmode = 0;
220
221static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
222 .type = FB_TYPE_PACKED_PIXELS,
223 .xpanstep = 1,
224 .ypanstep = 1,
225};
226
227static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
228 .xres = 640,
229 .yres = 480,
230 .xres_virtual = 640,
231 .yres_virtual = 480,
232 .bits_per_pixel = 8,
233 .red = {0, 8, 0},
234 .green = {0, 8, 0},
235 .blue = {0, 8, 0},
236 .transp = {0, 0, 0},
237 .activate = FB_ACTIVATE_NOW,
238 .height = -1,
239 .width = -1,
240 .pixclock = 39721,
241 .left_margin = 40,
242 .right_margin = 24,
243 .upper_margin = 32,
244 .lower_margin = 11,
245 .hsync_len = 96,
246 .vsync_len = 2,
247 .vmode = FB_VMODE_NONINTERLACED
248};
249
250/* from GGI */
251static const struct riva_regs reg_template = {
252 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
253 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
254 0x41, 0x01, 0x0F, 0x00, 0x00},
255 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
256 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
258 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
260 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
263 0x00, /* 0x40 */
264 },
265 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
266 0xFF},
267 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
268 0xEB /* MISC */
269};
270
271/*
272 * Backlight control
273 */
5474c120
MH		 274#ifdef CONFIG_FB_RIVA_BACKLIGHT
275/* We do not have any information about which values are allowed, thus
276 * we used safe values.
277 */
278#define MIN_LEVEL 0x158
279#define MAX_LEVEL 0x534
e01af038 280#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
1da177e4 281
5474c120
MH		 282static struct backlight_properties riva_bl_data;
283
e01af038 284/* Call with fb_info->bl_mutex held */
5474c120
MH		 285static int riva_bl_get_level_brightness(struct riva_par *par,
286 int level)
287{
288 struct fb_info *info = pci_get_drvdata(par->pdev);
289 int nlevel;
290
291 /* Get and convert the value */
e01af038 292 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
5474c120
MH		 293
294 if (nlevel < 0)
295 nlevel = 0;
296 else if (nlevel < MIN_LEVEL)
297 nlevel = MIN_LEVEL;
298 else if (nlevel > MAX_LEVEL)
299 nlevel = MAX_LEVEL;
300
301 return nlevel;
302}
303
e01af038
MH		 304/* Call with fb_info->bl_mutex held */
305static int __riva_bl_update_status(struct backlight_device *bd)
5474c120
MH		 306{
307 struct riva_par *par = class_get_devdata(&bd->class_dev);
308 U032 tmp_pcrt, tmp_pmc;
309 int level;
310
311 if (bd->props->power != FB_BLANK_UNBLANK ||
312 bd->props->fb_blank != FB_BLANK_UNBLANK)
313 level = 0;
314 else
315 level = bd->props->brightness;
316
317 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
318 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
319 if(level > 0) {
320 tmp_pcrt |= 0x1;
321 tmp_pmc |= (1 << 31); /* backlight bit */
322 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
323 }
324 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
325 par->riva.PMC[0x10F0/4] = tmp_pmc;
326
327 return 0;
328}
329
e01af038
MH		 330static int riva_bl_update_status(struct backlight_device *bd)
331{
332 struct riva_par *par = class_get_devdata(&bd->class_dev);
333 struct fb_info *info = pci_get_drvdata(par->pdev);
334 int ret;
335
336 mutex_lock(&info->bl_mutex);
337 ret = __riva_bl_update_status(bd);
338 mutex_unlock(&info->bl_mutex);
339
340 return ret;
341}
342
5474c120
MH		 343static int riva_bl_get_brightness(struct backlight_device *bd)
344{
345 return bd->props->brightness;
346}
1da177e4 347
5474c120
MH		 348static struct backlight_properties riva_bl_data = {
349 .owner = THIS_MODULE,
350 .get_brightness = riva_bl_get_brightness,
351 .update_status = riva_bl_update_status,
352 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
1da177e4 353};
5474c120 354
e01af038
MH		 355static void riva_bl_set_power(struct fb_info *info, int power)
356{
357 mutex_lock(&info->bl_mutex);
a9303638
BH		 358
359 if (info->bl_dev) {
360 down(&info->bl_dev->sem);
361 info->bl_dev->props->power = power;
362 __riva_bl_update_status(info->bl_dev);
363 up(&info->bl_dev->sem);
364 }
365
e01af038
MH		 366 mutex_unlock(&info->bl_mutex);
367}
368
5474c120
MH		 369static void riva_bl_init(struct riva_par *par)
370{
371 struct fb_info *info = pci_get_drvdata(par->pdev);
372 struct backlight_device *bd;
373 char name[12];
374
375 if (!par->FlatPanel)
376 return;
377
378#ifdef CONFIG_PMAC_BACKLIGHT
379 if (!machine_is(powermac) ||
380 !pmac_has_backlight_type("mnca"))
381 return;
382#endif
383
384 snprintf(name, sizeof(name), "rivabl%d", info->node);
385
386 bd = backlight_device_register(name, par, &riva_bl_data);
387 if (IS_ERR(bd)) {
388 info->bl_dev = NULL;
98a3c781 389 printk(KERN_WARNING "riva: Backlight registration failed\n");
5474c120
MH		 390 goto error;
391 }
392
393 mutex_lock(&info->bl_mutex);
394 info->bl_dev = bd;
395 fb_bl_default_curve(info, 0,
396 0x158 * FB_BACKLIGHT_MAX / MAX_LEVEL,
397 0x534 * FB_BACKLIGHT_MAX / MAX_LEVEL);
398 mutex_unlock(&info->bl_mutex);
399
a9303638 400 down(&bd->sem);
5474c120
MH		 401 bd->props->brightness = riva_bl_data.max_brightness;
402 bd->props->power = FB_BLANK_UNBLANK;
403 bd->props->update_status(bd);
a9303638 404 up(&bd->sem);
5474c120
MH		 405
406#ifdef CONFIG_PMAC_BACKLIGHT
407 mutex_lock(&pmac_backlight_mutex);
408 if (!pmac_backlight)
409 pmac_backlight = bd;
410 mutex_unlock(&pmac_backlight_mutex);
411#endif
412
413 printk("riva: Backlight initialized (%s)\n", name);
414
415 return;
416
417error:
418 return;
419}
420
421static void riva_bl_exit(struct riva_par *par)
422{
423 struct fb_info *info = pci_get_drvdata(par->pdev);
424
425#ifdef CONFIG_PMAC_BACKLIGHT
426 mutex_lock(&pmac_backlight_mutex);
427#endif
428
429 mutex_lock(&info->bl_mutex);
430 if (info->bl_dev) {
431#ifdef CONFIG_PMAC_BACKLIGHT
432 if (pmac_backlight == info->bl_dev)
433 pmac_backlight = NULL;
434#endif
435
436 backlight_device_unregister(info->bl_dev);
437
438 printk("riva: Backlight unloaded\n");
439 }
440 mutex_unlock(&info->bl_mutex);
441
442#ifdef CONFIG_PMAC_BACKLIGHT
443 mutex_unlock(&pmac_backlight_mutex);
444#endif
445}
446#else
447static inline void riva_bl_init(struct riva_par *par) {}
448static inline void riva_bl_exit(struct riva_par *par) {}
e01af038 449static inline void riva_bl_set_power(struct fb_info *info, int power) {}
5474c120 450#endif /* CONFIG_FB_RIVA_BACKLIGHT */
1da177e4
LT		 451
452/* ------------------------------------------------------------------------- *
453 *
454 * MMIO access macros
455 *
456 * ------------------------------------------------------------------------- */
457
458static inline void CRTCout(struct riva_par *par, unsigned char index,
459 unsigned char val)
460{
461 VGA_WR08(par->riva.PCIO, 0x3d4, index);
462 VGA_WR08(par->riva.PCIO, 0x3d5, val);
463}
464
465static inline unsigned char CRTCin(struct riva_par *par,
466 unsigned char index)
467{
468 VGA_WR08(par->riva.PCIO, 0x3d4, index);
469 return (VGA_RD08(par->riva.PCIO, 0x3d5));
470}
471
472static inline void GRAout(struct riva_par *par, unsigned char index,
473 unsigned char val)
474{
475 VGA_WR08(par->riva.PVIO, 0x3ce, index);
476 VGA_WR08(par->riva.PVIO, 0x3cf, val);
477}
478
479static inline unsigned char GRAin(struct riva_par *par,
480 unsigned char index)
481{
482 VGA_WR08(par->riva.PVIO, 0x3ce, index);
483 return (VGA_RD08(par->riva.PVIO, 0x3cf));
484}
485
486static inline void SEQout(struct riva_par *par, unsigned char index,
487 unsigned char val)
488{
489 VGA_WR08(par->riva.PVIO, 0x3c4, index);
490 VGA_WR08(par->riva.PVIO, 0x3c5, val);
491}
492
493static inline unsigned char SEQin(struct riva_par *par,
494 unsigned char index)
495{
496 VGA_WR08(par->riva.PVIO, 0x3c4, index);
497 return (VGA_RD08(par->riva.PVIO, 0x3c5));
498}
499
500static inline void ATTRout(struct riva_par *par, unsigned char index,
501 unsigned char val)
502{
503 VGA_WR08(par->riva.PCIO, 0x3c0, index);
504 VGA_WR08(par->riva.PCIO, 0x3c0, val);
505}
506
507static inline unsigned char ATTRin(struct riva_par *par,
508 unsigned char index)
509{
510 VGA_WR08(par->riva.PCIO, 0x3c0, index);
511 return (VGA_RD08(par->riva.PCIO, 0x3c1));
512}
513
514static inline void MISCout(struct riva_par *par, unsigned char val)
515{
516 VGA_WR08(par->riva.PVIO, 0x3c2, val);
517}
518
519static inline unsigned char MISCin(struct riva_par *par)
520{
521 return (VGA_RD08(par->riva.PVIO, 0x3cc));
522}
523
524static u8 byte_rev[256] = {
525 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
526 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
527 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
528 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
529 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
530 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
531 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
532 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
533 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
534 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
535 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
536 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
537 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
538 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
539 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
540 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
541 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
542 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
543 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
544 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
545 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
546 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
547 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
548 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
549 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
550 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
551 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
552 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
553 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
554 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
555 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
556 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
557};
558
559static inline void reverse_order(u32 *l)
560{
561 u8 *a = (u8 *)l;
562 *a = byte_rev[*a], a++;
563 *a = byte_rev[*a], a++;
564 *a = byte_rev[*a], a++;
565 *a = byte_rev[*a];
566}
567
568/* ------------------------------------------------------------------------- *
569 *
570 * cursor stuff
571 *
572 * ------------------------------------------------------------------------- */
573
574/**
575 * rivafb_load_cursor_image - load cursor image to hardware
576 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
577 * @par: pointer to private data
578 * @w: width of cursor image in pixels
579 * @h: height of cursor image in scanlines
580 * @bg: background color (ARGB1555) - alpha bit determines opacity
581 * @fg: foreground color (ARGB1555)
582 *
583 * DESCRIPTiON:
584 * Loads cursor image based on a monochrome source and mask bitmap. The
585 * image bits determines the color of the pixel, 0 for background, 1 for
586 * foreground. Only the affected region (as determined by @w and @h
587 * parameters) will be updated.
588 *
589 * CALLED FROM:
590 * rivafb_cursor()
591 */
592static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
593 u16 bg, u16 fg, u32 w, u32 h)
594{
595 int i, j, k = 0;
596 u32 b, tmp;
597 u32 *data = (u32 *)data8;
598 bg = le16_to_cpu(bg);
599 fg = le16_to_cpu(fg);
600
601 w = (w + 1) & ~1;
602
603 for (i = 0; i < h; i++) {
604 b = *data++;
605 reverse_order(&b);
606
607 for (j = 0; j < w/2; j++) {
608 tmp = 0;
609#if defined (__BIG_ENDIAN)
610 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
611 b <<= 1;
612 tmp |= (b & (1 << 31)) ? fg : bg;
613 b <<= 1;
614#else
615 tmp = (b & 1) ? fg : bg;
616 b >>= 1;
617 tmp |= (b & 1) ? fg << 16 : bg << 16;
618 b >>= 1;
619#endif
620 writel(tmp, &par->riva.CURSOR[k++]);
621 }
622 k += (MAX_CURS - w)/2;
623 }
624}
625
626/* ------------------------------------------------------------------------- *
627 *
628 * general utility functions
629 *
630 * ------------------------------------------------------------------------- */
631
632/**
633 * riva_wclut - set CLUT entry
634 * @chip: pointer to RIVA_HW_INST object
635 * @regnum: register number
636 * @red: red component
637 * @green: green component
638 * @blue: blue component
639 *
640 * DESCRIPTION:
641 * Sets color register @regnum.
642 *
643 * CALLED FROM:
644 * rivafb_setcolreg()
645 */
646static void riva_wclut(RIVA_HW_INST *chip,
647 unsigned char regnum, unsigned char red,
648 unsigned char green, unsigned char blue)
649{
650 VGA_WR08(chip->PDIO, 0x3c8, regnum);
651 VGA_WR08(chip->PDIO, 0x3c9, red);
652 VGA_WR08(chip->PDIO, 0x3c9, green);
653 VGA_WR08(chip->PDIO, 0x3c9, blue);
654}
655
656/**
657 * riva_rclut - read fromCLUT register
658 * @chip: pointer to RIVA_HW_INST object
659 * @regnum: register number
660 * @red: red component
661 * @green: green component
662 * @blue: blue component
663 *
664 * DESCRIPTION:
665 * Reads red, green, and blue from color register @regnum.
666 *
667 * CALLED FROM:
668 * rivafb_setcolreg()
669 */
670static void riva_rclut(RIVA_HW_INST *chip,
671 unsigned char regnum, unsigned char *red,
672 unsigned char *green, unsigned char *blue)
673{
674
675 VGA_WR08(chip->PDIO, 0x3c7, regnum);
676 *red = VGA_RD08(chip->PDIO, 0x3c9);
677 *green = VGA_RD08(chip->PDIO, 0x3c9);
678 *blue = VGA_RD08(chip->PDIO, 0x3c9);
679}
680
681/**
682 * riva_save_state - saves current chip state
683 * @par: pointer to riva_par object containing info for current riva board
684 * @regs: pointer to riva_regs object
685 *
686 * DESCRIPTION:
687 * Saves current chip state to @regs.
688 *
689 * CALLED FROM:
690 * rivafb_probe()
691 */
692/* from GGI */
693static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
694{
695 int i;
696
697 NVTRACE_ENTER();
698 par->riva.LockUnlock(&par->riva, 0);
699
700 par->riva.UnloadStateExt(&par->riva, &regs->ext);
701
702 regs->misc_output = MISCin(par);
703
704 for (i = 0; i < NUM_CRT_REGS; i++)
705 regs->crtc[i] = CRTCin(par, i);
706
707 for (i = 0; i < NUM_ATC_REGS; i++)
708 regs->attr[i] = ATTRin(par, i);
709
710 for (i = 0; i < NUM_GRC_REGS; i++)
711 regs->gra[i] = GRAin(par, i);
712
713 for (i = 0; i < NUM_SEQ_REGS; i++)
714 regs->seq[i] = SEQin(par, i);
715 NVTRACE_LEAVE();
716}
717
718/**
719 * riva_load_state - loads current chip state
720 * @par: pointer to riva_par object containing info for current riva board
721 * @regs: pointer to riva_regs object
722 *
723 * DESCRIPTION:
724 * Loads chip state from @regs.
725 *
726 * CALLED FROM:
727 * riva_load_video_mode()
728 * rivafb_probe()
729 * rivafb_remove()
730 */
731/* from GGI */
732static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
733{
734 RIVA_HW_STATE *state = &regs->ext;
735 int i;
736
737 NVTRACE_ENTER();
738 CRTCout(par, 0x11, 0x00);
739
740 par->riva.LockUnlock(&par->riva, 0);
741
742 par->riva.LoadStateExt(&par->riva, state);
743
744 MISCout(par, regs->misc_output);
745
746 for (i = 0; i < NUM_CRT_REGS; i++) {
747 switch (i) {
748 case 0x19:
749 case 0x20 ... 0x40:
750 break;
751 default:
752 CRTCout(par, i, regs->crtc[i]);
753 }
754 }
755
756 for (i = 0; i < NUM_ATC_REGS; i++)
757 ATTRout(par, i, regs->attr[i]);
758
759 for (i = 0; i < NUM_GRC_REGS; i++)
760 GRAout(par, i, regs->gra[i]);
761
762 for (i = 0; i < NUM_SEQ_REGS; i++)
763 SEQout(par, i, regs->seq[i]);
764 NVTRACE_LEAVE();
765}
766
767/**
768 * riva_load_video_mode - calculate timings
769 * @info: pointer to fb_info object containing info for current riva board
770 *
771 * DESCRIPTION:
772 * Calculate some timings and then send em off to riva_load_state().
773 *
774 * CALLED FROM:
775 * rivafb_set_par()
776 */
777static void riva_load_video_mode(struct fb_info *info)
778{
779 int bpp, width, hDisplaySize, hDisplay, hStart,
780 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
781 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
f4a41836 782 struct riva_par *par = info->par;
1da177e4
LT		 783 struct riva_regs newmode;
784
785 NVTRACE_ENTER();
786 /* time to calculate */
787 rivafb_blank(1, info);
788
789 bpp = info->var.bits_per_pixel;
790 if (bpp == 16 && info->var.green.length == 5)
791 bpp = 15;
792 width = info->var.xres_virtual;
793 hDisplaySize = info->var.xres;
794 hDisplay = (hDisplaySize / 8) - 1;
795 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
796 hEnd = (hDisplaySize + info->var.right_margin +
797 info->var.hsync_len) / 8 - 1;
798 hTotal = (hDisplaySize + info->var.right_margin +
799 info->var.hsync_len + info->var.left_margin) / 8 - 5;
800 hBlankStart = hDisplay;
801 hBlankEnd = hTotal + 4;
802
803 height = info->var.yres_virtual;
804 vDisplay = info->var.yres - 1;
805 vStart = info->var.yres + info->var.lower_margin - 1;
806 vEnd = info->var.yres + info->var.lower_margin +
807 info->var.vsync_len - 1;
808 vTotal = info->var.yres + info->var.lower_margin +
809 info->var.vsync_len + info->var.upper_margin + 2;
810 vBlankStart = vDisplay;
811 vBlankEnd = vTotal + 1;
812 dotClock = 1000000000 / info->var.pixclock;
813
814 memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
815
816 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
817 vTotal |= 1;
818
819 if (par->FlatPanel) {
820 vStart = vTotal - 3;
821 vEnd = vTotal - 2;
822 vBlankStart = vStart;
823 hStart = hTotal - 3;
824 hEnd = hTotal - 2;
825 hBlankEnd = hTotal + 4;
826 }
827
828 newmode.crtc[0x0] = Set8Bits (hTotal);
829 newmode.crtc[0x1] = Set8Bits (hDisplay);
830 newmode.crtc[0x2] = Set8Bits (hBlankStart);
831 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
832 newmode.crtc[0x4] = Set8Bits (hStart);
833 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
834 | SetBitField (hEnd, 4: 0, 4:0);
835 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
836 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
837 | SetBitField (vDisplay, 8: 8, 1:1)
838 | SetBitField (vStart, 8: 8, 2:2)
839 | SetBitField (vBlankStart, 8: 8, 3:3)
840 | SetBit (4)
841 | SetBitField (vTotal, 9: 9, 5:5)
842 | SetBitField (vDisplay, 9: 9, 6:6)
843 | SetBitField (vStart, 9: 9, 7:7);
844 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
845 | SetBit (6);
846 newmode.crtc[0x10] = Set8Bits (vStart);
847 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
848 | SetBit (5);
849 newmode.crtc[0x12] = Set8Bits (vDisplay);
850 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
851 newmode.crtc[0x15] = Set8Bits (vBlankStart);
852 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
853
854 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
855 | SetBitField(vBlankStart,10:10,3:3)
856 | SetBitField(vStart,10:10,2:2)
857 | SetBitField(vDisplay,10:10,1:1)
858 | SetBitField(vTotal,10:10,0:0);
859 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
860 | SetBitField(hDisplay,8:8,1:1)
861 | SetBitField(hBlankStart,8:8,2:2)
862 | SetBitField(hStart,8:8,3:3);
863 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
864 | SetBitField(vDisplay,11:11,2:2)
865 | SetBitField(vStart,11:11,4:4)
866 | SetBitField(vBlankStart,11:11,6:6);
867
868 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
869 int tmp = (hTotal >> 1) & ~1;
870 newmode.ext.interlace = Set8Bits(tmp);
871 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
872 } else
873 newmode.ext.interlace = 0xff; /* interlace off */
874
875 if (par->riva.Architecture >= NV_ARCH_10)
876 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
877
878 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
879 newmode.misc_output &= ~0x40;
880 else
881 newmode.misc_output |= 0x40;
882 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
883 newmode.misc_output &= ~0x80;
884 else
885 newmode.misc_output |= 0x80;
886
887 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
888 hDisplaySize, height, dotClock);
889
890 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
891 0xfff000ff;
892 if (par->FlatPanel == 1) {
893 newmode.ext.pixel |= (1 << 7);
894 newmode.ext.scale |= (1 << 8);
895 }
896 if (par->SecondCRTC) {
897 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
898 ~0x00001000;
899 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
900 0x00001000;
901 newmode.ext.crtcOwner = 3;
902 newmode.ext.pllsel |= 0x20000800;
903 newmode.ext.vpll2 = newmode.ext.vpll;
904 } else if (par->riva.twoHeads) {
905 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
906 0x00001000;
907 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
908 ~0x00001000;
909 newmode.ext.crtcOwner = 0;
910 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
911 }
912 if (par->FlatPanel == 1) {
913 newmode.ext.pixel |= (1 << 7);
914 newmode.ext.scale |= (1 << 8);
915 }
916 newmode.ext.cursorConfig = 0x02000100;
917 par->current_state = newmode;
918 riva_load_state(par, &par->current_state);
919 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
920 rivafb_blank(0, info);
921 NVTRACE_LEAVE();
922}
923
924static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
925{
926 NVTRACE_ENTER();
927 var->xres = var->xres_virtual = modedb->xres;
928 var->yres = modedb->yres;
929 if (var->yres_virtual < var->yres)
930 var->yres_virtual = var->yres;
931 var->xoffset = var->yoffset = 0;
932 var->pixclock = modedb->pixclock;
933 var->left_margin = modedb->left_margin;
934 var->right_margin = modedb->right_margin;
935 var->upper_margin = modedb->upper_margin;
936 var->lower_margin = modedb->lower_margin;
937 var->hsync_len = modedb->hsync_len;
938 var->vsync_len = modedb->vsync_len;
939 var->sync = modedb->sync;
940 var->vmode = modedb->vmode;
941 NVTRACE_LEAVE();
942}
943
944/**
945 * rivafb_do_maximize -
946 * @info: pointer to fb_info object containing info for current riva board
947 * @var:
948 * @nom:
949 * @den:
950 *
951 * DESCRIPTION:
952 * .
953 *
954 * RETURNS:
955 * -EINVAL on failure, 0 on success
956 *
957 *
958 * CALLED FROM:
959 * rivafb_check_var()
960 */
961static int rivafb_do_maximize(struct fb_info *info,
962 struct fb_var_screeninfo *var,
963 int nom, int den)
964{
965 static struct {
966 int xres, yres;
967 } modes[] = {
968 {1600, 1280},
969 {1280, 1024},
970 {1024, 768},
971 {800, 600},
972 {640, 480},
973 {-1, -1}
974 };
975 int i;
976
977 NVTRACE_ENTER();
978 /* use highest possible virtual resolution */
979 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
980 printk(KERN_WARNING PFX
981 "using maximum available virtual resolution\n");
982 for (i = 0; modes[i].xres != -1; i++) {
983 if (modes[i].xres * nom / den * modes[i].yres <
984 info->fix.smem_len)
985 break;
986 }
987 if (modes[i].xres == -1) {
988 printk(KERN_ERR PFX
989 "could not find a virtual resolution that fits into video memory!!\n");
990 NVTRACE("EXIT - EINVAL error\n");
991 return -EINVAL;
992 }
993 var->xres_virtual = modes[i].xres;
994 var->yres_virtual = modes[i].yres;
995
996 printk(KERN_INFO PFX
997 "virtual resolution set to maximum of %dx%d\n",
998 var->xres_virtual, var->yres_virtual);
999 } else if (var->xres_virtual == -1) {
1000 var->xres_virtual = (info->fix.smem_len * den /
1001 (nom * var->yres_virtual)) & ~15;
1002 printk(KERN_WARNING PFX
1003 "setting virtual X resolution to %d\n", var->xres_virtual);
1004 } else if (var->yres_virtual == -1) {
1005 var->xres_virtual = (var->xres_virtual + 15) & ~15;
1006 var->yres_virtual = info->fix.smem_len * den /
1007 (nom * var->xres_virtual);
1008 printk(KERN_WARNING PFX
1009 "setting virtual Y resolution to %d\n", var->yres_virtual);
1010 } else {
1011 var->xres_virtual = (var->xres_virtual + 15) & ~15;
1012 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
1013 printk(KERN_ERR PFX
1014 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
1015 var->xres, var->yres, var->bits_per_pixel);
1016 NVTRACE("EXIT - EINVAL error\n");
1017 return -EINVAL;
1018 }
1019 }
1020
1021 if (var->xres_virtual * nom / den >= 8192) {
1022 printk(KERN_WARNING PFX
1023 "virtual X resolution (%d) is too high, lowering to %d\n",
1024 var->xres_virtual, 8192 * den / nom - 16);
1025 var->xres_virtual = 8192 * den / nom - 16;
1026 }
1027
1028 if (var->xres_virtual < var->xres) {
1029 printk(KERN_ERR PFX
1030 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
1031 return -EINVAL;
1032 }
1033
1034 if (var->yres_virtual < var->yres) {
1035 printk(KERN_ERR PFX
1036 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
1037 return -EINVAL;
1038 }
1039 if (var->yres_virtual > 0x7fff/nom)
1040 var->yres_virtual = 0x7fff/nom;
1041 if (var->xres_virtual > 0x7fff/nom)
1042 var->xres_virtual = 0x7fff/nom;
1043 NVTRACE_LEAVE();
1044 return 0;
1045}
1046
1047static void
1048riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
1049{
1050 RIVA_FIFO_FREE(par->riva, Patt, 4);
1051 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
1052 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
1053 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
1054 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
1055}
1056
1057/* acceleration routines */
1058static inline void wait_for_idle(struct riva_par *par)
1059{
1060 while (par->riva.Busy(&par->riva));
1061}
1062
1063/*
1064 * Set ROP. Translate X rop into ROP3. Internal routine.
1065 */
1066static void
1067riva_set_rop_solid(struct riva_par *par, int rop)
1068{
1069 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1070 RIVA_FIFO_FREE(par->riva, Rop, 1);
1071 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
1072
1073}
1074
1075static void riva_setup_accel(struct fb_info *info)
1076{
f4a41836 1077 struct riva_par *par = info->par;
1da177e4
LT		 1078
1079 RIVA_FIFO_FREE(par->riva, Clip, 2);
1080 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
1081 NV_WR32(&par->riva.Clip->WidthHeight, 0,
1082 (info->var.xres_virtual & 0xffff) |
1083 (info->var.yres_virtual << 16));
1084 riva_set_rop_solid(par, 0xcc);
1085 wait_for_idle(par);
1086}
1087
1088/**
1089 * riva_get_cmap_len - query current color map length
1090 * @var: standard kernel fb changeable data
1091 *
1092 * DESCRIPTION:
1093 * Get current color map length.
1094 *
1095 * RETURNS:
1096 * Length of color map
1097 *
1098 * CALLED FROM:
1099 * rivafb_setcolreg()
1100 */
1101static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1102{
1103 int rc = 256; /* reasonable default */
1104
1105 switch (var->green.length) {
1106 case 8:
1107 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1108 break;
1109 case 5:
1110 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1111 break;
1112 case 6:
1113 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1114 break;
1115 default:
1116 /* should not occur */
1117 break;
1118 }
1119 return rc;
1120}
1121
1da177e4
LT		 1122/* ------------------------------------------------------------------------- *
1123 *
1124 * framebuffer operations
1125 *
1126 * ------------------------------------------------------------------------- */
1127
1128static int rivafb_open(struct fb_info *info, int user)
1129{
f4a41836 1130 struct riva_par *par = info->par;
1da177e4
LT		 1131 int cnt = atomic_read(&par->ref_count);
1132
1133 NVTRACE_ENTER();
1134 if (!cnt) {
1135#ifdef CONFIG_X86
1136 memset(&par->state, 0, sizeof(struct vgastate));
1137 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1138 /* save the DAC for Riva128 */
1139 if (par->riva.Architecture == NV_ARCH_03)
1140 par->state.flags |= VGA_SAVE_CMAP;
1141 save_vga(&par->state);
1142#endif
1143 /* vgaHWunlock() + riva unlock (0x7F) */
1144 CRTCout(par, 0x11, 0xFF);
1145 par->riva.LockUnlock(&par->riva, 0);
1146
1147 riva_save_state(par, &par->initial_state);
1148 }
1149 atomic_inc(&par->ref_count);
1150 NVTRACE_LEAVE();
1151 return 0;
1152}
1153
1154static int rivafb_release(struct fb_info *info, int user)
1155{
f4a41836 1156 struct riva_par *par = info->par;
1da177e4
LT		 1157 int cnt = atomic_read(&par->ref_count);
1158
1159 NVTRACE_ENTER();
1160 if (!cnt)
1161 return -EINVAL;
1162 if (cnt == 1) {
1163 par->riva.LockUnlock(&par->riva, 0);
1164 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1165 riva_load_state(par, &par->initial_state);
1166#ifdef CONFIG_X86
1167 restore_vga(&par->state);
1168#endif
1169 par->riva.LockUnlock(&par->riva, 1);
1170 }
1171 atomic_dec(&par->ref_count);
1172 NVTRACE_LEAVE();
1173 return 0;
1174}
1175
1176static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1177{
1178 struct fb_videomode *mode;
f4a41836 1179 struct riva_par *par = info->par;
1da177e4
LT		 1180 int nom, den; /* translating from pixels->bytes */
1181 int mode_valid = 0;
1182
1183 NVTRACE_ENTER();
1184 switch (var->bits_per_pixel) {
1185 case 1 ... 8:
1186 var->red.offset = var->green.offset = var->blue.offset = 0;
1187 var->red.length = var->green.length = var->blue.length = 8;
1188 var->bits_per_pixel = 8;
1189 nom = den = 1;
1190 break;
1191 case 9 ... 15:
1192 var->green.length = 5;
1193 /* fall through */
1194 case 16:
1195 var->bits_per_pixel = 16;
1196 /* The Riva128 supports RGB555 only */
1197 if (par->riva.Architecture == NV_ARCH_03)
1198 var->green.length = 5;
1199 if (var->green.length == 5) {
1200 /* 0rrrrrgg gggbbbbb */
1201 var->red.offset = 10;
1202 var->green.offset = 5;
1203 var->blue.offset = 0;
1204 var->red.length = 5;
1205 var->green.length = 5;
1206 var->blue.length = 5;
1207 } else {
1208 /* rrrrrggg gggbbbbb */
1209 var->red.offset = 11;
1210 var->green.offset = 5;
1211 var->blue.offset = 0;
1212 var->red.length = 5;
1213 var->green.length = 6;
1214 var->blue.length = 5;
1215 }
1216 nom = 2;
1217 den = 1;
1218 break;
1219 case 17 ... 32:
1220 var->red.length = var->green.length = var->blue.length = 8;
1221 var->bits_per_pixel = 32;
1222 var->red.offset = 16;
1223 var->green.offset = 8;
1224 var->blue.offset = 0;
1225 nom = 4;
1226 den = 1;
1227 break;
1228 default:
1229 printk(KERN_ERR PFX
1230 "mode %dx%dx%d rejected...color depth not supported.\n",
1231 var->xres, var->yres, var->bits_per_pixel);
1232 NVTRACE("EXIT, returning -EINVAL\n");
1233 return -EINVAL;
1234 }
1235
1236 if (!strictmode) {
1237 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1238 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1239 mode_valid = 1;
1240 }
1241
1242 /* calculate modeline if supported by monitor */
1243 if (!mode_valid && info->monspecs.gtf) {
1244 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1245 mode_valid = 1;
1246 }
1247
1248 if (!mode_valid) {
1249 mode = fb_find_best_mode(var, &info->modelist);
1250 if (mode) {
1251 riva_update_var(var, mode);
1252 mode_valid = 1;
1253 }
1254 }
1255
1256 if (!mode_valid && info->monspecs.modedb_len)
1257 return -EINVAL;
1258
1259 if (var->xres_virtual < var->xres)
1260 var->xres_virtual = var->xres;
1261 if (var->yres_virtual <= var->yres)
1262 var->yres_virtual = -1;
1263 if (rivafb_do_maximize(info, var, nom, den) < 0)
1264 return -EINVAL;
1265
1266 if (var->xoffset < 0)
1267 var->xoffset = 0;
1268 if (var->yoffset < 0)
1269 var->yoffset = 0;
1270
1271 /* truncate xoffset and yoffset to maximum if too high */
1272 if (var->xoffset > var->xres_virtual - var->xres)
1273 var->xoffset = var->xres_virtual - var->xres - 1;
1274
1275 if (var->yoffset > var->yres_virtual - var->yres)
1276 var->yoffset = var->yres_virtual - var->yres - 1;
1277
1278 var->red.msb_right =
1279 var->green.msb_right =
1280 var->blue.msb_right =
1281 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1282 NVTRACE_LEAVE();
1283 return 0;
1284}
1285
1286static int rivafb_set_par(struct fb_info *info)
1287{
f4a41836 1288 struct riva_par *par = info->par;
1da177e4
LT		 1289
1290 NVTRACE_ENTER();
1291 /* vgaHWunlock() + riva unlock (0x7F) */
1292 CRTCout(par, 0x11, 0xFF);
1293 par->riva.LockUnlock(&par->riva, 0);
1294 riva_load_video_mode(info);
1295 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1296 riva_setup_accel(info);
1297
1298 par->cursor_reset = 1;
1299 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1300 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1301 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1302
1303 if (info->flags & FBINFO_HWACCEL_DISABLED)
1304 info->pixmap.scan_align = 1;
1305 else
1306 info->pixmap.scan_align = 4;
1307 NVTRACE_LEAVE();
1308 return 0;
1309}
1310
1311/**
1312 * rivafb_pan_display
1313 * @var: standard kernel fb changeable data
1314 * @con: TODO
1315 * @info: pointer to fb_info object containing info for current riva board
1316 *
1317 * DESCRIPTION:
1318 * Pan (or wrap, depending on the `vmode' field) the display using the
1319 * `xoffset' and `yoffset' fields of the `var' structure.
1320 * If the values don't fit, return -EINVAL.
1321 *
1322 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1323 */
1324static int rivafb_pan_display(struct fb_var_screeninfo *var,
1325 struct fb_info *info)
1326{
f4a41836 1327 struct riva_par *par = info->par;
1da177e4
LT		 1328 unsigned int base;
1329
1330 NVTRACE_ENTER();
1da177e4 1331 base = var->yoffset * info->fix.line_length + var->xoffset;
1da177e4 1332 par->riva.SetStartAddress(&par->riva, base);
1da177e4
LT		 1333 NVTRACE_LEAVE();
1334 return 0;
1335}
1336
1337static int rivafb_blank(int blank, struct fb_info *info)
1338{
f4a41836 1339 struct riva_par *par= info->par;
1da177e4
LT		 1340 unsigned char tmp, vesa;
1341
1342 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1343 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1344
1345 NVTRACE_ENTER();
1346
1347 if (blank)
1348 tmp |= 0x20;
1349
1350 switch (blank) {
1351 case FB_BLANK_UNBLANK:
1352 case FB_BLANK_NORMAL:
1353 break;
1354 case FB_BLANK_VSYNC_SUSPEND:
1355 vesa |= 0x80;
1356 break;
1357 case FB_BLANK_HSYNC_SUSPEND:
1358 vesa |= 0x40;
1359 break;
1360 case FB_BLANK_POWERDOWN:
1361 vesa |= 0xc0;
1362 break;
1363 }
1364
1365 SEQout(par, 0x01, tmp);
1366 CRTCout(par, 0x1a, vesa);
1367
e01af038 1368 riva_bl_set_power(info, blank);
1da177e4
LT		 1369
1370 NVTRACE_LEAVE();
1371
1372 return 0;
1373}
1374
1375/**
1376 * rivafb_setcolreg
1377 * @regno: register index
1378 * @red: red component
1379 * @green: green component
1380 * @blue: blue component
1381 * @transp: transparency
1382 * @info: pointer to fb_info object containing info for current riva board
1383 *
1384 * DESCRIPTION:
1385 * Set a single color register. The values supplied have a 16 bit
1386 * magnitude.
1387 *
1388 * RETURNS:
1389 * Return != 0 for invalid regno.
1390 *
1391 * CALLED FROM:
1392 * fbcmap.c:fb_set_cmap()
1393 */
1394static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1395 unsigned blue, unsigned transp,
1396 struct fb_info *info)
1397{
f4a41836 1398 struct riva_par *par = info->par;
1da177e4
LT		 1399 RIVA_HW_INST *chip = &par->riva;
1400 int i;
1401
1402 if (regno >= riva_get_cmap_len(&info->var))
1403 return -EINVAL;
1404
1405 if (info->var.grayscale) {
1406 /* gray = 0.30*R + 0.59*G + 0.11*B */
1407 red = green = blue =
1408 (red * 77 + green * 151 + blue * 28) >> 8;
1409 }
1410
1411 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1412 ((u32 *) info->pseudo_palette)[regno] =
1413 (regno << info->var.red.offset) |
1414 (regno << info->var.green.offset) |
1415 (regno << info->var.blue.offset);
1416 /*
1417 * The Riva128 2D engine requires color information in
1418 * TrueColor format even if framebuffer is in DirectColor
1419 */
1420 if (par->riva.Architecture == NV_ARCH_03) {
1421 switch (info->var.bits_per_pixel) {
1422 case 16:
1423 par->palette[regno] = ((red & 0xf800) >> 1) |
1424 ((green & 0xf800) >> 6) |
1425 ((blue & 0xf800) >> 11);
1426 break;
1427 case 32:
1428 par->palette[regno] = ((red & 0xff00) << 8) |
1429 ((green & 0xff00)) |
1430 ((blue & 0xff00) >> 8);
1431 break;
1432 }
1433 }
1434 }
1435
1436 switch (info->var.bits_per_pixel) {
1437 case 8:
1438 /* "transparent" stuff is completely ignored. */
1439 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1440 break;
1441 case 16:
1442 if (info->var.green.length == 5) {
1443 for (i = 0; i < 8; i++) {
1444 riva_wclut(chip, regno*8+i, red >> 8,
1445 green >> 8, blue >> 8);
1446 }
1447 } else {
1448 u8 r, g, b;
1449
1450 if (regno < 32) {
1451 for (i = 0; i < 8; i++) {
1452 riva_wclut(chip, regno*8+i,
1453 red >> 8, green >> 8,
1454 blue >> 8);
1455 }
1456 }
1457 riva_rclut(chip, regno*4, &r, &g, &b);
1458 for (i = 0; i < 4; i++)
1459 riva_wclut(chip, regno*4+i, r,
1460 green >> 8, b);
1461 }
1462 break;
1463 case 32:
1464 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1465 break;
1466 default:
1467 /* do nothing */
1468 break;
1469 }
1470 return 0;
1471}
1472
1473/**
1474 * rivafb_fillrect - hardware accelerated color fill function
1475 * @info: pointer to fb_info structure
1476 * @rect: pointer to fb_fillrect structure
1477 *
1478 * DESCRIPTION:
1479 * This function fills up a region of framebuffer memory with a solid
1480 * color with a choice of two different ROP's, copy or invert.
1481 *
1482 * CALLED FROM:
1483 * framebuffer hook
1484 */
1485static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1486{
f4a41836 1487 struct riva_par *par = info->par;
1da177e4
LT		 1488 u_int color, rop = 0;
1489
1490 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1491 cfb_fillrect(info, rect);
1492 return;
1493 }
1494
1495 if (info->var.bits_per_pixel == 8)
1496 color = rect->color;
1497 else {
1498 if (par->riva.Architecture != NV_ARCH_03)
1499 color = ((u32 *)info->pseudo_palette)[rect->color];
1500 else
1501 color = par->palette[rect->color];
1502 }
1503
1504 switch (rect->rop) {
1505 case ROP_XOR:
1506 rop = 0x66;
1507 break;
1508 case ROP_COPY:
1509 default:
1510 rop = 0xCC;
1511 break;
1512 }
1513
1514 riva_set_rop_solid(par, rop);
1515
1516 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1517 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1518
1519 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1520 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1521 (rect->dx << 16) | rect->dy);
1522 mb();
1523 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1524 (rect->width << 16) | rect->height);
1525 mb();
1526 riva_set_rop_solid(par, 0xcc);
1527
1528}
1529
1530/**
1531 * rivafb_copyarea - hardware accelerated blit function
1532 * @info: pointer to fb_info structure
1533 * @region: pointer to fb_copyarea structure
1534 *
1535 * DESCRIPTION:
1536 * This copies an area of pixels from one location to another
1537 *
1538 * CALLED FROM:
1539 * framebuffer hook
1540 */
1541static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1542{
f4a41836 1543 struct riva_par *par = info->par;
1da177e4
LT		 1544
1545 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1546 cfb_copyarea(info, region);
1547 return;
1548 }
1549
1550 RIVA_FIFO_FREE(par->riva, Blt, 3);
1551 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1552 (region->sy << 16) | region->sx);
1553 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1554 (region->dy << 16) | region->dx);
1555 mb();
1556 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1557 (region->height << 16) | region->width);
1558 mb();
1559}
1560
1561static inline void convert_bgcolor_16(u32 *col)
1562{
1563 *col = ((*col & 0x0000F800) << 8)
1564 | ((*col & 0x00007E0) << 5)
1565 | ((*col & 0x0000001F) << 3)
1566 | 0xFF000000;
1567 mb();
1568}
1569
1570/**
1571 * rivafb_imageblit: hardware accelerated color expand function
1572 * @info: pointer to fb_info structure
1573 * @image: pointer to fb_image structure
1574 *
1575 * DESCRIPTION:
1576 * If the source is a monochrome bitmap, the function fills up a a region
1577 * of framebuffer memory with pixels whose color is determined by the bit
1578 * setting of the bitmap, 1 - foreground, 0 - background.
1579 *
1580 * If the source is not a monochrome bitmap, color expansion is not done.
1581 * In this case, it is channeled to a software function.
1582 *
1583 * CALLED FROM:
1584 * framebuffer hook
1585 */
1586static void rivafb_imageblit(struct fb_info *info,
1587 const struct fb_image *image)
1588{
f4a41836 1589 struct riva_par *par = info->par;
1da177e4
LT		 1590 u32 fgx = 0, bgx = 0, width, tmp;
1591 u8 *cdat = (u8 *) image->data;
1592 volatile u32 __iomem *d;
1593 int i, size;
1594
1595 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1596 cfb_imageblit(info, image);
1597 return;
1598 }
1599
1600 switch (info->var.bits_per_pixel) {
1601 case 8:
1602 fgx = image->fg_color;
1603 bgx = image->bg_color;
1604 break;
1605 case 16:
1606 case 32:
1607 if (par->riva.Architecture != NV_ARCH_03) {
1608 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1609 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1610 } else {
1611 fgx = par->palette[image->fg_color];
1612 bgx = par->palette[image->bg_color];
1613 }
1614 if (info->var.green.length == 6)
1615 convert_bgcolor_16(&bgx);
1616 break;
1617 }
1618
1619 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1620 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1621 (image->dy << 16) | (image->dx & 0xFFFF));
1622 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1623 (((image->dy + image->height) << 16) |
1624 ((image->dx + image->width) & 0xffff)));
1625 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1626 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1627 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1628 (image->height << 16) | ((image->width + 31) & ~31));
1629 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1630 (image->height << 16) | ((image->width + 31) & ~31));
1631 NV_WR32(&par->riva.Bitmap->PointE, 0,
1632 (image->dy << 16) | (image->dx & 0xFFFF));
1633
1634 d = &par->riva.Bitmap->MonochromeData01E;
1635
1636 width = (image->width + 31)/32;
1637 size = width * image->height;
1638 while (size >= 16) {
1639 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1640 for (i = 0; i < 16; i++) {
1641 tmp = *((u32 *)cdat);
1642 cdat = (u8 *)((u32 *)cdat + 1);
1643 reverse_order(&tmp);
1644 NV_WR32(d, i*4, tmp);
1645 }
1646 size -= 16;
1647 }
1648 if (size) {
1649 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1650 for (i = 0; i < size; i++) {
1651 tmp = *((u32 *) cdat);
1652 cdat = (u8 *)((u32 *)cdat + 1);
1653 reverse_order(&tmp);
1654 NV_WR32(d, i*4, tmp);
1655 }
1656 }
1657}
1658
1659/**
1660 * rivafb_cursor - hardware cursor function
1661 * @info: pointer to info structure
1662 * @cursor: pointer to fbcursor structure
1663 *
1664 * DESCRIPTION:
1665 * A cursor function that supports displaying a cursor image via hardware.
1666 * Within the kernel, copy and invert rops are supported. If exported
1667 * to user space, only the copy rop will be supported.
1668 *
1669 * CALLED FROM
1670 * framebuffer hook
1671 */
1672static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1673{
f4a41836 1674 struct riva_par *par = info->par;
1da177e4 1675 u8 data[MAX_CURS * MAX_CURS/8];
1da177e4 1676 int i, set = cursor->set;
f1ab5dac 1677 u16 fg, bg;
1da177e4 1678
f1ab5dac
JS		 1679 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1680 return -ENXIO;
1da177e4
LT		 1681
1682 par->riva.ShowHideCursor(&par->riva, 0);
1683
1684 if (par->cursor_reset) {
1685 set = FB_CUR_SETALL;
1686 par->cursor_reset = 0;
1687 }
1688
1689 if (set & FB_CUR_SETSIZE)
1690 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1691
1692 if (set & FB_CUR_SETPOS) {
1693 u32 xx, yy, temp;
1694
1695 yy = cursor->image.dy - info->var.yoffset;
1696 xx = cursor->image.dx - info->var.xoffset;
1697 temp = xx & 0xFFFF;
1698 temp |= yy << 16;
1699
1700 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1701 }
1702
1703
1704 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1705 u32 bg_idx = cursor->image.bg_color;
1706 u32 fg_idx = cursor->image.fg_color;
1707 u32 s_pitch = (cursor->image.width+7) >> 3;
1708 u32 d_pitch = MAX_CURS/8;
1709 u8 *dat = (u8 *) cursor->image.data;
1710 u8 *msk = (u8 *) cursor->mask;
1711 u8 *src;
1712
1713 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1714
1715 if (src) {
1716 switch (cursor->rop) {
1717 case ROP_XOR:
f1ab5dac 1718 for (i = 0; i < s_pitch * cursor->image.height; i++)
1da177e4
LT		 1719 src[i] = dat[i] ^ msk[i];
1720 break;
1721 case ROP_COPY:
1722 default:
f1ab5dac 1723 for (i = 0; i < s_pitch * cursor->image.height; i++)
1da177e4
LT		 1724 src[i] = dat[i] & msk[i];
1725 break;
1726 }
1727
f1ab5dac
JS		 1728 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1729 cursor->image.height);
1da177e4
LT		 1730
1731 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1732 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1733 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1734 1 << 15;
1735
1736 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1737 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1738 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1739 1 << 15;
1740
1741 par->riva.LockUnlock(&par->riva, 0);
1742
1743 rivafb_load_cursor_image(par, data, bg, fg,
1744 cursor->image.width,
1745 cursor->image.height);
1746 kfree(src);
1747 }
1748 }
1749
1750 if (cursor->enable)
1751 par->riva.ShowHideCursor(&par->riva, 1);
1752
1753 return 0;
1754}
1755
1756static int rivafb_sync(struct fb_info *info)
1757{
f4a41836 1758 struct riva_par *par = info->par;
1da177e4
LT		 1759
1760 wait_for_idle(par);
1761 return 0;
1762}
1763
1764/* ------------------------------------------------------------------------- *
1765 *
1766 * initialization helper functions
1767 *
1768 * ------------------------------------------------------------------------- */
1769
1770/* kernel interface */
1771static struct fb_ops riva_fb_ops = {
1772 .owner = THIS_MODULE,
1773 .fb_open = rivafb_open,
1774 .fb_release = rivafb_release,
1775 .fb_check_var = rivafb_check_var,
1776 .fb_set_par = rivafb_set_par,
1777 .fb_setcolreg = rivafb_setcolreg,
1778 .fb_pan_display = rivafb_pan_display,
1779 .fb_blank = rivafb_blank,
1780 .fb_fillrect = rivafb_fillrect,
1781 .fb_copyarea = rivafb_copyarea,
1782 .fb_imageblit = rivafb_imageblit,
1783 .fb_cursor = rivafb_cursor,
1784 .fb_sync = rivafb_sync,
1785};
1786
1787static int __devinit riva_set_fbinfo(struct fb_info *info)
1788{
1789 unsigned int cmap_len;
f4a41836 1790 struct riva_par *par = info->par;
1da177e4
LT		 1791
1792 NVTRACE_ENTER();
1793 info->flags = FBINFO_DEFAULT
1794 | FBINFO_HWACCEL_XPAN
1795 | FBINFO_HWACCEL_YPAN
1796 | FBINFO_HWACCEL_COPYAREA
1797 | FBINFO_HWACCEL_FILLRECT
1798 | FBINFO_HWACCEL_IMAGEBLIT;
1799
1800 /* Accel seems to not work properly on NV30 yet...*/
1801 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1802 printk(KERN_DEBUG PFX "disabling acceleration\n");
1803 info->flags |= FBINFO_HWACCEL_DISABLED;
1804 }
1805
1806 info->var = rivafb_default_var;
1807 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1808 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1809
1810 info->pseudo_palette = par->pseudo_palette;
1811
1812 cmap_len = riva_get_cmap_len(&info->var);
1813 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1814
1815 info->pixmap.size = 8 * 1024;
1816 info->pixmap.buf_align = 4;
58a60643 1817 info->pixmap.access_align = 32;
1da177e4
LT		 1818 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1819 info->var.yres_virtual = -1;
1820 NVTRACE_LEAVE();
1821 return (rivafb_check_var(&info->var, info));
1822}
1823
1824#ifdef CONFIG_PPC_OF
1825static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1826{
f4a41836 1827 struct riva_par *par = info->par;
1da177e4
LT		 1828 struct device_node *dp;
1829 unsigned char *pedid = NULL;
13b5aecc 1830 const unsigned char *disptype = NULL;
1da177e4
LT		 1831 static char *propnames[] = {
1832 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1833 int i;
1834
1835 NVTRACE_ENTER();
1836 dp = pci_device_to_OF_node(pd);
1837 for (; dp != NULL; dp = dp->child) {
b04e3dd4 1838 disptype = get_property(dp, "display-type", NULL);
1da177e4
LT		 1839 if (disptype == NULL)
1840 continue;
1841 if (strncmp(disptype, "LCD", 3) != 0)
1842 continue;
1843 for (i = 0; propnames[i] != NULL; ++i) {
b04e3dd4 1844 pedid = get_property(dp, propnames[i], NULL);
1da177e4
LT		 1845 if (pedid != NULL) {
1846 par->EDID = pedid;
1847 NVTRACE("LCD found.\n");
1848 return 1;
1849 }
1850 }
1851 }
1852 NVTRACE_LEAVE();
1853 return 0;
1854}
1855#endif /* CONFIG_PPC_OF */
1856
1857#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1858static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1859{
f4a41836 1860 struct riva_par *par = info->par;
1da177e4
LT		 1861 struct fb_var_screeninfo var;
1862 int i;
1863
1864 NVTRACE_ENTER();
1865 riva_create_i2c_busses(par);
1866 for (i = 0; i < par->bus; i++) {
1867 riva_probe_i2c_connector(par, i+1, &par->EDID);
1868 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1869 printk(PFX "Found EDID Block from BUS %i\n", i);
1870 break;
1871 }
1872 }
1873
1874 NVTRACE_LEAVE();
1875 return (par->EDID) ? 1 : 0;
1876}
1877#endif /* CONFIG_FB_RIVA_I2C */
1878
1879static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1880 struct fb_info *info)
1881{
1882 struct fb_monspecs *specs = &info->monspecs;
1883 struct fb_videomode modedb;
1884
1885 NVTRACE_ENTER();
1886 /* respect mode options */
1887 if (mode_option) {
1888 fb_find_mode(var, info, mode_option,
1889 specs->modedb, specs->modedb_len,
1890 NULL, 8);
1891 } else if (specs->modedb != NULL) {
1892 /* get preferred timing */
1893 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1894 int i;
1895
1896 for (i = 0; i < specs->modedb_len; i++) {
1897 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1898 modedb = specs->modedb[i];
1899 break;
1900 }
1901 }
1902 } else {
1903 /* otherwise, get first mode in database */
1904 modedb = specs->modedb[0];
1905 }
1906 var->bits_per_pixel = 8;
1907 riva_update_var(var, &modedb);
1908 }
1909 NVTRACE_LEAVE();
1910}
1911
1912
1913static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1914{
1915 NVTRACE_ENTER();
1916#ifdef CONFIG_PPC_OF
1917 if (!riva_get_EDID_OF(info, pdev))
1918 printk(PFX "could not retrieve EDID from OF\n");
44456d37 1919#elif defined(CONFIG_FB_RIVA_I2C)
1da177e4
LT		 1920 if (!riva_get_EDID_i2c(info))
1921 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1922#endif
1923 NVTRACE_LEAVE();
1924}
1925
1926
1927static void __devinit riva_get_edidinfo(struct fb_info *info)
1928{
1929 struct fb_var_screeninfo *var = &rivafb_default_var;
f4a41836 1930 struct riva_par *par = info->par;
1da177e4
LT		 1931
1932 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1933 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1934 &info->modelist);
1935 riva_update_default_var(var, info);
1936
1937 /* if user specified flatpanel, we respect that */
1938 if (info->monspecs.input & FB_DISP_DDI)
1939 par->FlatPanel = 1;
1940}
1941
1942/* ------------------------------------------------------------------------- *
1943 *
1944 * PCI bus
1945 *
1946 * ------------------------------------------------------------------------- */
1947
1948static u32 __devinit riva_get_arch(struct pci_dev *pd)
1949{
1950 u32 arch = 0;
1951
1952 switch (pd->device & 0x0ff0) {
1953 case 0x0100: /* GeForce 256 */
1954 case 0x0110: /* GeForce2 MX */
1955 case 0x0150: /* GeForce2 */
1956 case 0x0170: /* GeForce4 MX */
1957 case 0x0180: /* GeForce4 MX (8x AGP) */
1958 case 0x01A0: /* nForce */
1959 case 0x01F0: /* nForce2 */
1960 arch = NV_ARCH_10;
1961 break;
1962 case 0x0200: /* GeForce3 */
1963 case 0x0250: /* GeForce4 Ti */
1964 case 0x0280: /* GeForce4 Ti (8x AGP) */
1965 arch = NV_ARCH_20;
1966 break;
1967 case 0x0300: /* GeForceFX 5800 */
1968 case 0x0310: /* GeForceFX 5600 */
1969 case 0x0320: /* GeForceFX 5200 */
1970 case 0x0330: /* GeForceFX 5900 */
1971 case 0x0340: /* GeForceFX 5700 */
1972 arch = NV_ARCH_30;
1973 break;
1974 case 0x0020: /* TNT, TNT2 */
1975 arch = NV_ARCH_04;
1976 break;
1977 case 0x0010: /* Riva128 */
1978 arch = NV_ARCH_03;
1979 break;
1980 default: /* unknown architecture */
1981 break;
1982 }
1983 return arch;
1984}
1985
1986static int __devinit rivafb_probe(struct pci_dev *pd,
1987 const struct pci_device_id *ent)
1988{
1989 struct riva_par *default_par;
1990 struct fb_info *info;
1991 int ret;
1992
1993 NVTRACE_ENTER();
1994 assert(pd != NULL);
1995
1996 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1997 if (!info) {
1998 printk (KERN_ERR PFX "could not allocate memory\n");
1999 ret = -ENOMEM;
2000 goto err_ret;
2001 }
f4a41836 2002 default_par = info->par;
1da177e4
LT		 2003 default_par->pdev = pd;
2004
2005 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
2006 if (info->pixmap.addr == NULL) {
2007 ret = -ENOMEM;
2008 goto err_framebuffer_release;
2009 }
2010 memset(info->pixmap.addr, 0, 8 * 1024);
2011
2012 ret = pci_enable_device(pd);
2013 if (ret < 0) {
2014 printk(KERN_ERR PFX "cannot enable PCI device\n");
2015 goto err_free_pixmap;
2016 }
2017
2018 ret = pci_request_regions(pd, "rivafb");
2019 if (ret < 0) {
2020 printk(KERN_ERR PFX "cannot request PCI regions\n");
2021 goto err_disable_device;
2022 }
2023
2024 default_par->riva.Architecture = riva_get_arch(pd);
2025
2026 default_par->Chipset = (pd->vendor << 16) | pd->device;
2027 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
2028
1da177e4
LT		 2029 if(default_par->riva.Architecture == 0) {
2030 printk(KERN_ERR PFX "unknown NV_ARCH\n");
2031 ret=-ENODEV;
2032 goto err_release_region;
2033 }
2034 if(default_par->riva.Architecture == NV_ARCH_10 ||
2035 default_par->riva.Architecture == NV_ARCH_20 ||
2036 default_par->riva.Architecture == NV_ARCH_30) {
2037 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
2038 } else {
2039 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
2040 }
2041
2042 default_par->FlatPanel = flatpanel;
2043 if (flatpanel == 1)
2044 printk(KERN_INFO PFX "flatpanel support enabled\n");
2045 default_par->forceCRTC = forceCRTC;
2046
2047 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
2048 rivafb_fix.smem_len = pci_resource_len(pd, 1);
2049
2050 {
2051 /* enable IO and mem if not already done */
2052 unsigned short cmd;
2053
2054 pci_read_config_word(pd, PCI_COMMAND, &cmd);
2055 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
2056 pci_write_config_word(pd, PCI_COMMAND, cmd);
2057 }
2058
2059 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
2060 rivafb_fix.smem_start = pci_resource_start(pd, 1);
2061
2062 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
2063 rivafb_fix.mmio_len);
2064 if (!default_par->ctrl_base) {
2065 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
2066 ret = -EIO;
2067 goto err_release_region;
2068 }
2069
2070 switch (default_par->riva.Architecture) {
2071 case NV_ARCH_03:
2072 /* Riva128's PRAMIN is in the "framebuffer" space
2073 * Since these cards were never made with more than 8 megabytes
2074 * we can safely allocate this separately.
2075 */
2076 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
2077 if (!default_par->riva.PRAMIN) {
2078 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
2079 ret = -EIO;
2080 goto err_iounmap_ctrl_base;
2081 }
2082 break;
2083 case NV_ARCH_04:
2084 case NV_ARCH_10:
2085 case NV_ARCH_20:
2086 case NV_ARCH_30:
2087 default_par->riva.PCRTC0 =
2088 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2089 default_par->riva.PRAMIN =
2090 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2091 break;
2092 }
2093 riva_common_setup(default_par);
2094
2095 if (default_par->riva.Architecture == NV_ARCH_03) {
2096 default_par->riva.PCRTC = default_par->riva.PCRTC0
2097 = default_par->riva.PGRAPH;
2098 }
2099
2100 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2101 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2102 info->screen_base = ioremap(rivafb_fix.smem_start,
2103 rivafb_fix.smem_len);
2104 if (!info->screen_base) {
2105 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2106 ret = -EIO;
2107 goto err_iounmap_pramin;
2108 }
2109
2110#ifdef CONFIG_MTRR
2111 if (!nomtrr) {
2112 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2113 rivafb_fix.smem_len,
2114 MTRR_TYPE_WRCOMB, 1);
2115 if (default_par->mtrr.vram < 0) {
2116 printk(KERN_ERR PFX "unable to setup MTRR\n");
2117 } else {
2118 default_par->mtrr.vram_valid = 1;
2119 /* let there be speed */
2120 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2121 }
2122 }
2123#endif /* CONFIG_MTRR */
2124
2125 info->fbops = &riva_fb_ops;
2126 info->fix = rivafb_fix;
2127 riva_get_EDID(info, pd);
2128 riva_get_edidinfo(info);
2129
2130 ret=riva_set_fbinfo(info);
2131 if (ret < 0) {
2132 printk(KERN_ERR PFX "error setting initial video mode\n");
2133 goto err_iounmap_screen_base;
2134 }
2135
2136 fb_destroy_modedb(info->monspecs.modedb);
2137 info->monspecs.modedb = NULL;
ce38cac4
GG		 2138
2139 pci_set_drvdata(pd, info);
2140 riva_bl_init(info->par);
1da177e4
LT		 2141 ret = register_framebuffer(info);
2142 if (ret < 0) {
2143 printk(KERN_ERR PFX
2144 "error registering riva framebuffer\n");
2145 goto err_iounmap_screen_base;
2146 }
2147
1da177e4
LT		 2148 printk(KERN_INFO PFX
2149 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2150 info->fix.id,
2151 RIVAFB_VERSION,
2152 info->fix.smem_len / (1024 * 1024),
2153 info->fix.smem_start);
5474c120 2154
1da177e4
LT		 2155 NVTRACE_LEAVE();
2156 return 0;
2157
2158err_iounmap_screen_base:
2159#ifdef CONFIG_FB_RIVA_I2C
f4a41836 2160 riva_delete_i2c_busses(info->par);
1da177e4
LT		 2161#endif
2162 iounmap(info->screen_base);
2163err_iounmap_pramin:
2164 if (default_par->riva.Architecture == NV_ARCH_03)
2165 iounmap(default_par->riva.PRAMIN);
2166err_iounmap_ctrl_base:
2167 iounmap(default_par->ctrl_base);
2168err_release_region:
2169 pci_release_regions(pd);
2170err_disable_device:
1da177e4
LT		 2171err_free_pixmap:
2172 kfree(info->pixmap.addr);
2173err_framebuffer_release:
2174 framebuffer_release(info);
2175err_ret:
2176 return ret;
2177}
2178
2179static void __exit rivafb_remove(struct pci_dev *pd)
2180{
2181 struct fb_info *info = pci_get_drvdata(pd);
f4a41836 2182 struct riva_par *par = info->par;
1da177e4
LT		 2183
2184 NVTRACE_ENTER();
1da177e4 2185
5474c120
MH		 2186 riva_bl_exit(par);
2187
1da177e4
LT		 2188#ifdef CONFIG_FB_RIVA_I2C
2189 riva_delete_i2c_busses(par);
2190 kfree(par->EDID);
2191#endif
2192
2193 unregister_framebuffer(info);
2194#ifdef CONFIG_MTRR
2195 if (par->mtrr.vram_valid)
2196 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2197 info->fix.smem_len);
2198#endif /* CONFIG_MTRR */
2199
2200 iounmap(par->ctrl_base);
2201 iounmap(info->screen_base);
2202 if (par->riva.Architecture == NV_ARCH_03)
2203 iounmap(par->riva.PRAMIN);
2204 pci_release_regions(pd);
1da177e4
LT		 2205 kfree(info->pixmap.addr);
2206 framebuffer_release(info);
2207 pci_set_drvdata(pd, NULL);
2208 NVTRACE_LEAVE();
2209}
2210
2211/* ------------------------------------------------------------------------- *
2212 *
2213 * initialization
2214 *
2215 * ------------------------------------------------------------------------- */
2216
2217#ifndef MODULE
2218static int __init rivafb_setup(char *options)
2219{
2220 char *this_opt;
2221
2222 NVTRACE_ENTER();
2223 if (!options || !*options)
2224 return 0;
2225
2226 while ((this_opt = strsep(&options, ",")) != NULL) {
2227 if (!strncmp(this_opt, "forceCRTC", 9)) {
2228 char *p;
2229
2230 p = this_opt + 9;
2231 if (!*p || !*(++p)) continue;
2232 forceCRTC = *p - '0';
2233 if (forceCRTC < 0 || forceCRTC > 1)
2234 forceCRTC = -1;
2235 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2236 flatpanel = 1;
2237#ifdef CONFIG_MTRR
2238 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2239 nomtrr = 1;
2240#endif
2241 } else if (!strncmp(this_opt, "strictmode", 10)) {
2242 strictmode = 1;
2243 } else if (!strncmp(this_opt, "noaccel", 7)) {
2244 noaccel = 1;
2245 } else
2246 mode_option = this_opt;
2247 }
2248 NVTRACE_LEAVE();
2249 return 0;
2250}
2251#endif /* !MODULE */
2252
2253static struct pci_driver rivafb_driver = {
2254 .name = "rivafb",
2255 .id_table = rivafb_pci_tbl,
2256 .probe = rivafb_probe,
2257 .remove = __exit_p(rivafb_remove),
2258};
2259
2260
2261
2262/* ------------------------------------------------------------------------- *
2263 *
2264 * modularization
2265 *
2266 * ------------------------------------------------------------------------- */
2267
2268static int __devinit rivafb_init(void)
2269{
2270#ifndef MODULE
2271 char *option = NULL;
2272
2273 if (fb_get_options("rivafb", &option))
2274 return -ENODEV;
2275 rivafb_setup(option);
2276#endif
2277 return pci_register_driver(&rivafb_driver);
2278}
2279
2280
2281module_init(rivafb_init);
2282
2283#ifdef MODULE
2284static void __exit rivafb_exit(void)
2285{
2286 pci_unregister_driver(&rivafb_driver);
2287}
2288
2289module_exit(rivafb_exit);
2290#endif /* MODULE */
2291
2292module_param(noaccel, bool, 0);
2293MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2294module_param(flatpanel, int, 0);
2295MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2296module_param(forceCRTC, int, 0);
2297MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2298#ifdef CONFIG_MTRR
2299module_param(nomtrr, bool, 0);
2300MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2301#endif
2302module_param(strictmode, bool, 0);
2303MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2304
2305MODULE_AUTHOR("Ani Joshi, maintainer");
2306MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2307MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)