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[linux-block.git] / drivers / video / pxafb.c
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1da177e4
LT		 1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 */
24
25#include <linux/config.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/kernel.h>
29#include <linux/sched.h>
30#include <linux/errno.h>
31#include <linux/string.h>
32#include <linux/interrupt.h>
33#include <linux/slab.h>
34#include <linux/fb.h>
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/ioport.h>
38#include <linux/cpufreq.h>
d052d1be 39#include <linux/platform_device.h>
1da177e4
LT		 40#include <linux/dma-mapping.h>
41
42#include <asm/hardware.h>
43#include <asm/io.h>
44#include <asm/irq.h>
45#include <asm/uaccess.h>
bf1b8ab6 46#include <asm/div64.h>
1da177e4
LT		 47#include <asm/arch/pxa-regs.h>
48#include <asm/arch/bitfield.h>
49#include <asm/arch/pxafb.h>
50
51/*
52 * Complain if VAR is out of range.
53 */
54#define DEBUG_VAR 1
55
56#include "pxafb.h"
57
58/* Bits which should not be set in machine configuration structures */
59#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
60#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
61
62static void (*pxafb_backlight_power)(int);
63static void (*pxafb_lcd_power)(int);
64
65static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
66static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
67
68#ifdef CONFIG_FB_PXA_PARAMETERS
69#define PXAFB_OPTIONS_SIZE 256
70static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
71#endif
72
73static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
74{
75 unsigned long flags;
76
77 local_irq_save(flags);
78 /*
79 * We need to handle two requests being made at the same time.
80 * There are two important cases:
81 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
82 * We must perform the unblanking, which will do our REENABLE for us.
83 * 2. When we are blanking, but immediately unblank before we have
84 * blanked. We do the "REENABLE" thing here as well, just to be sure.
85 */
86 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
87 state = (u_int) -1;
88 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
89 state = C_REENABLE;
90
91 if (state != (u_int)-1) {
92 fbi->task_state = state;
93 schedule_work(&fbi->task);
94 }
95 local_irq_restore(flags);
96}
97
98static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
99{
100 chan &= 0xffff;
101 chan >>= 16 - bf->length;
102 return chan << bf->offset;
103}
104
105static int
106pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
107 u_int trans, struct fb_info *info)
108{
109 struct pxafb_info *fbi = (struct pxafb_info *)info;
110 u_int val, ret = 1;
111
112 if (regno < fbi->palette_size) {
113 if (fbi->fb.var.grayscale) {
114 val = ((blue >> 8) & 0x00ff);
115 } else {
116 val = ((red >> 0) & 0xf800);
117 val |= ((green >> 5) & 0x07e0);
118 val |= ((blue >> 11) & 0x001f);
119 }
120 fbi->palette_cpu[regno] = val;
121 ret = 0;
122 }
123 return ret;
124}
125
126static int
127pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
128 u_int trans, struct fb_info *info)
129{
130 struct pxafb_info *fbi = (struct pxafb_info *)info;
131 unsigned int val;
132 int ret = 1;
133
134 /*
135 * If inverse mode was selected, invert all the colours
136 * rather than the register number. The register number
137 * is what you poke into the framebuffer to produce the
138 * colour you requested.
139 */
140 if (fbi->cmap_inverse) {
141 red = 0xffff - red;
142 green = 0xffff - green;
143 blue = 0xffff - blue;
144 }
145
146 /*
147 * If greyscale is true, then we convert the RGB value
148 * to greyscale no matter what visual we are using.
149 */
150 if (fbi->fb.var.grayscale)
151 red = green = blue = (19595 * red + 38470 * green +
152 7471 * blue) >> 16;
153
154 switch (fbi->fb.fix.visual) {
155 case FB_VISUAL_TRUECOLOR:
156 /*
157 * 16-bit True Colour. We encode the RGB value
158 * according to the RGB bitfield information.
159 */
160 if (regno < 16) {
161 u32 *pal = fbi->fb.pseudo_palette;
162
163 val = chan_to_field(red, &fbi->fb.var.red);
164 val |= chan_to_field(green, &fbi->fb.var.green);
165 val |= chan_to_field(blue, &fbi->fb.var.blue);
166
167 pal[regno] = val;
168 ret = 0;
169 }
170 break;
171
172 case FB_VISUAL_STATIC_PSEUDOCOLOR:
173 case FB_VISUAL_PSEUDOCOLOR:
174 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
175 break;
176 }
177
178 return ret;
179}
180
181/*
182 * pxafb_bpp_to_lccr3():
183 * Convert a bits per pixel value to the correct bit pattern for LCCR3
184 */
185static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
186{
187 int ret = 0;
188 switch (var->bits_per_pixel) {
189 case 1: ret = LCCR3_1BPP; break;
190 case 2: ret = LCCR3_2BPP; break;
191 case 4: ret = LCCR3_4BPP; break;
192 case 8: ret = LCCR3_8BPP; break;
193 case 16: ret = LCCR3_16BPP; break;
194 }
195 return ret;
196}
197
198#ifdef CONFIG_CPU_FREQ
199/*
200 * pxafb_display_dma_period()
201 * Calculate the minimum period (in picoseconds) between two DMA
202 * requests for the LCD controller. If we hit this, it means we're
203 * doing nothing but LCD DMA.
204 */
205static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
206{
207 /*
208 * Period = pixclock * bits_per_byte * bytes_per_transfer
209 * / memory_bits_per_pixel;
210 */
211 return var->pixclock * 8 * 16 / var->bits_per_pixel;
212}
213
214extern unsigned int get_clk_frequency_khz(int info);
215#endif
216
217/*
218 * pxafb_check_var():
219 * Get the video params out of 'var'. If a value doesn't fit, round it up,
220 * if it's too big, return -EINVAL.
221 *
222 * Round up in the following order: bits_per_pixel, xres,
223 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
224 * bitfields, horizontal timing, vertical timing.
225 */
226static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
227{
228 struct pxafb_info *fbi = (struct pxafb_info *)info;
229
230 if (var->xres < MIN_XRES)
231 var->xres = MIN_XRES;
232 if (var->yres < MIN_YRES)
233 var->yres = MIN_YRES;
234 if (var->xres > fbi->max_xres)
2cbbb3b5 235 return -EINVAL;
1da177e4 236 if (var->yres > fbi->max_yres)
2cbbb3b5 237 return -EINVAL;
1da177e4
LT		 238 var->xres_virtual =
239 max(var->xres_virtual, var->xres);
240 var->yres_virtual =
241 max(var->yres_virtual, var->yres);
242
243 /*
244 * Setup the RGB parameters for this display.
245 *
246 * The pixel packing format is described on page 7-11 of the
247 * PXA2XX Developer's Manual.
248 */
249 if (var->bits_per_pixel == 16) {
250 var->red.offset = 11; var->red.length = 5;
251 var->green.offset = 5; var->green.length = 6;
252 var->blue.offset = 0; var->blue.length = 5;
253 var->transp.offset = var->transp.length = 0;
254 } else {
255 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
256 var->red.length = 8;
257 var->green.length = 8;
258 var->blue.length = 8;
259 var->transp.length = 0;
260 }
261
262#ifdef CONFIG_CPU_FREQ
ca5da710
RK		 263 pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
264 pxafb_display_dma_period(var),
265 get_clk_frequency_khz(0));
1da177e4
LT		 266#endif
267
268 return 0;
269}
270
271static inline void pxafb_set_truecolor(u_int is_true_color)
272{
ca5da710 273 pr_debug("pxafb: true_color = %d\n", is_true_color);
1da177e4
LT		 274 // do your machine-specific setup if needed
275}
276
277/*
278 * pxafb_set_par():
279 * Set the user defined part of the display for the specified console
280 */
281static int pxafb_set_par(struct fb_info *info)
282{
283 struct pxafb_info *fbi = (struct pxafb_info *)info;
284 struct fb_var_screeninfo *var = &info->var;
285 unsigned long palette_mem_size;
286
ca5da710 287 pr_debug("pxafb: set_par\n");
1da177e4
LT		 288
289 if (var->bits_per_pixel == 16)
290 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
291 else if (!fbi->cmap_static)
292 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
293 else {
294 /*
295 * Some people have weird ideas about wanting static
296 * pseudocolor maps. I suspect their user space
297 * applications are broken.
298 */
299 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
300 }
301
302 fbi->fb.fix.line_length = var->xres_virtual *
303 var->bits_per_pixel / 8;
304 if (var->bits_per_pixel == 16)
305 fbi->palette_size = 0;
306 else
307 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
308
309 palette_mem_size = fbi->palette_size * sizeof(u16);
310
ca5da710 311 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
1da177e4
LT		 312
313 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
314 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
315
316 /*
317 * Set (any) board control register to handle new color depth
318 */
319 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
320
321 if (fbi->fb.var.bits_per_pixel == 16)
322 fb_dealloc_cmap(&fbi->fb.cmap);
323 else
324 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
325
326 pxafb_activate_var(var, fbi);
327
328 return 0;
329}
330
331/*
332 * Formal definition of the VESA spec:
333 * On
334 * This refers to the state of the display when it is in full operation
335 * Stand-By
336 * This defines an optional operating state of minimal power reduction with
337 * the shortest recovery time
338 * Suspend
339 * This refers to a level of power management in which substantial power
340 * reduction is achieved by the display. The display can have a longer
341 * recovery time from this state than from the Stand-by state
342 * Off
343 * This indicates that the display is consuming the lowest level of power
344 * and is non-operational. Recovery from this state may optionally require
345 * the user to manually power on the monitor
346 *
347 * Now, the fbdev driver adds an additional state, (blank), where they
348 * turn off the video (maybe by colormap tricks), but don't mess with the
349 * video itself: think of it semantically between on and Stand-By.
350 *
351 * So here's what we should do in our fbdev blank routine:
352 *
353 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
354 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
355 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
356 * VESA_POWERDOWN (mode 3) Video off, front/back light off
357 *
358 * This will match the matrox implementation.
359 */
360
361/*
362 * pxafb_blank():
363 * Blank the display by setting all palette values to zero. Note, the
364 * 16 bpp mode does not really use the palette, so this will not
365 * blank the display in all modes.
366 */
367static int pxafb_blank(int blank, struct fb_info *info)
368{
369 struct pxafb_info *fbi = (struct pxafb_info *)info;
370 int i;
371
ca5da710 372 pr_debug("pxafb: blank=%d\n", blank);
1da177e4
LT		 373
374 switch (blank) {
375 case FB_BLANK_POWERDOWN:
376 case FB_BLANK_VSYNC_SUSPEND:
377 case FB_BLANK_HSYNC_SUSPEND:
378 case FB_BLANK_NORMAL:
379 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
380 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
381 for (i = 0; i < fbi->palette_size; i++)
382 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
383
384 pxafb_schedule_work(fbi, C_DISABLE);
385 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
386 break;
387
388 case FB_BLANK_UNBLANK:
389 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
390 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
391 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
392 fb_set_cmap(&fbi->fb.cmap, info);
393 pxafb_schedule_work(fbi, C_ENABLE);
394 }
395 return 0;
396}
397
216d526c 398static int pxafb_mmap(struct fb_info *info,
1da177e4
LT		 399 struct vm_area_struct *vma)
400{
401 struct pxafb_info *fbi = (struct pxafb_info *)info;
402 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
403
404 if (off < info->fix.smem_len) {
405 vma->vm_pgoff += 1;
406 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
407 fbi->map_dma, fbi->map_size);
408 }
409 return -EINVAL;
410}
411
412static struct fb_ops pxafb_ops = {
413 .owner = THIS_MODULE,
414 .fb_check_var = pxafb_check_var,
415 .fb_set_par = pxafb_set_par,
416 .fb_setcolreg = pxafb_setcolreg,
417 .fb_fillrect = cfb_fillrect,
418 .fb_copyarea = cfb_copyarea,
419 .fb_imageblit = cfb_imageblit,
420 .fb_blank = pxafb_blank,
1da177e4
LT		 421 .fb_mmap = pxafb_mmap,
422};
423
424/*
425 * Calculate the PCD value from the clock rate (in picoseconds).
426 * We take account of the PPCR clock setting.
427 * From PXA Developer's Manual:
428 *
429 * PixelClock = LCLK
430 * -------------
431 * 2 ( PCD + 1 )
432 *
433 * PCD = LCLK
434 * ------------- - 1
435 * 2(PixelClock)
436 *
437 * Where:
438 * LCLK = LCD/Memory Clock
439 * PCD = LCCR3[7:0]
440 *
441 * PixelClock here is in Hz while the pixclock argument given is the
442 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
443 *
444 * The function get_lclk_frequency_10khz returns LCLK in units of
445 * 10khz. Calling the result of this function lclk gives us the
446 * following
447 *
448 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
449 * -------------------------------------- - 1
450 * 2
451 *
452 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
453 */
454static inline unsigned int get_pcd(unsigned int pixclock)
455{
456 unsigned long long pcd;
457
458 /* FIXME: Need to take into account Double Pixel Clock mode
459 * (DPC) bit? or perhaps set it based on the various clock
460 * speeds */
461
462 pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
bf1b8ab6 463 do_div(pcd, 100000000 * 2);
1da177e4
LT		 464 /* no need for this, since we should subtract 1 anyway. they cancel */
465 /* pcd += 1; */ /* make up for integer math truncations */
466 return (unsigned int)pcd;
467}
468
ba44cd2d
RP		 469/*
470 * Some touchscreens need hsync information from the video driver to
471 * function correctly. We export it here.
472 */
473static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
474{
475 unsigned long long htime;
476
477 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
478 fbi->hsync_time=0;
479 return;
480 }
481
482 htime = (unsigned long long)get_lcdclk_frequency_10khz() * 10000;
483 do_div(htime, pcd * fbi->fb.var.hsync_len);
484 fbi->hsync_time = htime;
485}
486
487unsigned long pxafb_get_hsync_time(struct device *dev)
488{
489 struct pxafb_info *fbi = dev_get_drvdata(dev);
490
491 /* If display is blanked/suspended, hsync isn't active */
492 if (!fbi || (fbi->state != C_ENABLE))
493 return 0;
494
495 return fbi->hsync_time;
496}
497EXPORT_SYMBOL(pxafb_get_hsync_time);
498
1da177e4
LT		 499/*
500 * pxafb_activate_var():
501 * Configures LCD Controller based on entries in var parameter. Settings are
502 * only written to the controller if changes were made.
503 */
504static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
505{
506 struct pxafb_lcd_reg new_regs;
507 u_long flags;
508 u_int lines_per_panel, pcd = get_pcd(var->pixclock);
509
ca5da710 510 pr_debug("pxafb: Configuring PXA LCD\n");
1da177e4 511
ca5da710
RK		 512 pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
513 var->xres, var->hsync_len,
514 var->left_margin, var->right_margin);
515 pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
516 var->yres, var->vsync_len,
517 var->upper_margin, var->lower_margin);
518 pr_debug("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
1da177e4
LT		 519
520#if DEBUG_VAR
521 if (var->xres < 16 || var->xres > 1024)
522 printk(KERN_ERR "%s: invalid xres %d\n",
523 fbi->fb.fix.id, var->xres);
524 switch(var->bits_per_pixel) {
525 case 1:
526 case 2:
527 case 4:
528 case 8:
529 case 16:
530 break;
531 default:
532 printk(KERN_ERR "%s: invalid bit depth %d\n",
533 fbi->fb.fix.id, var->bits_per_pixel);
534 break;
535 }
536 if (var->hsync_len < 1 || var->hsync_len > 64)
537 printk(KERN_ERR "%s: invalid hsync_len %d\n",
538 fbi->fb.fix.id, var->hsync_len);
539 if (var->left_margin < 1 || var->left_margin > 255)
540 printk(KERN_ERR "%s: invalid left_margin %d\n",
541 fbi->fb.fix.id, var->left_margin);
542 if (var->right_margin < 1 || var->right_margin > 255)
543 printk(KERN_ERR "%s: invalid right_margin %d\n",
544 fbi->fb.fix.id, var->right_margin);
545 if (var->yres < 1 || var->yres > 1024)
546 printk(KERN_ERR "%s: invalid yres %d\n",
547 fbi->fb.fix.id, var->yres);
548 if (var->vsync_len < 1 || var->vsync_len > 64)
549 printk(KERN_ERR "%s: invalid vsync_len %d\n",
550 fbi->fb.fix.id, var->vsync_len);
551 if (var->upper_margin < 0 || var->upper_margin > 255)
552 printk(KERN_ERR "%s: invalid upper_margin %d\n",
553 fbi->fb.fix.id, var->upper_margin);
554 if (var->lower_margin < 0 || var->lower_margin > 255)
555 printk(KERN_ERR "%s: invalid lower_margin %d\n",
556 fbi->fb.fix.id, var->lower_margin);
557#endif
558
559 new_regs.lccr0 = fbi->lccr0 |
560 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
561 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
562
563 new_regs.lccr1 =
564 LCCR1_DisWdth(var->xres) +
565 LCCR1_HorSnchWdth(var->hsync_len) +
566 LCCR1_BegLnDel(var->left_margin) +
567 LCCR1_EndLnDel(var->right_margin);
568
569 /*
570 * If we have a dual scan LCD, we need to halve
571 * the YRES parameter.
572 */
573 lines_per_panel = var->yres;
574 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
575 lines_per_panel /= 2;
576
577 new_regs.lccr2 =
578 LCCR2_DisHght(lines_per_panel) +
579 LCCR2_VrtSnchWdth(var->vsync_len) +
580 LCCR2_BegFrmDel(var->upper_margin) +
581 LCCR2_EndFrmDel(var->lower_margin);
582
583 new_regs.lccr3 = fbi->lccr3 |
584 pxafb_bpp_to_lccr3(var) |
585 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
586 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
587
588 if (pcd)
589 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
590
ca5da710
RK		 591 pr_debug("nlccr0 = 0x%08x\n", new_regs.lccr0);
592 pr_debug("nlccr1 = 0x%08x\n", new_regs.lccr1);
593 pr_debug("nlccr2 = 0x%08x\n", new_regs.lccr2);
594 pr_debug("nlccr3 = 0x%08x\n", new_regs.lccr3);
1da177e4
LT		 595
596 /* Update shadow copy atomically */
597 local_irq_save(flags);
598
599 /* setup dma descriptors */
600 fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
601 fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
602 fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
603
604 fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
605 fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
606 fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
607
608#define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
609
610 /* populate descriptors */
611 fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
612 fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
613 fbi->dmadesc_fblow_cpu->fidr = 0;
614 fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
615
616 fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
617
618 fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
619 fbi->dmadesc_fbhigh_cpu->fidr = 0;
620 fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
621
622 fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
623 fbi->dmadesc_palette_cpu->fidr = 0;
624 fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
625
626 if (var->bits_per_pixel == 16) {
627 /* palette shouldn't be loaded in true-color mode */
628 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
629 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
630 /* init it to something, even though we won't be using it */
631 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
632 } else {
633 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
634 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
635 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
636 }
637
638#if 0
ca5da710
RK		 639 pr_debug("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
640 pr_debug("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
641 pr_debug("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
642 pr_debug("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
643 pr_debug("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
644 pr_debug("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
645
646 pr_debug("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
647 pr_debug("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
648 pr_debug("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
649
650 pr_debug("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
651 pr_debug("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
652 pr_debug("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
653
654 pr_debug("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
655 pr_debug("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
656 pr_debug("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
1da177e4
LT		 657#endif
658
659 fbi->reg_lccr0 = new_regs.lccr0;
660 fbi->reg_lccr1 = new_regs.lccr1;
661 fbi->reg_lccr2 = new_regs.lccr2;
662 fbi->reg_lccr3 = new_regs.lccr3;
ba44cd2d 663 set_hsync_time(fbi, pcd);
1da177e4
LT		 664 local_irq_restore(flags);
665
666 /*
667 * Only update the registers if the controller is enabled
668 * and something has changed.
669 */
670 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
671 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
672 (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1))
673 pxafb_schedule_work(fbi, C_REENABLE);
674
675 return 0;
676}
677
678/*
679 * NOTE! The following functions are purely helpers for set_ctrlr_state.
680 * Do not call them directly; set_ctrlr_state does the correct serialisation
681 * to ensure that things happen in the right way 100% of time time.
682 * -- rmk
683 */
684static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
685{
ca5da710 686 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1da177e4
LT		 687
688 if (pxafb_backlight_power)
689 pxafb_backlight_power(on);
690}
691
692static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
693{
ca5da710 694 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1da177e4
LT		 695
696 if (pxafb_lcd_power)
697 pxafb_lcd_power(on);
698}
699
700static void pxafb_setup_gpio(struct pxafb_info *fbi)
701{
702 int gpio, ldd_bits;
703 unsigned int lccr0 = fbi->lccr0;
704
705 /*
706 * setup is based on type of panel supported
707 */
708
709 /* 4 bit interface */
710 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
711 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
712 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
713 ldd_bits = 4;
714
715 /* 8 bit interface */
716 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
717 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
718 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
719 (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
720 ldd_bits = 8;
721
722 /* 16 bit interface */
723 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
724 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
725 ldd_bits = 16;
726
727 else {
728 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
729 return;
730 }
731
732 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
733 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
734 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
735 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
736 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
737 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
738}
739
740static void pxafb_enable_controller(struct pxafb_info *fbi)
741{
ca5da710
RK		 742 pr_debug("pxafb: Enabling LCD controller\n");
743 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
744 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
745 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
746 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
747 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
748 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1da177e4 749
8d372266
NP		 750 /* enable LCD controller clock */
751 pxa_set_cken(CKEN16_LCD, 1);
752
1da177e4
LT		 753 /* Sequence from 11.7.10 */
754 LCCR3 = fbi->reg_lccr3;
755 LCCR2 = fbi->reg_lccr2;
756 LCCR1 = fbi->reg_lccr1;
757 LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
758
759 FDADR0 = fbi->fdadr0;
760 FDADR1 = fbi->fdadr1;
761 LCCR0 |= LCCR0_ENB;
762
ca5da710
RK		 763 pr_debug("FDADR0 0x%08x\n", (unsigned int) FDADR0);
764 pr_debug("FDADR1 0x%08x\n", (unsigned int) FDADR1);
765 pr_debug("LCCR0 0x%08x\n", (unsigned int) LCCR0);
766 pr_debug("LCCR1 0x%08x\n", (unsigned int) LCCR1);
767 pr_debug("LCCR2 0x%08x\n", (unsigned int) LCCR2);
768 pr_debug("LCCR3 0x%08x\n", (unsigned int) LCCR3);
1da177e4
LT		 769}
770
771static void pxafb_disable_controller(struct pxafb_info *fbi)
772{
773 DECLARE_WAITQUEUE(wait, current);
774
ca5da710 775 pr_debug("pxafb: disabling LCD controller\n");
1da177e4
LT		 776
777 set_current_state(TASK_UNINTERRUPTIBLE);
778 add_wait_queue(&fbi->ctrlr_wait, &wait);
779
780 LCSR = 0xffffffff; /* Clear LCD Status Register */
781 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
782 LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */
783
2cbbb3b5 784 schedule_timeout(200 * HZ / 1000);
1da177e4 785 remove_wait_queue(&fbi->ctrlr_wait, &wait);
8d372266
NP		 786
787 /* disable LCD controller clock */
788 pxa_set_cken(CKEN16_LCD, 0);
1da177e4
LT		 789}
790
791/*
792 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
793 */
794static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
795{
796 struct pxafb_info *fbi = dev_id;
797 unsigned int lcsr = LCSR;
798
799 if (lcsr & LCSR_LDD) {
800 LCCR0 |= LCCR0_LDM;
801 wake_up(&fbi->ctrlr_wait);
802 }
803
804 LCSR = lcsr;
805 return IRQ_HANDLED;
806}
807
808/*
809 * This function must be called from task context only, since it will
810 * sleep when disabling the LCD controller, or if we get two contending
811 * processes trying to alter state.
812 */
813static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
814{
815 u_int old_state;
816
817 down(&fbi->ctrlr_sem);
818
819 old_state = fbi->state;
820
821 /*
822 * Hack around fbcon initialisation.
823 */
824 if (old_state == C_STARTUP && state == C_REENABLE)
825 state = C_ENABLE;
826
827 switch (state) {
828 case C_DISABLE_CLKCHANGE:
829 /*
830 * Disable controller for clock change. If the
831 * controller is already disabled, then do nothing.
832 */
833 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
834 fbi->state = state;
835 //TODO __pxafb_lcd_power(fbi, 0);
836 pxafb_disable_controller(fbi);
837 }
838 break;
839
840 case C_DISABLE_PM:
841 case C_DISABLE:
842 /*
843 * Disable controller
844 */
845 if (old_state != C_DISABLE) {
846 fbi->state = state;
847 __pxafb_backlight_power(fbi, 0);
848 __pxafb_lcd_power(fbi, 0);
849 if (old_state != C_DISABLE_CLKCHANGE)
850 pxafb_disable_controller(fbi);
851 }
852 break;
853
854 case C_ENABLE_CLKCHANGE:
855 /*
856 * Enable the controller after clock change. Only
857 * do this if we were disabled for the clock change.
858 */
859 if (old_state == C_DISABLE_CLKCHANGE) {
860 fbi->state = C_ENABLE;
861 pxafb_enable_controller(fbi);
862 //TODO __pxafb_lcd_power(fbi, 1);
863 }
864 break;
865
866 case C_REENABLE:
867 /*
868 * Re-enable the controller only if it was already
869 * enabled. This is so we reprogram the control
870 * registers.
871 */
872 if (old_state == C_ENABLE) {
873 pxafb_disable_controller(fbi);
874 pxafb_setup_gpio(fbi);
875 pxafb_enable_controller(fbi);
876 }
877 break;
878
879 case C_ENABLE_PM:
880 /*
881 * Re-enable the controller after PM. This is not
882 * perfect - think about the case where we were doing
883 * a clock change, and we suspended half-way through.
884 */
885 if (old_state != C_DISABLE_PM)
886 break;
887 /* fall through */
888
889 case C_ENABLE:
890 /*
891 * Power up the LCD screen, enable controller, and
892 * turn on the backlight.
893 */
894 if (old_state != C_ENABLE) {
895 fbi->state = C_ENABLE;
896 pxafb_setup_gpio(fbi);
897 pxafb_enable_controller(fbi);
898 __pxafb_lcd_power(fbi, 1);
899 __pxafb_backlight_power(fbi, 1);
900 }
901 break;
902 }
903 up(&fbi->ctrlr_sem);
904}
905
906/*
907 * Our LCD controller task (which is called when we blank or unblank)
908 * via keventd.
909 */
910static void pxafb_task(void *dummy)
911{
912 struct pxafb_info *fbi = dummy;
913 u_int state = xchg(&fbi->task_state, -1);
914
915 set_ctrlr_state(fbi, state);
916}
917
918#ifdef CONFIG_CPU_FREQ
919/*
920 * CPU clock speed change handler. We need to adjust the LCD timing
921 * parameters when the CPU clock is adjusted by the power management
922 * subsystem.
923 *
924 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
925 */
926static int
927pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
928{
929 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
930 //TODO struct cpufreq_freqs *f = data;
931 u_int pcd;
932
933 switch (val) {
934 case CPUFREQ_PRECHANGE:
935 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
936 break;
937
938 case CPUFREQ_POSTCHANGE:
939 pcd = get_pcd(fbi->fb.var.pixclock);
ba44cd2d 940 set_hsync_time(fbi, pcd);
1da177e4
LT		 941 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
942 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
943 break;
944 }
945 return 0;
946}
947
948static int
949pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
950{
951 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
952 struct fb_var_screeninfo *var = &fbi->fb.var;
953 struct cpufreq_policy *policy = data;
954
955 switch (val) {
956 case CPUFREQ_ADJUST:
957 case CPUFREQ_INCOMPATIBLE:
958 printk(KERN_DEBUG "min dma period: %d ps, "
959 "new clock %d kHz\n", pxafb_display_dma_period(var),
960 policy->max);
961 // TODO: fill in min/max values
962 break;
963#if 0
964 case CPUFREQ_NOTIFY:
965 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
966 do {} while(0);
967 /* todo: panic if min/max values aren't fulfilled
968 * [can't really happen unless there's a bug in the
969 * CPU policy verification process *
970 */
971 break;
972#endif
973 }
974 return 0;
975}
976#endif
977
978#ifdef CONFIG_PM
979/*
980 * Power management hooks. Note that we won't be called from IRQ context,
981 * unlike the blank functions above, so we may sleep.
982 */
3ae5eaec 983static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 984{
3ae5eaec 985 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 986
9480e307 987 set_ctrlr_state(fbi, C_DISABLE_PM);
1da177e4
LT		 988 return 0;
989}
990
3ae5eaec 991static int pxafb_resume(struct platform_device *dev)
1da177e4 992{
3ae5eaec 993 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 994
9480e307 995 set_ctrlr_state(fbi, C_ENABLE_PM);
1da177e4
LT		 996 return 0;
997}
998#else
999#define pxafb_suspend NULL
1000#define pxafb_resume NULL
1001#endif
1002
1003/*
1004 * pxafb_map_video_memory():
1005 * Allocates the DRAM memory for the frame buffer. This buffer is
1006 * remapped into a non-cached, non-buffered, memory region to
1007 * allow palette and pixel writes to occur without flushing the
1008 * cache. Once this area is remapped, all virtual memory
1009 * access to the video memory should occur at the new region.
1010 */
1011static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1012{
1013 u_long palette_mem_size;
1014
1015 /*
1016 * We reserve one page for the palette, plus the size
1017 * of the framebuffer.
1018 */
1019 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1020 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1021 &fbi->map_dma, GFP_KERNEL);
1022
1023 if (fbi->map_cpu) {
1024 /* prevent initial garbage on screen */
1025 memset(fbi->map_cpu, 0, fbi->map_size);
1026 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1027 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1028 /*
1029 * FIXME: this is actually the wrong thing to place in
1030 * smem_start. But fbdev suffers from the problem that
1031 * it needs an API which doesn't exist (in this case,
1032 * dma_writecombine_mmap)
1033 */
1034 fbi->fb.fix.smem_start = fbi->screen_dma;
1035
1036 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1037
1038 palette_mem_size = fbi->palette_size * sizeof(u16);
ca5da710 1039 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
1da177e4
LT		 1040
1041 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1042 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1043 }
1044
1045 return fbi->map_cpu ? 0 : -ENOMEM;
1046}
1047
1048static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1049{
1050 struct pxafb_info *fbi;
1051 void *addr;
1052 struct pxafb_mach_info *inf = dev->platform_data;
1053
1054 /* Alloc the pxafb_info and pseudo_palette in one step */
1055 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1056 if (!fbi)
1057 return NULL;
1058
1059 memset(fbi, 0, sizeof(struct pxafb_info));
1060 fbi->dev = dev;
1061
1062 strcpy(fbi->fb.fix.id, PXA_NAME);
1063
1064 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1065 fbi->fb.fix.type_aux = 0;
1066 fbi->fb.fix.xpanstep = 0;
1067 fbi->fb.fix.ypanstep = 0;
1068 fbi->fb.fix.ywrapstep = 0;
1069 fbi->fb.fix.accel = FB_ACCEL_NONE;
1070
1071 fbi->fb.var.nonstd = 0;
1072 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1073 fbi->fb.var.height = -1;
1074 fbi->fb.var.width = -1;
1075 fbi->fb.var.accel_flags = 0;
1076 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1077
1078 fbi->fb.fbops = &pxafb_ops;
1079 fbi->fb.flags = FBINFO_DEFAULT;
1080 fbi->fb.node = -1;
1081
1082 addr = fbi;
1083 addr = addr + sizeof(struct pxafb_info);
1084 fbi->fb.pseudo_palette = addr;
1085
1086 fbi->max_xres = inf->xres;
1087 fbi->fb.var.xres = inf->xres;
1088 fbi->fb.var.xres_virtual = inf->xres;
1089 fbi->max_yres = inf->yres;
1090 fbi->fb.var.yres = inf->yres;
1091 fbi->fb.var.yres_virtual = inf->yres;
1092 fbi->max_bpp = inf->bpp;
1093 fbi->fb.var.bits_per_pixel = inf->bpp;
1094 fbi->fb.var.pixclock = inf->pixclock;
1095 fbi->fb.var.hsync_len = inf->hsync_len;
1096 fbi->fb.var.left_margin = inf->left_margin;
1097 fbi->fb.var.right_margin = inf->right_margin;
1098 fbi->fb.var.vsync_len = inf->vsync_len;
1099 fbi->fb.var.upper_margin = inf->upper_margin;
1100 fbi->fb.var.lower_margin = inf->lower_margin;
1101 fbi->fb.var.sync = inf->sync;
1102 fbi->fb.var.grayscale = inf->cmap_greyscale;
1103 fbi->cmap_inverse = inf->cmap_inverse;
1104 fbi->cmap_static = inf->cmap_static;
1105 fbi->lccr0 = inf->lccr0;
1106 fbi->lccr3 = inf->lccr3;
1107 fbi->state = C_STARTUP;
1108 fbi->task_state = (u_char)-1;
1109 fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
1110 fbi->max_bpp / 8;
1111
1112 init_waitqueue_head(&fbi->ctrlr_wait);
1113 INIT_WORK(&fbi->task, pxafb_task, fbi);
1114 init_MUTEX(&fbi->ctrlr_sem);
1115
1116 return fbi;
1117}
1118
1119#ifdef CONFIG_FB_PXA_PARAMETERS
1120static int __init pxafb_parse_options(struct device *dev, char *options)
1121{
1122 struct pxafb_mach_info *inf = dev->platform_data;
1123 char *this_opt;
1124
1125 if (!options || !*options)
1126 return 0;
1127
1128 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1129
1130 /* could be made table driven or similar?... */
1131 while ((this_opt = strsep(&options, ",")) != NULL) {
1132 if (!strncmp(this_opt, "mode:", 5)) {
1133 const char *name = this_opt+5;
1134 unsigned int namelen = strlen(name);
1135 int res_specified = 0, bpp_specified = 0;
1136 unsigned int xres = 0, yres = 0, bpp = 0;
1137 int yres_specified = 0;
1138 int i;
1139 for (i = namelen-1; i >= 0; i--) {
1140 switch (name[i]) {
1141 case '-':
1142 namelen = i;
1143 if (!bpp_specified && !yres_specified) {
1144 bpp = simple_strtoul(&name[i+1], NULL, 0);
1145 bpp_specified = 1;
1146 } else
1147 goto done;
1148 break;
1149 case 'x':
1150 if (!yres_specified) {
1151 yres = simple_strtoul(&name[i+1], NULL, 0);
1152 yres_specified = 1;
1153 } else
1154 goto done;
1155 break;
1156 case '0'...'9':
1157 break;
1158 default:
1159 goto done;
1160 }
1161 }
1162 if (i < 0 && yres_specified) {
1163 xres = simple_strtoul(name, NULL, 0);
1164 res_specified = 1;
1165 }
1166 done:
1167 if (res_specified) {
1168 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1169 inf->xres = xres; inf->yres = yres;
1170 }
1171 if (bpp_specified)
1172 switch (bpp) {
1173 case 1:
1174 case 2:
1175 case 4:
1176 case 8:
1177 case 16:
1178 inf->bpp = bpp;
1179 dev_info(dev, "overriding bit depth: %d\n", bpp);
1180 break;
1181 default:
1182 dev_err(dev, "Depth %d is not valid\n", bpp);
1183 }
1184 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1185 inf->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1186 dev_info(dev, "override pixclock: %ld\n", inf->pixclock);
1187 } else if (!strncmp(this_opt, "left:", 5)) {
1188 inf->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1189 dev_info(dev, "override left: %u\n", inf->left_margin);
1190 } else if (!strncmp(this_opt, "right:", 6)) {
1191 inf->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1192 dev_info(dev, "override right: %u\n", inf->right_margin);
1193 } else if (!strncmp(this_opt, "upper:", 6)) {
1194 inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1195 dev_info(dev, "override upper: %u\n", inf->upper_margin);
1196 } else if (!strncmp(this_opt, "lower:", 6)) {
1197 inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1198 dev_info(dev, "override lower: %u\n", inf->lower_margin);
1199 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1200 inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1201 dev_info(dev, "override hsynclen: %u\n", inf->hsync_len);
1202 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1203 inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1204 dev_info(dev, "override vsynclen: %u\n", inf->vsync_len);
1205 } else if (!strncmp(this_opt, "hsync:", 6)) {
1206 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1207 dev_info(dev, "override hsync: Active Low\n");
1208 inf->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1209 } else {
1210 dev_info(dev, "override hsync: Active High\n");
1211 inf->sync |= FB_SYNC_HOR_HIGH_ACT;
1212 }
1213 } else if (!strncmp(this_opt, "vsync:", 6)) {
1214 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1215 dev_info(dev, "override vsync: Active Low\n");
1216 inf->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1217 } else {
1218 dev_info(dev, "override vsync: Active High\n");
1219 inf->sync |= FB_SYNC_VERT_HIGH_ACT;
1220 }
1221 } else if (!strncmp(this_opt, "dpc:", 4)) {
1222 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1223 dev_info(dev, "override double pixel clock: false\n");
1224 inf->lccr3 &= ~LCCR3_DPC;
1225 } else {
1226 dev_info(dev, "override double pixel clock: true\n");
1227 inf->lccr3 |= LCCR3_DPC;
1228 }
1229 } else if (!strncmp(this_opt, "outputen:", 9)) {
1230 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1231 dev_info(dev, "override output enable: active low\n");
1232 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1233 } else {
1234 dev_info(dev, "override output enable: active high\n");
1235 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1236 }
1237 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1238 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1239 dev_info(dev, "override pixel clock polarity: falling edge\n");
1240 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1241 } else {
1242 dev_info(dev, "override pixel clock polarity: rising edge\n");
1243 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1244 }
1245 } else if (!strncmp(this_opt, "color", 5)) {
1246 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1247 } else if (!strncmp(this_opt, "mono", 4)) {
1248 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1249 } else if (!strncmp(this_opt, "active", 6)) {
1250 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1251 } else if (!strncmp(this_opt, "passive", 7)) {
1252 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1253 } else if (!strncmp(this_opt, "single", 6)) {
1254 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1255 } else if (!strncmp(this_opt, "dual", 4)) {
1256 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1257 } else if (!strncmp(this_opt, "4pix", 4)) {
1258 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1259 } else if (!strncmp(this_opt, "8pix", 4)) {
1260 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1261 } else {
1262 dev_err(dev, "unknown option: %s\n", this_opt);
1263 return -EINVAL;
1264 }
1265 }
1266 return 0;
1267
1268}
1269#endif
1270
3ae5eaec 1271int __init pxafb_probe(struct platform_device *dev)
1da177e4
LT		 1272{
1273 struct pxafb_info *fbi;
1274 struct pxafb_mach_info *inf;
1275 int ret;
1276
2cbbb3b5 1277 dev_dbg(&dev->dev, "pxafb_probe\n");
1da177e4 1278
3ae5eaec 1279 inf = dev->dev.platform_data;
1da177e4
LT		 1280 ret = -ENOMEM;
1281 fbi = NULL;
1282 if (!inf)
1283 goto failed;
1284
1285#ifdef CONFIG_FB_PXA_PARAMETERS
3ae5eaec 1286 ret = pxafb_parse_options(&dev->dev, g_options);
1da177e4
LT		 1287 if (ret < 0)
1288 goto failed;
1289#endif
1290
1291#ifdef DEBUG_VAR
1292 /* Check for various illegal bit-combinations. Currently only
1293 * a warning is given. */
1294
1295 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
3ae5eaec 1296 dev_warn(&dev->dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1da177e4
LT		 1297 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1298 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
3ae5eaec 1299 dev_warn(&dev->dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1da177e4
LT		 1300 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1301 if (inf->lccr0 & LCCR0_DPD &&
1302 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1303 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1304 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
3ae5eaec 1305 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1da177e4
LT		 1306 " single panel mode\n");
1307 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1308 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
3ae5eaec 1309 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1da177e4
LT		 1310 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1311 (inf->upper_margin || inf->lower_margin))
3ae5eaec 1312 dev_warn(&dev->dev, "Upper and lower margins must be 0 in passive mode\n");
1da177e4
LT		 1313#endif
1314
3ae5eaec 1315 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp);
1da177e4 1316 if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) {
3ae5eaec 1317 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1da177e4
LT		 1318 ret = -EINVAL;
1319 goto failed;
1320 }
1321 pxafb_backlight_power = inf->pxafb_backlight_power;
1322 pxafb_lcd_power = inf->pxafb_lcd_power;
3ae5eaec 1323 fbi = pxafb_init_fbinfo(&dev->dev);
1da177e4 1324 if (!fbi) {
3ae5eaec 1325 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1da177e4
LT		 1326 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1327 goto failed;
1328 }
1329
1330 /* Initialize video memory */
1331 ret = pxafb_map_video_memory(fbi);
1332 if (ret) {
3ae5eaec 1333 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1da177e4
LT		 1334 ret = -ENOMEM;
1335 goto failed;
1336 }
1da177e4
LT		 1337
1338 ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi);
1339 if (ret) {
3ae5eaec 1340 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1da177e4
LT		 1341 ret = -EBUSY;
1342 goto failed;
1343 }
1344
1345 /*
1346 * This makes sure that our colour bitfield
1347 * descriptors are correctly initialised.
1348 */
1349 pxafb_check_var(&fbi->fb.var, &fbi->fb);
1350 pxafb_set_par(&fbi->fb);
1351
3ae5eaec 1352 platform_set_drvdata(dev, fbi);
1da177e4
LT		 1353
1354 ret = register_framebuffer(&fbi->fb);
1355 if (ret < 0) {
3ae5eaec 1356 dev_err(&dev->dev, "Failed to register framebuffer device: %d\n", ret);
1da177e4
LT		 1357 goto failed;
1358 }
1359
1360#ifdef CONFIG_PM
1361 // TODO
1362#endif
1363
1364#ifdef CONFIG_CPU_FREQ
1365 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1366 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1367 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1368 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1369#endif
1370
1371 /*
1372 * Ok, now enable the LCD controller
1373 */
1374 set_ctrlr_state(fbi, C_ENABLE);
1375
1376 return 0;
1377
1378failed:
3ae5eaec 1379 platform_set_drvdata(dev, NULL);
1da177e4
LT		 1380 kfree(fbi);
1381 return ret;
1382}
1383
3ae5eaec 1384static struct platform_driver pxafb_driver = {
1da177e4
LT		 1385 .probe = pxafb_probe,
1386#ifdef CONFIG_PM
1387 .suspend = pxafb_suspend,
1388 .resume = pxafb_resume,
1389#endif
3ae5eaec
RK		 1390 .driver = {
1391 .name = "pxa2xx-fb",
1392 },
1da177e4
LT		 1393};
1394
1395#ifndef MODULE
1396int __devinit pxafb_setup(char *options)
1397{
1398# ifdef CONFIG_FB_PXA_PARAMETERS
fb79ffa4
OR		 1399 if (options)
1400 strlcpy(g_options, options, sizeof(g_options));
1da177e4
LT		 1401# endif
1402 return 0;
1403}
1404#else
1405# ifdef CONFIG_FB_PXA_PARAMETERS
1406module_param_string(options, g_options, sizeof(g_options), 0);
1407MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1408# endif
1409#endif
1410
1411int __devinit pxafb_init(void)
1412{
1413#ifndef MODULE
1414 char *option = NULL;
1415
1416 if (fb_get_options("pxafb", &option))
1417 return -ENODEV;
1418 pxafb_setup(option);
1419#endif
3ae5eaec 1420 return platform_driver_register(&pxafb_driver);
1da177e4
LT		 1421}
1422
1423module_init(pxafb_init);
1424
1425MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1426MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)